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peisongxiao
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rose
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a94823b44a71c464c383e7a7b827efb015ac5f54
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3 Commits
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Peisong Xiao
a94823b44a
finished the hub's logic, half done with the interfaces, and hopefully working on pi logic soon
2025-06-05 22:38:26 -04:00
Peisong Xiao
dac3140829
heavy work in progress
2025-05-21 21:04:57 -04:00
Peisong Xiao
1f7c47a1fb
WORKING PROGRESS. revamped the files and naming, so git is a bit confused
...
mem_hub.sv -> hub.sv spi_slave.sv -> interface.sv
2025-05-17 22:06:41 -04:00