147 lines
5.0 KiB
Systemverilog
147 lines
5.0 KiB
Systemverilog
// NOTE: The first byte is used for syncing due to using different clock domains
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`include <params.svh>
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module spi_interface(
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input logic rst,
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input logic sys_clk,
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input logic mosi,
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input logic cs,
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input logic sclk,
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output logic miso,
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output logic [7:0] rx_byte,
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output logic rx_valid,
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input logic rx_ready,
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output logic [PACKET_ADDR_LEN - 1:0] rx_pkt_addr,
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input logic [7:0] tx_byte,
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input logic tx_valid,
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output logic tx_ready,
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output logic [PACKET_ADDR_LEN - 1:0] tx_pkt_addr,
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output logic [QUEUE_ADDR_LEN - 1:0] tx_queue_addr,
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input logic [QUEUE_ADDR_LEN - 1:0] tx_new_queue,
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input logic tx_new_queue_valid,
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output logic tx_new_queue_ready,
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input logic free_queue_empty);
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timeunit 1ns;
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timeprecision 1ps;
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// SPI logic
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logic sclk_rising_edge;
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logic sclk_falling_edge;
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async_get_clk_edges sync (.rst(rst),
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.ext_clk(sclk),
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.sys_clk(sys_clk),
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.clk_rising_edge(sclk_rising_edge),
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.clk_falling_edge(sclk_falling_edge));
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shortint bit_cnt = 0;
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logic [7:0] rx_shift;
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logic [7:0] tx_shift = 8'b00101010;
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logic [7:0] rx_buff = '0;
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logic byte_ready = 0;
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always_ff @ (posedge sclk_rising_edge or posedge rst) begin
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if (rst) begin
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rx_shift <= '0;
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rx_buff <= '0;
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bit_cnt <= '0;
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byte_ready <= 0;
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end
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else begin
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if (cs) begin
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rx_shift <= 0;
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rx_buff <= 0;
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bit_cnt <= 0;
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end else begin
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rx_shift <= {rx_shift[6:0], mosi};
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bit_cnt <= bit_cnt + 1;
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if (bit_cnt == 7) begin
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bit_cnt <= 0;
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rx_buff <= {rx_shift[6:0], mosi};
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byte_ready <= 1;
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end else begin
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byte_ready <= 0;
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end
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end // else: !if(cs)
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end // else: !if(rst)
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end // always_ff @ (posedge sclk)
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shortint idle_cntdn;
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logic rx_drained;
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always_ff @ (posedge sys_clk or rst) begin
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if (rst) begin
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rx_drained <= 0;
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rx_pkt_addr <= '1;
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rx_byte <= '0;
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rx_valid <= 0;
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idle_cntdn <= 0;
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end else begin
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if (!rx_drained && byte_ready) begin
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rx_byte <= rx_buff;
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rx_valid <= 1;
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idle_cntdn <= INTERFACE_IDLE_COUNTDOWN;
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rx_drained <= 1;
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rx_pkt_addr <= rx_pkt_addr + 1;
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end else if (!byte_ready) begin
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rx_drained <= 0;
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if (!(|idle_cntdn)) begin
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rx_valid <= 0;
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end else begin
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idle_cntdn <= idle_cntdn - 1;
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end
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end
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end
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end
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always_ff @ (posedge sclk_falling_edge or rst) begin
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if (rst) begin
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tx_shift <= 8'b00101010;
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end else begin
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if (cs) begin
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tx_shift <= 0;
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end else begin
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if (bit_cnt == 0) begin
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tx_shift <= rx_buff[7:0];
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end else begin
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tx_shift <= {tx_shift[6:0], 1'b0};
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end
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end
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end // else: !if(rst)
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$display("last bit sent: %b", miso);
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$display("[%0d] current tx_shift: %b", $time, tx_shift);
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$display("-----------------------------------------");
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end // always_ff @ (negedge sclk)
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assign miso = tx_shift[7];
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endmodule // spi_interface
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module async_get_clk_edges(
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input logic rst,
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input logic ext_clk,
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input logic sys_clk,
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output logic clk_rising_edge,
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output logic clk_falling_edge);
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timeunit 1ns;
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timeprecision 1ps;
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logic sync_0 = 0;
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logic sync_1 = 0;
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always_ff @ (posedge sys_clk) begin
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if (rst) begin
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sync_0 <= 0;
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sync_1 <= 0;
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end else begin
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sync_0 <= ext_clk;
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sync_1 <= sync_0;
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end
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end
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assign clk_rising_edge = sync_0 & ~sync_1;
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assign clk_falling_edge = ~sync_0 & sync_1;
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endmodule // async_get_clk_edges
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