018b7a3fcf
minor change: revised directory structure, added MIT license
Peisong Xiao2025-06-06 16:37:26 -04:00
a94823b44a
finished the hub's logic, half done with the interfaces, and hopefully working on pi logic soon
Peisong Xiao2025-06-05 22:38:26 -04:00
f61de84b4a
work in progress, major overhaul for design, see devlogs for details. Also added the first version of the style guide
Peisong Xiao2025-05-29 00:18:06 -04:00
1f7c47a1fb
WORKING PROGRESS. revamped the files and naming, so git is a bit confused mem_hub.sv -> hub.sv spi_slave.sv -> interface.sv
Peisong Xiao2025-05-17 22:06:41 -04:00
a83a8f9f95
Fix: indent to 4 spaces (3 spaces is pure evil)
Peisong Xiao2025-05-15 20:03:54 -04:00
b26a716ccf
began work on the central routing logic, updated some documentation
Peisong Xiao2025-05-14 22:27:40 -04:00
24bf28db9d
initial commit: figuring out SPI on the Tang Primer 20K, already 3 devlogs, will commit on a per-devlog/document change basis
Peisong Xiao2025-05-11 00:35:24 -04:00
Peisong Xiao