a94823b44afinished the hub's logic, half done with the interfaces, and hopefully working on pi logic soonPeisong Xiao2025-06-05 22:38:26 -04:00
f61de84b4awork in progress, major overhaul for design, see devlogs for details. Also added the first version of the style guidePeisong Xiao2025-05-29 00:18:06 -04:00
1f7c47a1fbWORKING PROGRESS. revamped the files and naming, so git is a bit confused mem_hub.sv -> hub.sv spi_slave.sv -> interface.svPeisong Xiao2025-05-17 22:06:41 -04:00
a83a8f9f95Fix: indent to 4 spaces (3 spaces is pure evil)Peisong Xiao2025-05-15 20:03:54 -04:00
b26a716ccfbegan work on the central routing logic, updated some documentationPeisong Xiao2025-05-14 22:27:40 -04:00
24bf28db9dinitial commit: figuring out SPI on the Tang Primer 20K, already 3 devlogs, will commit on a per-devlog/document change basisPeisong Xiao2025-05-11 00:35:24 -04:00
Peisong Xiao