244 lines
7.3 KiB
Systemverilog
244 lines
7.3 KiB
Systemverilog
// NOTE: The first byte is used for syncing due to using different clock domains
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`define SYNC_2FF
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module spi_interface(
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input logic rst,
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input logic sys_clk,
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input logic mosi,
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input logic cs,
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input logic sclk,
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input logic rx_ready,
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input logic tx_valid,
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input logic [7:0] tx_byte,
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input logic [1:0] tx_src,
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input logic [1:0] packet_size,
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output logic miso,
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output logic tx_ready,
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output logic rx_valid,
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output logic [7:0] rx_byte,
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output logic [7:0] rx_dest,
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output logic [7:0] rx_cmd,
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output logic rx_cmd_valid);
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timeunit 1ns;
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timeprecision 1ps;
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// SPI logic
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logic sclk_rising_edge;
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logic sclk_falling_edge;
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async_get_clk_edges sync (.rst(rst),
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.ext_clk(sclk),
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.sys_clk(sys_clk),
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.clk_rising_edge(sclk_rising_edge),
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.clk_falling_edge(sclk_falling_edge));
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int bit_cnt = 0;
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logic [7:0] rx_shift;
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logic [7:0] tx_shift = 8'b00101010;
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logic [7:0] rx_buff = '0;
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logic byte_ready = 0;
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always_ff @ (posedge sclk_rising_edge or posedge rst) begin
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if (rst) begin
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rx_shift <= '0;
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rx_buff <= '0;
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bit_cnt <= '0;
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byte_ready <= 0;
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end
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else begin
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if (cs) begin
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rx_shift <= 0;
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rx_buff <= 0;
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bit_cnt <= 0;
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end else begin
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rx_shift <= {rx_shift[6:0], mosi};
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bit_cnt <= bit_cnt + 1;
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if (bit_cnt == 7) begin
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bit_cnt <= 0;
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rx_buff <= {rx_shift[6:0], mosi};
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byte_ready <= 1;
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end else
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byte_ready <= 0;
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end // else: !if(cs)
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end // else: !if(rst)
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$display("[%0d] current rx_shift: %b", $time, rx_shift);
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$display("[%0d] current bit_cnt: %0d", $time, bit_cnt);
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$display("[%0d] current rx_buff: %b", $time, rx_buff);
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end // always_ff @ (posedge sclk)
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always_ff @ (posedge sclk_falling_edge) begin
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if (rst) begin
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tx_shift <= 0;
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end
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else begin
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if (cs) begin
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tx_shift <= 0;
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end else begin
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if (bit_cnt == 0) begin
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tx_shift <= rx_buff[7:0];
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end else begin
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tx_shift <= {tx_shift[6:0], 1'b0};
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end
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end
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end // else: !if(rst)
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$display("last bit sent: %b", miso);
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$display("[%0d] current tx_shift: %b", $time, tx_shift);
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$display("-----------------------------------------");
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end // always_ff @ (negedge sclk)
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assign miso = tx_shift[7];
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// RX and TX logic
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logic [9:0] rx_queue_head = 0;
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logic [9:0] rx_queue_tail = 0;
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logic [10:0] rx_size = 0;
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logic rx_queue_write = 0;
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logic [7:0] rx_read;
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logic [7:0] dest_read;
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logic packet_sending;
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logic rx_queue_empty;
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assign rx_size = (rx_queue_tail + 11'd1024 - rx_queue_head) & 11'h3FF;
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assign rx_queue_empty = ~(|rx_size);
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rx_queue_bram rx_queue (.sys_clk(sys_clk),
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.write_enable(rx_queue_write),
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.read_addr(rx_queue_head),
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.write_addr(rx_queue_tail),
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.write_data(rx_buff),
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.read_data(rx_read),
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.read_dest(dest_read));
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always_ff @ (posedge sys_clk) begin
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if (rst) begin
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rx_queue_head <= '0;
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rx_queue_tail <= '0;
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rx_queue_write <= '0;
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rx_read <= '0;
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packet_sending <= 0;
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end else begin
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if (byte_ready)
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rx_queue_write <= 1;
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if (rx_queue_write) begin
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rx_queue_write <= 0;
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rx_queue_tail <= rx_queue_tail + 1;
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end
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if (!packet_sending) begin
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if (rx_size > 2 && rx_ready) begin
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rx_byte <= rx_read;
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rx_dest <= dest_read;
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rx_valid <= 1;
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end else
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rx_valid <= 0;
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end else begin
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if (is_packet_complete(rx_queue_head, packet_size))
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packet_sending <= 0;
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else if (rx_size > 0) begin
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rx_byte <= rx_read;
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rx_dest <= dest_read;
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rx_valid <= 1;
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end
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end
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end
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end // always_ff @ (posedge sys_clk)
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logic [13:0] tx_queue_head;
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logic [13:0] tx_queue_tail;
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endmodule // spi_interface
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module async_get_clk_edges(
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input logic rst,
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input logic ext_clk,
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input logic sys_clk,
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output logic clk_rising_edge,
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output logic clk_falling_edge);
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timeunit 1ns;
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timeprecision 1ps;
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`ifdef SYNC_2FF
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logic sync_0 = 0;
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logic sync_1 = 0;
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always_ff @ (posedge sys_clk) begin
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if (rst) begin
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sync_0 <= 0;
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sync_1 <= 0;
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end else begin
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sync_0 <= ext_clk;
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sync_1 <= sync_0;
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end
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end
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assign clk_rising_edge = sync_0 & ~sync_1;
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assign clk_falling_edge = ~sync_0 & sync_1;
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`else // !`ifdef SYNC_2FF
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logic [2:0] clk_sync = 0;
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always_ff @ (posedge sys_clk) begin
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if (rst)
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clk_sync <= {clk_sync[1:0], ext_clk};
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end
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assign clk_rising_edge = (clk_sync[2:1] == 2'b01);
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assign clk_falling_edge = (clk_sync[2:1] == 2'b10);
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`endif // !`ifdef SYNC_2FF
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endmodule // async_get_clk_edges
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module rx_queue_bram (
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input logic sys_clk,
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input logic write_enable,
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input logic [9:0] read_addr,
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input logic [9:0] write_addr,
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input logic [7:0] write_data,
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output logic [7:0] read_data,
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output logic [7:0] read_dest);
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timeunit 1ns;
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timeprecision 1ps;
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logic [7:0] mem [1023:0];
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always_ff @ (posedge sys_clk) begin
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if (write_enable)
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mem[write_addr] <= write_data;
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read_data <= mem[read_addr];
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read_dest <= mem[read_addr + 1];
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end
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endmodule // rx_queue_bram
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module tx_queue_bram(input logic sys_clk,
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input logic write_enable,
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input logic [13:0] read_addr,
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input logic [13:0] write_addr,
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input logic [7:0] write_data,
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output logic [7:0] read_data);
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timeunit 1ns;
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timeprecision 1ps;
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logic [7:0] mem [16 * 1023:0];
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always_ff @ (posedge sys_clk) begin
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if (write_enable)
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mem[write_addr] <= write_data;
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read_data <= mem[read_addr];
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end
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endmodule // tx_queue_bram
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function automatic logic is_packet_complete(input logic [9:0] head,
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input logic [1:0] packet_size);
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case(packet_size)
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2'b00:
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return &(head & 'd64);
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2'b01:
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return &(head & 'd128);
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2'b10:
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return &(head & 'd256);
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2'b11:
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return &head;
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endcase // case (packet_size)
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endfunction // packet_complete
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