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rose
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1f7c47a1fb777eaa42e9d4c238b9b91bbed9b787
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3 Commits
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Peisong Xiao
1f7c47a1fb
WORKING PROGRESS. revamped the files and naming, so git is a bit confused
...
mem_hub.sv -> hub.sv spi_slave.sv -> interface.sv
2025-05-17 22:06:41 -04:00
Peisong Xiao
b26a716ccf
began work on the central routing logic, updated some documentation
2025-05-14 22:27:40 -04:00
Peisong Xiao
24bf28db9d
initial commit: figuring out SPI on the Tang Primer 20K, already 3 devlogs, will commit on a per-devlog/document change basis
2025-05-11 00:35:24 -04:00