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8 Commits 1 Branch 0 Tags
018b7a3fcf0377aaa0d940d36852433401bbe316
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6 Commits

Author SHA1 Message Date
Peisong Xiao
a94823b44a finished the hub's logic, half done with the interfaces, and hopefully working on pi logic soon 2025-06-05 22:38:26 -04:00
Peisong Xiao
f61de84b4a work in progress, major overhaul for design, see devlogs for details. Also added the first version of the style guide 2025-05-29 00:18:06 -04:00
Peisong Xiao
dac3140829 heavy work in progress 2025-05-21 21:04:57 -04:00
Peisong Xiao
1f7c47a1fb WORKING PROGRESS. revamped the files and naming, so git is a bit confused
mem_hub.sv -> hub.sv
spi_slave.sv -> interface.sv
2025-05-17 22:06:41 -04:00
Peisong Xiao
b26a716ccf began work on the central routing logic, updated some documentation 2025-05-14 22:27:40 -04:00
Peisong Xiao
24bf28db9d initial commit: figuring out SPI on the Tang Primer 20K, already 3 devlogs, will commit on a per-devlog/document change basis 2025-05-11 00:35:24 -04:00
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