12 lines
215 B
Systemverilog
12 lines
215 B
Systemverilog
`ifndef __UTILS_SVH__
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`define __UTILS_SVH__
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`include <params.svh>
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`include <packet.svh>
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function automatic logic get_bit(input Packet pkt, input int pos);
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if (pos <= 0 | pos >=
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endfunction // get_bit
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`endif
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