50 lines
1.9 KiB
Markdown
50 lines
1.9 KiB
Markdown
# The Bootloader
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Date: 2025-07-02
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## Goals and expectations
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Writing the bootloader logic for the fabric. This is for easy scaling
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of the buffer size.
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And also add indicators (output logic) to signal the user and
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interfaces that the fabric is ready.
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## Results
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Done. A simple bootloader, much simpler than I expected, just a
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simple FSM with some initializing logic.
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Just some logic inside the `free_queue` module to initialize it when
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the FPGA boots.
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And in the meanwhile, I spawned a new server (one specifically for
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running long term simulations), and also changed my shell to `fish`
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from `zsh` for some more modern feel.
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## Reflections
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1. Once again, I am bemused by the simplicity of combinational logic.
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FSMs translate much better to SystemVerilog than to some
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sequentially executed logic like C.
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2. Keep it simple. A simple bootloader is much easier for future
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implementations compared to initializing through other means, and
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once complete, it's very scalable.
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3. The plan isn't everything. This wasn't part of the plan, the plan
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was to burn the initial values inside a hex file or some other
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methods that would allow instant initialization. However, due to
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the elements of the `free_queue` being not byte-aligned, this would
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become much more trouble in the end. The plan was modified
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accordingly.
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4. Make the best out of the existing tools on hand. This is a
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follow-up to the previous point. Don't go into coding with only
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the plan and goals in mind, reassess when you've set foot on its
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grounds, weigh the options, and something else might just come up.
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## Final thoughts
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Find the right tools to do the right things. Trying to simulate
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clocked behaviors in C++ is as awkward as trying to write sequential
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logic in SystemVerilog.
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The first choice isn't always the best one, but the final choice
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should the better one after weighing the options.
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## Next steps
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THORN!
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