87 lines
3.6 KiB
Markdown
87 lines
3.6 KiB
Markdown
# Fabric's Basic Logic Done
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Date: 2025-06-06
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## Goals and expectations
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Complete the fabric's code.
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## Results
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Done.
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And also revised the directory layout (swapped `fabric/` and `src/`).
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As a bonus, I also modularized the interfaces' code, making it cleaner
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and easier to maintain.
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And as a second bonus, I completed the drop logic.
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## Packet dropping
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Packet dropping can be caused by two issues:
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1. The packet memory is full, in which case the hub will notify all
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interfaces to drop their packets.
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2. The destination's packet queue is full, in which case the hub will
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drop the packet by immediately reclaiming the slot via the reuse
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logic.
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There are a few scenarios for which this can play out. Notably, if both
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the packet memory and the destination's packet queue is full, and the
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destination was full before the packet memory, then the **hub** will
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drop the packet instead of the source interface.
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## Reflections
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1. Keep the momentum alive. I kept the momentum I gained yesterday
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alive by actively coding today, this helped me pick up my previous
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thoughts.
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2. Small rewards go a long way. I recently showed some people the
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ROSE repo, they didn't read much code, but they were obsessed with
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the devlogs and the README and how organized the entire project is.
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This boosted my confidence in thinking that ROSE could be a
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game changer for me - I wanted it to become something that people
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can appreciate, even if they're not devs, even if they don't read
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the code. I enjoyed their praise, and I'm preparing myself to
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uphold that.
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3. Simplify the logic. Much of today's code was linking different
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modules together and having internal states within the modules to
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manage the operations. Most of the time, the data is already
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available, and there's no reason to stall it for an additional
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cycle to buffer it.
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4. HDL is better for design meant for hardware. This isn't
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ROSE-specific, but rather a thought that I came across while
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implementing the new ARCANE load balancing algorithm for an `ns-3`
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sim. It would've been much cleaner to implement a
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hardware-targeting algorithm in HDL than in a language like C++.
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For example, the three states of ARCANE (explore, normal and
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freeze) would be perfectly implemented by an FSM. While the C++
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sim would have to schedule timeouts using very explicit (and
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seemingly unnecessarily complex) code, SystemVerilog would embrace
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that by design.
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## Final thoughts
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Finally! After more than a month of intermittent coding, I'm close to
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completing an implementation for the fabric. Just some sim tests and
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I can begin working on the Linux code for the hosts.
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I love coding, I love writing my thoughts down, in code or in plain
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words. It's the proof of my existence. I'm here to leave a mark, for
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those who'd like to see how I do it.
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> C'est cela l'amour, tout donner, tout sacrifier sans espoir de
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> retour.
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### What is such a thing as love that doesn't hope for anything in return?
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It's that the love is for a bigger picture. We'd always hope for
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something in return, whether that's tangible or intangible, whether
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that's spontaneous or given to by someone else. But the scale of the
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hope changes when we have love. With it, we see a bigger picture -
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how that love is impulsive, how that love drives us forward, and how
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in the broader view, it makes us better.
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## Next steps
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Testing. I'm sure when I throw real traffic at my code, it will go
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wrong in ways.
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Notably, I should test the drop logic with different scenarios:
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bursts, incast, and heavy background flows. Simulating congestion is
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my thing (but, of course, we won't be running something as complex as
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an AllReduce workload).
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