work in progress, major overhaul for design, see devlogs for details. Also added the first version of the style guide
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@ -1,96 +1,167 @@
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module hub (
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input logic rst,
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input logic sys_clk,
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input logic [31:0] rx_cmd, // for routing-related commands
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input logic [3:0] rx_cmd_valid,
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input logic [31:0] rx_byte,
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input logic [3:0] rx_valid,
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input logic [31:0] rx2tx_dest, // rx byte's destination
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input logic [3:0] tx_ready, // if tx_byte is ready to be read
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output logic [3:0] rx_ready, // if rx_byte is ready to be read
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output logic [7:0] tx_src, // tell the tx where the stream is comming from
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output logic [31:0] tx_byte,
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output logic [3:0] tx_valid,
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output logic [1:0] packet_size); // 4 states for 4 fixed packet sizes
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`include <params.sv>
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// IMPORTANT: interfaces are supposed to keep track of their own packet states
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module hub(
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input logic sys_clk,
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input logic rst,
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input logic [INTERFACE_CNT - 1][PACKET_ADDR_LEN - 1:0] rx_pkt_addr,
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input logic [INTERFACE_CNT - 1:0][7:0] rx_byte,
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input logic [INTERFACE_CNT - 1:0] rx_valid,
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input logic [INTERFACE_CNT - 1:0] tx_ready,
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input logic [INTERFACE_CNT - 1:0] tx_full,
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input logic [INTERFACE_CNT - 1:0][PACKET_ADDR_LEN - 1:0] tx_pkt_addr,
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input logic [INTERFACE_CNT - 1:0] rx_new_packet,
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output logic [INTERFACE_CNT - 1:0] rx_ready,
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output logic [INTERFACE_CNT - 1:0][PACKET_ADDR_LEN - 1:0] tx_queue_addr,
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output logic [INTERFACE_CNT - 1:0] tx_queue_addr_valid,
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output logic [INTERFACE_CNT - 1:0][7:0] tx_byte,
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output logic [INTERFACE_CNT - 1:0] tx_valid);
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timeunit 1ns;
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timeprecision 1ps;
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logic [INTERFACE_CNT - 1:0] curr_service;
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logic request_new_slot;
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logic [QUEUE_ADDR_LEN - 1:0] new_slot_addr;
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logic free_queue_empty;
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logic [QUEUE_ADDR_LEN - 1:0] empty_slot_addr;
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logic [QUEUE_ADDR_LEN - 1:0] empty_slot_enqueue;
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free_queue fqueue(.sys_clk(sys_clk),
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.rst(rst),
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.request_new_slot(request_new_slot),
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.empty_slot_addr(empty_slot_addr),
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.empty_slot_enqueue(empty_slot_enqueue),
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.new_slot_addr(new_slot_addr),
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.queue_empty(free_queue_empty));
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// TBD: pre-agree on packet size
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logic [INTERFACE_CNT - 1:0][MEMORY_ADDR_LEN - 1:0] rx_mem_addr;
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logic [MEMORY_POOL_ADDR_LEN - 1:0] mem_read_addr;
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logic [7:0] mem_read_byte;
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logic [MEMORY_POOL_ADDR_LEN - 1:0] mem_write_addr;
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logic mem_write_enable;
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logic [7:0] mem_write_byte;
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// use the round-robin strat to poll since the routing is much faster
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// NOTE: To expand to more connected_devices, use a hierarchical design
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logic [1:0] curr_service = 0;
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logic [1:0] last_dest = 0;
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// src dest byte
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typedef struct {
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logic [1:0] dest;
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logic [7:0] payload;
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} svc_buffer;
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svc_buffer service_buffer [3:0];
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svc_buffer curr_buffer;
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assign curr_buffer = service_buffer[curr_service];
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logic [3:0] in_buffer;
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assign rx_ready = ~in_buffer;
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always_ff @ (posedge sys_clk) begin
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memory_pool mpool(.sys_clk(sys_clk),
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.rst(rst),
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.read_addr(mem_read_addr),
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.write_addr(mem_write_addr),
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.write_byte(mem_write_byte),
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.write_enable(mem_write_enable),
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.read_byte(mem_read_byte));
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always_ff @ (posedge sys_clk or rst) begin
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if (rst) begin
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in_buffer <= '0;
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tx_src <= '0;
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tx_queue_addr <= '0;
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tx_queue_addr_valid <= '0;
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tx_byte <= '0;
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tx_valid <= '0;
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packet_size <= '0;
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curr_service <= '0;
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last_dest <= '0;
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for (int i = 0; i < 4; i++) begin
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service_buffer[i] <= '0;
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end
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end else begin // if (rst)
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// Handle RX side logic
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for (int i = 0; i < 4; i++) begin
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if (rx_valid[i]) begin
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if (!in_buffer[i]) begin
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service_buffer[i].dest <= get_hop(rx2tx_dest, i[1:0]);
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service_buffer[i].payload <= get_byte(rx_byte, i[1:0]);
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in_buffer[i] <= 1;
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rx_ready <= '0;
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rx_mem_addr <= '0;
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mem_read_addr <= '0;
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mem_write_addr <= '0;
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mem_write_enable <= 0;
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mem_write_byte <= '0;
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end else begin
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// NOTE: signaled the servicing interface in the last cycle
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rx_ready[curr_service] <= 0;
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rx_ready[curr_service + 1] <= 1;
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// IMPORTANT: interfaces should send the byte no matter what, rx_ready is to prevent sending a new byte
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if (rx_valid[curr_service]) begin
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// IMPORTANT: memory_write_addr is ready on the next cycle
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if (rx_new_packet[curr_service]) begin
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if (free_queue_empty) begin
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// TODO: handle the drop logic
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end else begin
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request_new_slot <= 1;
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rx_mem_addr[{curr_service,
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MEMORY_POOL_ADDR_SHIFT'd0}
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+:MEMORY_POOL_ADDR_LEN
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] <= {new_slot_addr, PACKET_ADDR_LEN'd0};
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mem_write_addr <= {new_slot_addr, PACKET_ADDR_LEN'd0};
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end
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end
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end
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// Handle TX side logic
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if (in_buffer[curr_service] && tx_ready[curr_buffer.dest]) begin
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tx_byte[{curr_buffer.dest, 3'b000} +: 8]
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<= curr_buffer.payload;
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tx_src[{curr_buffer.dest, 1'b0} +: 2]
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<= curr_service;
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in_buffer[curr_service] <= 0;
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tx_valid[curr_buffer.dest] <= 1;
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end
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tx_valid[last_dest] <= 0;
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last_dest <= service_buffer[curr_service].dest;
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curr_service <= curr_service + 1;
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end // else: !if(rst)
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end // always_ff @ (posedge sys_clk)
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end else begin // if (rx_new_packet[curr_service])
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// NOTE: if memory
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mem_write_addr <= mem_write_addr + 1;
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request_new_slot <= 0;
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end // else: !if(rx_new_packet[curr_service])
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mem_write_byte <= rx_byte[{curr_service, 3'd0}+:8];
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mem_write_enable <= 1;
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end else // if (rx_valid[curr_service])
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mem_write_enable <= 0;
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end
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end
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endmodule // hub
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function automatic logic [7:0] get_byte(input logic [31:0] byte_arr,
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input logic [1:0] idx);
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return byte_arr[{idx, 3'b000} +: 8];
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endfunction // get_byte
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// IMPORTANT: the current queue_addr is always valid unless queue_empty
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// REQUIRES: hub does not request a new slot when the queue is empty
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module free_queue(input logic sys_clk,
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input logic rst,
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input logic request_new_slot,
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input logic [QUEUE_ADDR_LEN - 1:0] empty_slot_addr,
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input logic empty_slot_enqueue,
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output logic [QUEUE_ADDR_LEN - 1:0] new_slot_addr,
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output logic queue_empty);
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timeunit 1ns;
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timeprecision 1ps;
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// NOTE: addr 0 is alway mapped to the fabric itself and caught before this
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function automatic logic [1:0] get_hop(input logic [31:0] dest_map,
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input logic [1:0] idx);
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case (dest_map[{idx, 3'b000} +: 8])
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8'b00000001:
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return 2'b00;
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8'b00000010:
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return 2'b01;
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8'b00000011:
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return 2'b10;
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8'b00000100:
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return 2'b11;
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default:
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return 0;
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endcase // case (dest_map[{idx, 3'b000} +: 8])
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endfunction // get_hop
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logic [QUEUE_ADDR_LEN - 1:0] fqueue [QUEUE_SIZE - 1:0];
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logic [QUEUE_ADDR_LEN - 1:0] head;
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logic [QUEUE_ADDR_LEN - 1:0] tail;
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shortint queue_size;
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assign queue_empty = queue_size == 0;
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initial begin
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// TODO: pre-load the free queue with every slot possible
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end
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// IMPORTANT: rst must be held high for at least 2 sys_clk cycles
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always_ff @ (posedge sys_clk or rst) begin
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if (rst) begin
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head <= '0;
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tail <= QUEUE_ADDR_LEN'd1;
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queue_size = QUEUE_SIZE;
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new_slot_addr <= '0;
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end else begin
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if (request_new_slot) begin
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head <= head + 1;
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queue_size <= queue_size - 1;
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end
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new_slot_addr <= fqueue[head];
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if (empty_slot_enqueue) begin
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fqueue[tail] <= empty_slot_addr;
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tail <= tail + 1;
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queue_size <= queue_size + 1;
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end
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end
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end
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endmodule // free_queue
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module memory_pool(input logic sys_clk,
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input logic rst,
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input logic [MEMORY_POOL_ADDR_LEN - 1:0] read_addr,
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input logic [MEMORY_POOL_ADDR_LEN - 1:0] write_addr,
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input logic [7:0] write_byte,
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input logic write_enable,
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output logic [7:0] read_byte);
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timeunit 1ns;
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timeprecision 1ps;
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logic [7:0] mem_pool[MEMORY_POOL_SIZE - 1:0];
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always_ff @ (posedge sys_clk or rst) begin
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if (rst) begin
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read_byte <= 8'hFF;
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end else begin
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if (write_enable)
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mem_pool[write_addr] <= write_byte;
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read_byte <= mem_pool[read_addr];
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end
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end
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endmodule // memory_pool
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11
fabric/src/params.sv
Normal file
11
fabric/src/params.sv
Normal file
@ -0,0 +1,11 @@
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parameter int PACKET_SIZE = 64;
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parameter int PACKET_ADDR_LEN = 6;
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parameter int QUEUE_SIZE = 1024;
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parameter int QUEUE_ADDR_LEN = 10;
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parameter int MEMORY_POOL_SIZE = QUEUE_SIZE * PACKET_SIZE;
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parameter int MEMORY_POOL_ADDR_LEN = QUEUE_ADDR_LEN + PACKET_ADDR_LEN;
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parameter int MEMORY_POOL_ADDR_SHIFT = 4;
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parameter int INTERFACE_QUEUE_SIZE = 512;
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parameter int INTERFACE_QUEUE_ADDR_LEN = 9;
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parameter int INTERFACE_CNT = 4;
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parameter int CRC_BITS = 8;
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