back to work, added the top module for the fabric

plan.md

@@ -13,11 +13,16 @@ Implement a functional SPI slave on the FPGA.  Add small logic to
 manipulate the data.  Learn about cross-clock domain design and
 implementation.
 
-### [TODO] Implement the routing logic along with the interfaces
+### [DONE] Implement the routing logic along with the interfaces
 This would be the core part of implementing ROSE on the fabric
 side. This is a bare minimum implementation disregarding any
 congestion control or inter-fabric routing.
 
+### [TODO] Test the logic in sims
+This is an important next step.  And one of the most important aspects
+of this project.  I need to test this out in ideal scenarios so that I
+can catch and fix bugs before I get to hard-to-debug bare metal.
+
 ### [TODO] Test on a RPi-FPGA setup
 Getting the code to run on sims is one thing, getting it to run on
 actual hardware is another.  This entire step will be to ship the code
@@ -98,3 +103,12 @@ implementation that's elegant and simple.
 #### The lesson learned
 Focus. Know what ROSE really stand for, and stop spending thoughts on
 unnecessary things like trying to dual-wield AI and HFT workloads.
+
+### Added sims as part of the plan
+Yes, that should be explicitly written in the plan!
+
+#### The lesson learned
+Every step is a step.  Every step you've walked is solid, and every
+step you plan should also fall sequentially.  There's no jumping from
+raw code to deployment, and there's no excuse for leaving this out of
+the plan.