began work on the central routing logic, updated some documentation
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50
fabric/src/mem_hub.sv
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50
fabric/src/mem_hub.sv
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module mem_hub (input logic rst,
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input logic sys_clk,
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input logic [3:0] connected_devices, // manually configured
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input logic [3:0][7:0] rx_cmd, // for routing-related commands
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input logic [3:0] rx_cmd_valid,
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input logic [3:0][7:0] rx_byte,
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input logic [3:0] rx_valid,
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input logic [3:0][1:0] rx2tx_dest, // rx byte's destination
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input logic [3:0] tx_read, // if tx_byte was read
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output logic [3:0] rx_read, // if rx_byte was read
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output logic [3:0][1:0] tx_src, // tell the tx where the stream is comming from
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output logic [3:0][7:0] tx_byte,
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output logic [3:0] tx_valid,
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output logic [1:0] packet_size); // 4 states for 4 fixed packet sizes
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timeunit 1ns;
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timeprecision 1ps;
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// TBD: pre-agree on packet size
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// [index][rx_src]
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logic [3:0][1:0] service_queue;
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logic [3:0] in_queue;
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// [rx_src][tx_dest], might not be useful
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logic [1:0][1:0] rx2tx_map;
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logic [2:0] i;
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always_ff @ (posedge sys_clk) begin
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if (rst) begin
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rx_read <= '0;
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tx_src <= '0;
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tx_valid <= '0;
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packet_size <= '0;
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service_queue <= '0;
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in_queue <= '0;
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rx2tx_map <= '0;
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i <= 0;
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end
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if (in_queue == 4'd0) begin // no one is in the queue yet
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if (tx_valid != 4'd0) begin
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for (i = 0; i < 3'd4; i++) begin
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// TODO: write the logic for enqueuing
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end
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end
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end else begin
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end
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end
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endmodule // mem_hub
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