began work on the central routing logic, updated some documentation

This commit is contained in:
2025-05-14 22:27:40 -04:00
parent 24bf28db9d
commit b26a716ccf
5 changed files with 329 additions and 1 deletions

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fabric/src/mem_hub.sv Normal file
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module mem_hub (input logic rst,
input logic sys_clk,
input logic [3:0] connected_devices, // manually configured
input logic [3:0][7:0] rx_cmd, // for routing-related commands
input logic [3:0] rx_cmd_valid,
input logic [3:0][7:0] rx_byte,
input logic [3:0] rx_valid,
input logic [3:0][1:0] rx2tx_dest, // rx byte's destination
input logic [3:0] tx_read, // if tx_byte was read
output logic [3:0] rx_read, // if rx_byte was read
output logic [3:0][1:0] tx_src, // tell the tx where the stream is comming from
output logic [3:0][7:0] tx_byte,
output logic [3:0] tx_valid,
output logic [1:0] packet_size); // 4 states for 4 fixed packet sizes
timeunit 1ns;
timeprecision 1ps;
// TBD: pre-agree on packet size
// [index][rx_src]
logic [3:0][1:0] service_queue;
logic [3:0] in_queue;
// [rx_src][tx_dest], might not be useful
logic [1:0][1:0] rx2tx_map;
logic [2:0] i;
always_ff @ (posedge sys_clk) begin
if (rst) begin
rx_read <= '0;
tx_src <= '0;
tx_valid <= '0;
packet_size <= '0;
service_queue <= '0;
in_queue <= '0;
rx2tx_map <= '0;
i <= 0;
end
if (in_queue == 4'd0) begin // no one is in the queue yet
if (tx_valid != 4'd0) begin
for (i = 0; i < 3'd4; i++) begin
// TODO: write the logic for enqueuing
end
end
end else begin
end
end
endmodule // mem_hub