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Fix: indent to 4 spaces (3 spaces is pure evil)

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Peisong Xiao
2025-05-15 20:03:54 -04:00
parent b26a716ccf
commit a83a8f9f95
3 changed files with 102 additions and 109 deletions
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71
fabric/src/mem_hub.sv
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@ -1,50 +1,43 @@
module mem_hub (input logic rst, module mem_hub (input logic rst,
input logic sys_clk, input logic sys_clk,
input logic [3:0] connected_devices, // manually configured input logic [3:0] connected_devices, // manually configured
input logic [3:0][7:0] rx_cmd, // for routing-related commands input logic [3:0][7:0] rx_cmd, // for routing-related commands
input logic [3:0] rx_cmd_valid, input logic [3:0] rx_cmd_valid,
input logic [3:0][7:0] rx_byte, input logic [3:0][7:0] rx_byte,
input logic [3:0] rx_valid, input logic [3:0] rx_valid,
input logic [3:0][1:0] rx2tx_dest, // rx byte's destination input logic [3:0][1:0] rx2tx_dest, // rx byte's destination
input logic [3:0] tx_read, // if tx_byte was read input logic [3:0] tx_ready, // if tx_byte was read
output logic [3:0] rx_read, // if rx_byte was read output logic [3:0] rx_ready, // if rx_byte was read
output logic [3:0][1:0] tx_src, // tell the tx where the stream is comming from output logic [3:0][1:0] tx_src, // tell the tx where the stream is comming from
output logic [3:0][7:0] tx_byte, output logic [3:0][7:0] tx_byte,
output logic [3:0] tx_valid, output logic [3:0] tx_valid,
output logic [1:0] packet_size); // 4 states for 4 fixed packet sizes output logic [1:0] packet_size); // 4 states for 4 fixed packet sizes
timeunit 1ns; timeunit 1ns;
timeprecision 1ps; timeprecision 1ps;
// TBD: pre-agree on packet size // TBD: pre-agree on packet size
// [index][rx_src] // use the round-robin strat to poll since the routing is much faster
logic [3:0][1:0] service_queue; // NOTE: To expand to more connected_devices, use a hierarchical design
logic [3:0] in_queue; logic [1:0] curr_service = 0;
// [rx_src][tx_dest], might not be useful // src dest byte
logic [1:0][1:0] rx2tx_map; logic [1:0][1:0][7:0] service_buffer;
logic [3:0] in_buffer;
logic [2:0] i;
// Core service logic
always_ff @ (posedge sys_clk) begin always_ff @ (posedge sys_clk) begin
if (rst) begin if (rst) begin
rx_read <= '0; rx_ready <= '1;
tx_src <= '0; tx_src <= '0;
tx_valid <= '0; tx_valid <= '0;
packet_size <= '0; packet_size <= '0;
service_queue <= '0; service_buffer <= '0;
in_queue <= '0; curr_service <= '0;
rx2tx_map <= '0; end else if (rx_valid[curr_service]) begin
i <= 0;
end end
if (in_queue == 4'd0) begin // no one is in the queue yet curr_service <= curr_service + 1;
if (tx_valid != 4'd0) begin
for (i = 0; i < 3'd4; i++) begin
// TODO: write the logic for enqueuing
end
end
end else begin
end
end end
endmodule // mem_hub endmodule // mem_hub

90
fabric/src/spi_slave.sv
View File

@ -14,9 +14,9 @@ module spi_slave(
logic sclk_falling_edge; logic sclk_falling_edge;
async_get_clk_edges sync (.ext_clk(sclk), async_get_clk_edges sync (.ext_clk(sclk),
.sys_clk(sys_clk), .sys_clk(sys_clk),
.clk_rising_edge(sclk_rising_edge), .clk_rising_edge(sclk_rising_edge),
.clk_falling_edge(sclk_falling_edge)); .clk_falling_edge(sclk_falling_edge));
int bit_cnt = 0; int bit_cnt = 0;
logic [7:0] rx_shift; logic [7:0] rx_shift;
@ -25,50 +25,50 @@ module spi_slave(
logic byte_ready = 0; logic byte_ready = 0;
always_ff @ (posedge sclk_rising_edge or posedge rst) begin always_ff @ (posedge sclk_rising_edge or posedge rst) begin
if (rst) begin if (rst) begin
rx_shift <= 0; rx_shift <= 0;
tx_buff <= 0; tx_buff <= 0;
bit_cnt <= 0; bit_cnt <= 0;
end end
else begin else begin
if (cs) begin if (cs) begin
rx_shift <= 0; rx_shift <= 0;
tx_buff <= 0; tx_buff <= 0;
bit_cnt <= 0;
end else begin
rx_shift <= {rx_shift[6:0], mosi};
bit_cnt <= bit_cnt + 1;
if (bit_cnt == 7) begin
bit_cnt <= 0; bit_cnt <= 0;
tx_buff <= {rx_shift[6:0], mosi} + 1; end else begin
end rx_shift <= {rx_shift[6:0], mosi};
end // else: !if(cs) bit_cnt <= bit_cnt + 1;
end // else: !if(rst)
if (bit_cnt == 7) begin
bit_cnt <= 0;
tx_buff <= {rx_shift[6:0], mosi} + 1;
end
end // else: !if(cs)
end // else: !if(rst)
$display("[%0d] current rx_shift: %b", $time, rx_shift); $display("[%0d] current rx_shift: %b", $time, rx_shift);
$display("[%0d] current bit_cnt: %0d", $time, bit_cnt); $display("[%0d] current bit_cnt: %0d", $time, bit_cnt);
$display("[%0d] current tx_buff: %b", $time, tx_buff); $display("[%0d] current tx_buff: %b", $time, tx_buff);
end // always_ff @ (posedge sclk) end // always_ff @ (posedge sclk)
always_ff @ (posedge sclk_falling_edge) begin always_ff @ (posedge sclk_falling_edge) begin
if (rst) begin if (rst) begin
tx_shift <= 0; tx_shift <= 0;
end end
else begin else begin
if (cs) begin if (cs) begin
tx_shift <= 0; tx_shift <= 0;
end else begin end else begin
if (bit_cnt == 0) begin if (bit_cnt == 0) begin
tx_shift <= tx_buff[7:0]; tx_shift <= tx_buff[7:0];
end else begin end else begin
tx_shift <= {tx_shift[6:0], 1'b0}; tx_shift <= {tx_shift[6:0], 1'b0};
end end
end end
end // else: !if(rst) end // else: !if(rst)
$display("last bit sent: %b", miso); $display("last bit sent: %b", miso);
$display("[%0d] current tx_shift: %b", $time, tx_shift); $display("[%0d] current tx_shift: %b", $time, tx_shift);
$display("-----------------------------------------"); $display("-----------------------------------------");
end // always_ff @ (negedge sclk) end // always_ff @ (negedge sclk)
assign miso = tx_shift[7]; assign miso = tx_shift[7];
@ -87,8 +87,8 @@ module async_get_clk_edges(
logic sync_1; logic sync_1;
always_ff @ (posedge sys_clk) begin always_ff @ (posedge sys_clk) begin
sync_0 <= ext_clk; sync_0 <= ext_clk;
sync_1 <= sync_0; sync_1 <= sync_0;
end end
assign clk_rising_edge = sync_0 & ~sync_1; assign clk_rising_edge = sync_0 & ~sync_1;
@ -97,7 +97,7 @@ module async_get_clk_edges(
logic [2:0] clk_sync; logic [2:0] clk_sync;
always_ff @ (posedge sys_clk) begin always_ff @ (posedge sys_clk) begin
clk_sync <= {clk_sync[1:0], ext_clk}; clk_sync <= {clk_sync[1:0], ext_clk};
end end
assign clk_rising_edge = (clk_sync[2:1] == 2'b01); assign clk_rising_edge = (clk_sync[2:1] == 2'b01);

50
fabric/src/tb.sv
View File

@ -19,40 +19,40 @@ module tb;
.sclk(sclk), .sclk(sclk),
.miso(miso)); .miso(miso));
initial begin initial begin
#20 rst_n = 1; #20 rst_n = 1;
end end
task spi_test (input logic [7:0] tx_byte, task spi_test (input logic [7:0] tx_byte,
output logic [7:0] rx_byte); output logic [7:0] rx_byte);
begin begin
cs = 0; cs = 0;
#30; #30;
for(int idx = 1; idx < hello.len(); idx = idx + 1) begin for(int idx = 1; idx < hello.len(); idx = idx + 1) begin
tx_byte = hello[idx]; tx_byte = hello[idx];
$display("%0d=================================================", $time); $display("%0d=================================================", $time);
for (int i = 7; i >= 0; i = i - 1) begin for (int i = 7; i >= 0; i = i - 1) begin
mosi = tx_byte[i]; mosi = tx_byte[i];
sclk = 1; sclk = 1;
#10; #10;
sclk = 0; sclk = 0;
rx_byte[i] = miso; rx_byte[i] = miso;
#10; #10;
$display("[%0d] received bit: %b", $time, miso); $display("[%0d] received bit: %b", $time, miso);
end // for (int i = 7; i >= 0; i = i - 1) end // for (int i = 7; i >= 0; i = i - 1)
$display("[%0d] Sent: %c | %b", $time, tx_byte, tx_byte); $display("[%0d] Sent: %c | %b", $time, tx_byte, tx_byte);
$display("[%0d] Received: %c (expected %c)", $time, rx_byte, hello[idx - 1] + 8'd1); $display("[%0d] Received: %c (expected %c)", $time, rx_byte, hello[idx - 1] + 8'd1);
$display("[%0d] Received: %b (expected %b)", $time, rx_byte, hello[idx - 1] + 8'd1); $display("[%0d] Received: %b (expected %b)", $time, rx_byte, hello[idx - 1] + 8'd1);
$display("%0d=================================================", $time); $display("%0d=================================================", $time);
end end
cs = 1; cs = 1;
#40; #40;
end end
endtask // spi_test endtask // spi_test
logic [7:0] tx_data = 8'd65; logic [7:0] tx_data = 8'd65;
logic [7:0] rx_data; logic [7:0] rx_data;
initial begin initial begin
spi_test(tx_data, rx_data); spi_test(tx_data, rx_data);
end end
endmodule // tb endmodule // tb