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Fix: indent to 4 spaces (3 spaces is pure evil)

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Peisong Xiao
2025-05-15 20:03:54 -04:00
parent b26a716ccf
commit a83a8f9f95
3 changed files with 102 additions and 109 deletions
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37
fabric/src/mem_hub.sv
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@ -6,8 +6,8 @@ module mem_hub (input logic rst,
input logic [3:0][7:0] rx_byte, input logic [3:0][7:0] rx_byte,
input logic [3:0] rx_valid, input logic [3:0] rx_valid,
input logic [3:0][1:0] rx2tx_dest, // rx byte's destination input logic [3:0][1:0] rx2tx_dest, // rx byte's destination
input logic [3:0] tx_read, // if tx_byte was read input logic [3:0] tx_ready, // if tx_byte was read
output logic [3:0] rx_read, // if rx_byte was read output logic [3:0] rx_ready, // if rx_byte was read
output logic [3:0][1:0] tx_src, // tell the tx where the stream is comming from output logic [3:0][1:0] tx_src, // tell the tx where the stream is comming from
output logic [3:0][7:0] tx_byte, output logic [3:0][7:0] tx_byte,
output logic [3:0] tx_valid, output logic [3:0] tx_valid,
@ -17,34 +17,27 @@ module mem_hub (input logic rst,
// TBD: pre-agree on packet size // TBD: pre-agree on packet size
// [index][rx_src] // use the round-robin strat to poll since the routing is much faster
logic [3:0][1:0] service_queue; // NOTE: To expand to more connected_devices, use a hierarchical design
logic [3:0] in_queue; logic [1:0] curr_service = 0;
// [rx_src][tx_dest], might not be useful // src dest byte
logic [1:0][1:0] rx2tx_map; logic [1:0][1:0][7:0] service_buffer;
logic [3:0] in_buffer;
logic [2:0] i;
// Core service logic
always_ff @ (posedge sys_clk) begin always_ff @ (posedge sys_clk) begin
if (rst) begin if (rst) begin
rx_read <= '0; rx_ready <= '1;
tx_src <= '0; tx_src <= '0;
tx_valid <= '0; tx_valid <= '0;
packet_size <= '0; packet_size <= '0;
service_queue <= '0; service_buffer <= '0;
in_queue <= '0; curr_service <= '0;
rx2tx_map <= '0; end else if (rx_valid[curr_service]) begin
i <= 0;
end end
if (in_queue == 4'd0) begin // no one is in the queue yet curr_service <= curr_service + 1;
if (tx_valid != 4'd0) begin
for (i = 0; i < 3'd4; i++) begin
// TODO: write the logic for enqueuing
end
end
end else begin
end
end end
endmodule // mem_hub endmodule // mem_hub