# The Bootloader
Date: 2025-07-02

## Goals and expectations
Writing the bootloader logic for the fabric.  This is for easy scaling
of the buffer size.

And also add indicators (output logic) to signal the user and
interfaces that the fabric is ready.

## Results
Done.  A simple bootloader, much simpler than I expected, just a
simple FSM with some initializing logic.

Just some logic inside the `free_queue` module to initialize it when
the FPGA boots.

And in the meanwhile, I spawned a new server (one specifically for
running long term simulations), and also changed my shell to `fish`
from `zsh` for some more modern feel.

## Reflections
1. Once again, I am bemused by the simplicity of combinational logic.
   FSMs translate much better to SystemVerilog than to some
   sequentially executed logic like C.
2. Keep it simple.  A simple bootloader is much easier for future
   implementations compared to initializing through other means, and
   once complete, it's very scalable.
3. The plan isn't everything.  This wasn't part of the plan, the plan
   was to burn the initial values inside a hex file or some other
   methods that would allow instant initialization.  However, due to
   the elements of the `free_queue` being not byte-aligned, this would
   become much more trouble in the end.  The plan was modified
   accordingly.
4. Make the best out of the existing tools on hand.  This is a
   follow-up to the previous point.  Don't go into coding with only
   the plan and goals in mind, reassess when you've set foot on its
   grounds, weigh the options, and something else might just come up.
   
## Final thoughts
Find the right tools to do the right things.  Trying to simulate
clocked behaviors in C++ is as awkward as trying to write sequential
logic in SystemVerilog.

The first choice isn't always the best one, but the final choice
should the better one after weighing the options.

## Next steps
THORN!
