module tb;
   timeunit 1ns;
   timeprecision 1ps;

   logic sys_clk = 0;

   always #3.703 sys_clk = ~sys_clk;

   logic sclk = 0;
   logic cs = 1;
   logic mosi = 0;
   logic miso;
   logic rst_n = 0;
   string hello = {'b1111_0000_1111_0000, "_ABCD"};

   spi_slave dut (.sys_clk(sys_clk),
		  .mosi(mosi),
		  .cs(cs),
		  .sclk(sclk),
		  .miso(miso));
   initial begin
       #20 rst_n = 1;
   end

   task spi_test (input logic [7:0] tx_byte,
		  output logic [7:0] rx_byte);
       begin
	   cs = 0;
	   #30;
	   for(int idx = 1; idx < hello.len(); idx = idx + 1) begin
	       tx_byte = hello[idx];
	       $display("%0d=================================================", $time);
	       for (int i = 7; i >= 0; i = i - 1) begin
	           mosi = tx_byte[i];
                   sclk = 1;
                   #10;
                   sclk = 0;
	           rx_byte[i] = miso;
	           #10;
	           $display("[%0d] received bit: %b", $time, miso);
	       end // for (int i = 7; i >= 0; i = i - 1)
	       $display("[%0d] Sent: %c  |  %b", $time, tx_byte, tx_byte);
	       $display("[%0d] Received: %c (expected %c)", $time, rx_byte, hello[idx - 1] + 8'd1);
	       $display("[%0d] Received: %b (expected %b)", $time, rx_byte, hello[idx - 1] + 8'd1);
	       $display("%0d=================================================", $time);
	   end
	   cs = 1;
	   #40;
       end
   endtask // spi_test
   
   logic [7:0] tx_data = 8'd65;
   logic [7:0] rx_data;
   
   initial begin
       spi_test(tx_data, rx_data);
   end
endmodule // tb
