added tools, Makefile, and setup

.gitignore

@@ -1 +1,2 @@
 *.~undo-tree~
+*.dSYM~

.vscode/c_cpp_properties.json

@@ -0,0 +1,19 @@
+{
+    "configurations": [
+        {
+            "name": "Mac",
+            "includePath": [
+                "${workspaceFolder}/**"
+            ],
+            "defines": [],
+            "macFrameworkPath": [
+                "/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks"
+            ],
+            "compilerPath": "/usr/bin/clang",
+            "cStandard": "c17",
+            "cppStandard": "c++20",
+            "intelliSenseMode": "macos-clang-x64"
+        }
+    ],
+    "version": 4
+}

Makefile

@@ -0,0 +1,33 @@
+# Universal makefile for single C++ program
+#
+# Use gcc flag -MMD (user) or -MD (user/system) to generate dependencies among source files.
+# Use make default rules for commonly used file-name suffixes and make variables names.
+#
+# % make [ a.out ]
+
+########## Variables ##########
+
+CXX = g++					# compiler
+CXXFLAGS = -std=c++20 -g -Wall -MMD			# compiler flags
+MAKEFILE_NAME = ${firstword ${MAKEFILE_LIST}}	# makefile name
+
+SOURCES = $(wildcard *.cc)			# source files (*.cc)
+OBJECTS = ${SOURCES:.cc=.o}			# object files forming executable
+DEPENDS = ${OBJECTS:.o=.d}			# substitute ".o" with ".d"
+EXEC = a.out					# executable name
+
+########## Targets ##########
+
+.PHONY : clean					# not file names
+
+${EXEC} : ${OBJECTS}				# link step
+	${CXX} ${CXXFLAGS} $^ -o $@		# additional object files before $^
+
+${OBJECTS} : ${MAKEFILE_NAME}			# OPTIONAL : changes to this file => recompile
+
+# make implicitly generates rules to compile C++ files that generate .o files
+
+-include ${DEPENDS}				# include *.d files containing program dependences
+
+clean :						# remove files that can be regenerated
+	rm -f ${DEPENDS} ${OBJECTS} ${EXEC}

test.cc

@@ -0,0 +1,8 @@
+#include <iostream>
+
+using namespace std;
+
+int main()
+{
+  cout << "Hello, World!" << endl;
+}

tools/Makefile

@@ -0,0 +1,33 @@
+# Universal makefile for single C++ program
+#
+# Use gcc flag -MMD (user) or -MD (user/system) to generate dependencies among source files.
+# Use make default rules for commonly used file-name suffixes and make variables names.
+#
+# % make [ a.out ]
+
+########## Variables ##########
+
+CXX = g++-11					# compiler
+CXXFLAGS = -std=c++20 -g -Wall -MMD			# compiler flags
+MAKEFILE_NAME = ${firstword ${MAKEFILE_LIST}}	# makefile name
+
+SOURCES = $(wildcard *.cc)			# source files (*.cc)
+OBJECTS = ${SOURCES:.cc=.o}			# object files forming executable
+DEPENDS = ${OBJECTS:.o=.d}			# substitute ".o" with ".d"
+EXEC = a.out					# executable name
+
+########## Targets ##########
+
+.PHONY : clean					# not file names
+
+${EXEC} : ${OBJECTS}				# link step
+	${CXX} ${CXXFLAGS} $^ -o $@		# additional object files before $^
+
+${OBJECTS} : ${MAKEFILE_NAME}			# OPTIONAL : changes to this file => recompile
+
+# make implicitly generates rules to compile C++ files that generate .o files
+
+-include ${DEPENDS}				# include *.d files containing program dependences
+
+clean :						# remove files that can be regenerated
+	rm -f ${DEPENDS} ${OBJECTS} ${EXEC}

tools/compile

@@ -0,0 +1,25 @@
+#!/bin/bash
+# Use this script to compile your .cc files in dependency order
+
+# Arguments:
+#   $1 = name of file containing list of .cc files
+#   $2 = name of the output file
+
+cxx="g++-11"
+cxxflags="-std=c++20 -fmodules-ts -Wall -g"
+
+if [ $# -lt 1 ]; then
+  echo "Usage:  $0 list-filename [output-name]" 1>&2
+  exit 1
+fi
+
+if [ $# -eq 2 ]; then
+  name="-o $2"
+fi
+
+for x in $(cat $1); do
+  $cxx $cxxflags -c $x
+done
+
+$cxx *.o $name
+