mirror of
https://github.com/ggml-org/llama.cpp.git
synced 2025-11-19 11:57:07 +00:00
e95fec640f
* HIP: Disable ROCWMMA fatt on CDNA when compiled against ROCWMMA 2.0.0 rocwmma 2.0.0 includes a bug in the code fakeing fp16 accumulation on CDNA * CUDA: Fix volta condition in ggml_cuda_should_use_wmma_fattn
334 lines
12 KiB
Plaintext
334 lines
12 KiB
Plaintext
#include "common.cuh"
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#include "fattn-common.cuh"
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#include "fattn-mma-f16.cuh"
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#include "fattn-tile.cuh"
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#include "fattn-vec.cuh"
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#include "fattn-wmma-f16.cuh"
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#include "fattn.cuh"
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template <int DKQ, int DV, int ncols2>
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static void ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc;
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const ggml_tensor * Q = dst->src[0];
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if constexpr (ncols2 <= 8) {
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if (Q->ne[1] <= 8/ncols2) {
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ggml_cuda_flash_attn_ext_mma_f16_case<DKQ, DV, 8/ncols2, ncols2>(ctx, dst);
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return;
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}
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}
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if (Q->ne[1] <= 16/ncols2) {
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ggml_cuda_flash_attn_ext_mma_f16_case<DKQ, DV, 16/ncols2, ncols2>(ctx, dst);
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return;
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}
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if (ggml_cuda_highest_compiled_arch(cc) == GGML_CUDA_CC_TURING || Q->ne[1] <= 32/ncols2) {
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ggml_cuda_flash_attn_ext_mma_f16_case<DKQ, DV, 32/ncols2, ncols2>(ctx, dst);
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return;
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}
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ggml_cuda_flash_attn_ext_mma_f16_case<DKQ, DV, 64/ncols2, ncols2>(ctx, dst);
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}
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template <int DKQ, int DV>
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static void ggml_cuda_flash_attn_ext_mma_f16_switch_ncols2(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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const ggml_tensor * KQV = dst;
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const ggml_tensor * Q = dst->src[0];
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const ggml_tensor * K = dst->src[1];
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const ggml_tensor * mask = dst->src[3];
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float max_bias = 0.0f;
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memcpy(&max_bias, (const float *) KQV->op_params + 1, sizeof(float));
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const bool use_gqa_opt = mask && max_bias == 0.0f;
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GGML_ASSERT(Q->ne[2] % K->ne[2] == 0);
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const int gqa_ratio = Q->ne[2] / K->ne[2];
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if (use_gqa_opt && gqa_ratio % 8 == 0) {
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<DKQ, DV, 8>(ctx, dst);
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return;
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}
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if (use_gqa_opt && gqa_ratio % 4 == 0) {
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<DKQ, DV, 4>(ctx, dst);
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return;
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}
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if (use_gqa_opt && gqa_ratio % 2 == 0) {
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<DKQ, DV, 2>(ctx, dst);
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return;
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}
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<DKQ, DV, 1>(ctx, dst);
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}
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static void ggml_cuda_flash_attn_ext_mma_f16(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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const ggml_tensor * KQV = dst;
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const ggml_tensor * Q = dst->src[0];
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const ggml_tensor * K = dst->src[1];
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const ggml_tensor * V = dst->src[2];
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const ggml_tensor * mask = dst->src[3];
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switch (Q->ne[0]) {
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case 64:
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GGML_ASSERT(V->ne[0] == 64);
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols2< 64, 64>(ctx, dst);
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break;
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case 80:
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GGML_ASSERT(V->ne[0] == 80);
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols2< 80, 80>(ctx, dst);
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break;
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case 96:
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GGML_ASSERT(V->ne[0] == 96);
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols2< 96, 96>(ctx, dst);
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break;
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case 112:
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GGML_ASSERT(V->ne[0] == 112);
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols2<112, 112>(ctx, dst);
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break;
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case 128:
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GGML_ASSERT(V->ne[0] == 128);
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols2<128, 128>(ctx, dst);
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break;
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case 256:
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GGML_ASSERT(V->ne[0] == 256);
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols2<256, 256>(ctx, dst);
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break;
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case 576: {
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// For Deepseek, go straight to the ncols1 switch to avoid compiling unnecessary kernels.
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GGML_ASSERT(V->ne[0] == 512);
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float max_bias = 0.0f;
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memcpy(&max_bias, (const float *) KQV->op_params + 1, sizeof(float));
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const bool use_gqa_opt = mask && max_bias == 0.0f;
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GGML_ASSERT(use_gqa_opt);
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GGML_ASSERT(Q->ne[2] % K->ne[2] == 0);
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const int gqa_ratio = Q->ne[2] / K->ne[2];
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GGML_ASSERT(gqa_ratio % 16 == 0);
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ggml_cuda_flash_attn_ext_mma_f16_switch_ncols1<576, 512, 16>(ctx, dst);
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} break;
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default:
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GGML_ABORT("fatal error");
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break;
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}
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}
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#define FATTN_VEC_CASE(D, type_K, type_V) \
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if (Q->ne[0] == (D) && K->type == (type_K) && V->type == (type_V)) { \
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ggml_cuda_flash_attn_ext_vec_case<D, type_K, type_V>(ctx, dst); \
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return; \
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} \
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#define FATTN_VEC_CASES_ALL_D(type_K, type_V) \
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FATTN_VEC_CASE( 64, type_K, type_V) \
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FATTN_VEC_CASE(128, type_K, type_V) \
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FATTN_VEC_CASE(256, type_K, type_V) \
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static void ggml_cuda_flash_attn_ext_vec(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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ggml_tensor * Q = dst->src[0];
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ggml_tensor * K = dst->src[1];
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ggml_tensor * V = dst->src[2];
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#ifdef GGML_CUDA_FA_ALL_QUANTS
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_F16)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_F16)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_F16)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_F16)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_F16)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_F16)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_Q4_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q4_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_Q4_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_Q4_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_Q4_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q4_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_Q4_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q4_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_Q4_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_Q4_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_Q4_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q4_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_Q5_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q5_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_Q5_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_Q5_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_Q5_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q5_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_Q5_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q5_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_Q5_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_Q5_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_Q5_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q5_1)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_Q8_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q8_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_Q8_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_Q8_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_Q8_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q8_0)
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#else
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_F16)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q4_0)
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FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q8_0)
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#endif // GGML_CUDA_FA_ALL_QUANTS
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GGML_ABORT("fatal error");
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}
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// Best FlashAttention kernel for a specific GPU:
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enum best_fattn_kernel {
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BEST_FATTN_KERNEL_NONE = 0,
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BEST_FATTN_KERNEL_TILE = 200,
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BEST_FATTN_KERNEL_VEC = 100,
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BEST_FATTN_KERNEL_WMMA_F16 = 300,
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BEST_FATTN_KERNEL_MMA_F16 = 400,
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};
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static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const ggml_tensor * dst) {
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#ifndef FLASH_ATTN_AVAILABLE
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GGML_UNUSED(device); GGML_UNUSED(dst);
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return BEST_FATTN_KERNEL_NONE;
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#endif// FLASH_ATTN_AVAILABLE
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const ggml_tensor * Q = dst->src[0];
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const ggml_tensor * K = dst->src[1];
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const ggml_tensor * V = dst->src[2];
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const ggml_tensor * mask = dst->src[3];
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const int gqa_ratio = Q->ne[2] / K->ne[2];
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GGML_ASSERT(Q->ne[2] % K->ne[2] == 0);
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const int cc = ggml_cuda_info().devices[device].cc;
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switch (K->ne[0]) {
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case 64:
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case 128:
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case 256:
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if (V->ne[0] != K->ne[0]) {
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return BEST_FATTN_KERNEL_NONE;
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}
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break;
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case 80:
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case 96:
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case 112:
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if (V->ne[0] != K->ne[0]) {
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return BEST_FATTN_KERNEL_NONE;
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}
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if (!ggml_cuda_should_use_wmma_fattn(cc) && !turing_mma_available(cc)) {
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return BEST_FATTN_KERNEL_NONE;
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}
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break;
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case 576:
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if (V->ne[0] != 512) {
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return BEST_FATTN_KERNEL_NONE;
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}
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if (!turing_mma_available(cc) || gqa_ratio % 16 != 0) {
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return BEST_FATTN_KERNEL_NONE;
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}
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break;
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default:
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return BEST_FATTN_KERNEL_NONE;
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}
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#ifndef GGML_CUDA_FA_ALL_QUANTS
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if (K->type != V->type) {
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return BEST_FATTN_KERNEL_NONE;
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}
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#endif // GGML_CUDA_FA_ALL_QUANTS
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switch (K->type) {
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case GGML_TYPE_F16:
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break;
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case GGML_TYPE_Q4_1:
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case GGML_TYPE_Q5_0:
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case GGML_TYPE_Q5_1:
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#ifndef GGML_CUDA_FA_ALL_QUANTS
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return BEST_FATTN_KERNEL_NONE;
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#endif // GGML_CUDA_FA_ALL_QUANTS
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case GGML_TYPE_Q4_0:
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case GGML_TYPE_Q8_0:
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break;
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default:
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return BEST_FATTN_KERNEL_NONE;
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}
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if (mask && mask->ne[2] != 1) {
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return BEST_FATTN_KERNEL_NONE;
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}
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const bool can_use_vector_kernel = Q->ne[0] <= 256 && Q->ne[0] % 64 == 0;
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// If Turing tensor cores available, use them except for some cases with batch size 1:
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if (turing_mma_available(cc)) {
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best_fattn_kernel best = BEST_FATTN_KERNEL_MMA_F16;
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if (can_use_vector_kernel) {
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if (K->type == GGML_TYPE_F16 && V->type == GGML_TYPE_F16) {
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if (cc >= GGML_CUDA_CC_ADA_LOVELACE && Q->ne[1] == 1 && Q->ne[3] == 1 && !(gqa_ratio > 4 && K->ne[1] >= 8192)) {
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best = BEST_FATTN_KERNEL_VEC;
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}
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} else {
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if (cc >= GGML_CUDA_CC_ADA_LOVELACE) {
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if (Q->ne[1] <= 2) {
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best = BEST_FATTN_KERNEL_VEC;
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}
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} else {
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if (Q->ne[1] == 1) {
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best = BEST_FATTN_KERNEL_VEC;
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}
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}
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}
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if ((gqa_ratio % 2 != 0 || !mask) && Q->ne[1] == 1) {
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best = BEST_FATTN_KERNEL_VEC; // GQA-specific optimizations in the mma kernel do not apply.
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}
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}
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return best;
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}
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// Use kernels specialized for small batch sizes if possible:
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if (Q->ne[1] <= 8 && can_use_vector_kernel) {
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return BEST_FATTN_KERNEL_VEC;
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}
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// For large batch sizes, use the WMMA kernel if possible:
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if (ggml_cuda_should_use_wmma_fattn(cc)) {
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return BEST_FATTN_KERNEL_WMMA_F16;
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}
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// If there is no suitable kernel for tensor cores or small batch sizes, use the generic kernel for large batch sizes:
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return BEST_FATTN_KERNEL_TILE;
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}
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void ggml_cuda_flash_attn_ext(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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ggml_cuda_set_device(ctx.device);
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switch (ggml_cuda_get_best_fattn_kernel(ggml_cuda_get_device(), dst)) {
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case BEST_FATTN_KERNEL_NONE:
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GGML_ABORT("fatal error");
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case BEST_FATTN_KERNEL_TILE:
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ggml_cuda_flash_attn_ext_tile(ctx, dst);
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break;
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case BEST_FATTN_KERNEL_VEC:
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ggml_cuda_flash_attn_ext_vec(ctx, dst);
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break;
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case BEST_FATTN_KERNEL_WMMA_F16:
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ggml_cuda_flash_attn_ext_wmma_f16(ctx, dst);
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break;
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case BEST_FATTN_KERNEL_MMA_F16:
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ggml_cuda_flash_attn_ext_mma_f16(ctx, dst);
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break;
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}
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}
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bool ggml_cuda_flash_attn_ext_supported(int device, const ggml_tensor * dst) {
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return ggml_cuda_get_best_fattn_kernel(device, dst) != BEST_FATTN_KERNEL_NONE;
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}
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