mirror of
https://github.com/ggml-org/llama.cpp.git
synced 2025-10-28 08:31:25 +00:00
344 lines
13 KiB
Plaintext
344 lines
13 KiB
Plaintext
#include "mmq.cuh"
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#include "quantize.cuh"
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#include <vector>
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static void ggml_cuda_mul_mat_q_switch_type(ggml_backend_cuda_context & ctx, const mmq_args & args, cudaStream_t stream) {
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switch (args.type_x) {
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case GGML_TYPE_Q4_0:
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mul_mat_q_case<GGML_TYPE_Q4_0>(ctx, args, stream);
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break;
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case GGML_TYPE_Q4_1:
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mul_mat_q_case<GGML_TYPE_Q4_1>(ctx, args, stream);
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break;
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case GGML_TYPE_Q5_0:
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mul_mat_q_case<GGML_TYPE_Q5_0>(ctx, args, stream);
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break;
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case GGML_TYPE_Q5_1:
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mul_mat_q_case<GGML_TYPE_Q5_1>(ctx, args, stream);
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break;
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case GGML_TYPE_Q8_0:
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mul_mat_q_case<GGML_TYPE_Q8_0>(ctx, args, stream);
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break;
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case GGML_TYPE_MXFP4:
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mul_mat_q_case<GGML_TYPE_MXFP4>(ctx, args, stream);
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break;
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case GGML_TYPE_Q2_K:
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mul_mat_q_case<GGML_TYPE_Q2_K>(ctx, args, stream);
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break;
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case GGML_TYPE_Q3_K:
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mul_mat_q_case<GGML_TYPE_Q3_K>(ctx, args, stream);
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break;
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case GGML_TYPE_Q4_K:
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mul_mat_q_case<GGML_TYPE_Q4_K>(ctx, args, stream);
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break;
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case GGML_TYPE_Q5_K:
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mul_mat_q_case<GGML_TYPE_Q5_K>(ctx, args, stream);
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break;
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case GGML_TYPE_Q6_K:
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mul_mat_q_case<GGML_TYPE_Q6_K>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_XXS:
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mul_mat_q_case<GGML_TYPE_IQ2_XXS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_XS:
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mul_mat_q_case<GGML_TYPE_IQ2_XS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_S:
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mul_mat_q_case<GGML_TYPE_IQ2_S>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ3_XXS:
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mul_mat_q_case<GGML_TYPE_IQ3_XXS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ3_S:
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mul_mat_q_case<GGML_TYPE_IQ3_S>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ1_S:
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mul_mat_q_case<GGML_TYPE_IQ1_S>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ4_XS:
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mul_mat_q_case<GGML_TYPE_IQ4_XS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ4_NL:
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mul_mat_q_case<GGML_TYPE_IQ4_NL>(ctx, args, stream);
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break;
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default:
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GGML_ABORT("fatal error");
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break;
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}
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}
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void ggml_cuda_mul_mat_q(
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ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst) {
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GGML_ASSERT( src1->type == GGML_TYPE_F32);
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GGML_ASSERT( dst->type == GGML_TYPE_F32);
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GGML_ASSERT(!ids || ids->type == GGML_TYPE_I32); // Optional, used for batched GGML_MUL_MAT_ID.
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GGML_TENSOR_BINARY_OP_LOCALS;
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cudaStream_t stream = ctx.stream();
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const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc;
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const size_t ts_src0 = ggml_type_size(src0->type);
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const size_t ts_src1 = ggml_type_size(src1->type);
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const size_t ts_dst = ggml_type_size(dst->type);
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GGML_ASSERT( nb00 == ts_src0);
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GGML_ASSERT( nb10 == ts_src1);
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GGML_ASSERT( nb0 == ts_dst);
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GGML_ASSERT(!ids || ids->nb[0] == ggml_type_size(ids->type));
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const char * src0_d = (const char *) src0->data;
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const float * src1_d = (const float *) src1->data;
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float * dst_d = (float *) dst->data;
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// If src0 is a temporary compute buffer, clear any potential padding.
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if (ggml_backend_buffer_get_usage(src0->buffer) == GGML_BACKEND_BUFFER_USAGE_COMPUTE) {
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const size_t size_data = ggml_nbytes(src0);
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const size_t size_alloc = ggml_backend_buffer_get_alloc_size(src0->buffer, src0);
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if (size_alloc > size_data) {
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GGML_ASSERT(ggml_is_contiguously_allocated(src0));
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GGML_ASSERT(!src0->view_src);
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CUDA_CHECK(cudaMemsetAsync((char *) src0->data + size_data, 0, size_alloc - size_data, stream));
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}
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}
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const int64_t ne10_padded = GGML_PAD(ne10, MATRIX_ROW_PADDING);
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const int64_t s01 = src0->nb[1] / ts_src0;
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const int64_t s1 = dst->nb[1] / ts_dst;
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const int64_t s02 = src0->nb[2] / ts_src0;
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const int64_t s2 = dst->nb[2] / ts_dst;
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const int64_t s03 = src0->nb[3] / ts_src0;
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const int64_t s3 = dst->nb[3] / ts_dst;
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const bool use_stream_k = (GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA)
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|| GGML_CUDA_CC_IS_CDNA(cc);
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if (!ids) {
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const size_t nbytes_src1_q8_1 = ne13*ne12 * ne11*ne10_padded * sizeof(block_q8_1)/QK8_1 +
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get_mmq_x_max_host(cc)*sizeof(block_q8_1_mmq);
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ggml_cuda_pool_alloc<char> src1_q8_1(ctx.pool(), nbytes_src1_q8_1);
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{
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const int64_t s11 = src1->nb[1] / ts_src1;
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const int64_t s12 = src1->nb[2] / ts_src1;
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const int64_t s13 = src1->nb[3] / ts_src1;
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quantize_mmq_q8_1_cuda(src1_d, nullptr, src1_q8_1.get(), src0->type,
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ne10, s11, s12, s13, ne10_padded, ne11, ne12, ne13, stream);
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CUDA_CHECK(cudaGetLastError());
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}
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const int64_t s12 = ne11*ne10_padded * sizeof(block_q8_1)/(QK8_1*sizeof(int));
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const int64_t s13 = ne12*s12;
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const mmq_args args = {
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src0_d, src0->type, (const int *) src1_q8_1.ptr, nullptr, nullptr, dst_d,
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ne00, ne01, ne1, s01, ne11, s1,
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ne02, ne12, s02, s12, s2,
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ne03, ne13, s03, s13, s3,
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use_stream_k};
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ggml_cuda_mul_mat_q_switch_type(ctx, args, stream);
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return;
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}
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GGML_ASSERT(ne13 == 1);
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GGML_ASSERT(nb12 % nb11 == 0);
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GGML_ASSERT(nb2 % nb1 == 0);
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const int64_t n_expert_used = ids->ne[0];
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const int64_t ne_get_rows = ne12 * n_expert_used;
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std::vector<char> ids_host(ggml_nbytes(ids));
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std::vector<int32_t> ids_src1_host;
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ids_src1_host.reserve(ne_get_rows);
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std::vector<int32_t> ids_dst_host;
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ids_dst_host.reserve(ne_get_rows);
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std::vector<int32_t> tokens_per_expert_host(ne02);
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std::vector<int32_t> expert_bounds_host(ne02 + 1);
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ggml_cuda_pool_alloc<int32_t> ids_buf_dev(ctx.pool());
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CUDA_CHECK(cudaMemcpyAsync(ids_host.data(), ids->data, ggml_nbytes(ids), cudaMemcpyDeviceToHost, stream));
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CUDA_CHECK(cudaStreamSynchronize(stream));
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for (int64_t i02 = 0; i02 < ne02; ++i02) { // expert matrices
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for (int64_t i12 = 0; i12 < ne12; ++i12) { // tokens
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for (int64_t iex = 0; iex < n_expert_used; ++iex) {
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const int32_t expert_to_use = *(const int32_t *)(ids_host.data() + i12*ids->nb[1] + iex*ids->nb[0]);
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assert(expert_to_use >= 0 && expert_to_use < ne02);
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if (expert_to_use == i02) {
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ids_src1_host.push_back(i12*(nb12/nb11) + iex % ne11);
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ids_dst_host.push_back(i12*ne1 + iex);
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tokens_per_expert_host[i02]++;
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break;
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}
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}
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}
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}
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int32_t cumsum = 0;
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for (int64_t i = 0; i < ne02; ++i) {
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expert_bounds_host[i] = cumsum;
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cumsum += tokens_per_expert_host[i];
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}
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expert_bounds_host[ne02] = cumsum;
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std::vector<int32_t> ids_buf_host;
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ids_buf_host.reserve(ids_src1_host.size() + ids_dst_host.size() + expert_bounds_host.size());
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ids_buf_host.insert(ids_buf_host.end(), ids_src1_host.begin(), ids_src1_host.end());
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ids_buf_host.insert(ids_buf_host.end(), ids_dst_host.begin(), ids_dst_host.end());
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ids_buf_host.insert(ids_buf_host.end(), expert_bounds_host.begin(), expert_bounds_host.end());
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ids_buf_dev.alloc(ids_buf_host.size() + get_mmq_x_max_host(cc)); // Expert bounds are padded on device.
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CUDA_CHECK(cudaMemcpyAsync(ids_buf_dev.ptr, ids_buf_host.data(), ids_buf_host.size()*sizeof(int32_t), cudaMemcpyHostToDevice, stream));
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CUDA_CHECK(cudaStreamSynchronize(stream));
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const int32_t * ids_src1_dev = ids_buf_dev.ptr;
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const int32_t * ids_dst_dev = ids_src1_dev + ids_src1_host.size();
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const int32_t * expert_bounds_dev = ids_dst_dev + ids_dst_host.size();
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const size_t nbytes_src1_q8_1 = ne12*n_expert_used*ne10_padded * sizeof(block_q8_1)/QK8_1 +
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get_mmq_x_max_host(cc)*sizeof(block_q8_1_mmq);
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ggml_cuda_pool_alloc<char> src1_q8_1(ctx.pool(), nbytes_src1_q8_1);
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const int64_t ne11_flat = ne12*n_expert_used;
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const int64_t ne12_flat = 1;
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const int64_t ne13_flat = 1;
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{
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const int64_t s11 = src1->nb[1] / ts_src1;
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const int64_t s12 = src1->nb[2] / ts_src1;
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const int64_t s13 = src1->nb[2] / ts_src1;
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quantize_mmq_q8_1_cuda(src1_d, ids_src1_dev, src1_q8_1.get(), src0->type,
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ne10, s11, s12, s13, ne10_padded, ne11_flat, ne12_flat, ne13_flat, stream);
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CUDA_CHECK(cudaGetLastError());
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}
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const int64_t s12 = ne11*ne10_padded * sizeof(block_q8_1)/(QK8_1*sizeof(int));
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const int64_t s13 = ne12*s12;
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// Note that ne02 is used instead of ne12 because the number of y channels determines the z dimension of the CUDA grid.
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const mmq_args args = {
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src0_d, src0->type, (const int *) src1_q8_1.ptr, ids_dst_dev, expert_bounds_dev, dst_d,
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ne00, ne01, ne_get_rows, s01, ne_get_rows, s1,
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ne02, ne02, s02, s12, s2,
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ne03, ne13, s03, s13, s3,
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use_stream_k};
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ggml_cuda_mul_mat_q_switch_type(ctx, args, stream);
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}
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void ggml_cuda_op_mul_mat_q(
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ggml_backend_cuda_context & ctx,
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const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, const char * src0_dd_i, const float * src1_ddf_i,
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const char * src1_ddq_i, float * dst_dd_i, const int64_t row_low, const int64_t row_high, const int64_t src1_ncols,
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const int64_t src1_padded_row_size, cudaStream_t stream) {
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const int64_t ne00 = src0->ne[0];
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const int64_t ne10 = src1->ne[0];
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const int64_t ne11 = src1->ne[1];
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GGML_ASSERT(ne10 % QK8_1 == 0);
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const int64_t ne0 = dst->ne[0];
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const int64_t row_diff = row_high - row_low;
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const int64_t stride01 = ne00 / ggml_blck_size(src0->type);
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const int id = ggml_cuda_get_device();
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const int cc = ggml_cuda_info().devices[id].cc;
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// the main device has a larger memory buffer to hold the results from all GPUs
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// nrows_dst == nrows of the matrix that the kernel writes into
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const int64_t nrows_dst = id == ctx.device ? ne0 : row_diff;
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// The stream-k decomposition is only faster for recent NVIDIA GPUs.
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// Also its fixup needs to allocate a temporary buffer in the memory pool.
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// There are multiple parallel CUDA streams for src1_ncols != ne11 which would introduce a race condition for this buffer.
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const bool use_stream_k = ((GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA)
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|| GGML_CUDA_CC_IS_CDNA(cc))
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&& src1_ncols == ne11;
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const mmq_args args = {
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src0_dd_i, src0->type, (const int *) src1_ddq_i, nullptr, nullptr, dst_dd_i,
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ne00, row_diff, src1_ncols, stride01, ne11, nrows_dst,
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1, 1, 0, 0, 0,
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1, 1, 0, 0, 0,
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use_stream_k};
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ggml_cuda_mul_mat_q_switch_type(ctx, args, stream);
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GGML_UNUSED_VARS(src1, dst, src1_ddf_i, src1_padded_row_size);
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}
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bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11) {
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#ifdef GGML_CUDA_FORCE_CUBLAS
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return false;
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#endif // GGML_CUDA_FORCE_CUBLAS
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bool mmq_supported;
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switch (type) {
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case GGML_TYPE_Q4_0:
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case GGML_TYPE_Q4_1:
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case GGML_TYPE_Q5_0:
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case GGML_TYPE_Q5_1:
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case GGML_TYPE_Q8_0:
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case GGML_TYPE_MXFP4:
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case GGML_TYPE_Q2_K:
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case GGML_TYPE_Q3_K:
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case GGML_TYPE_Q4_K:
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case GGML_TYPE_Q5_K:
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case GGML_TYPE_Q6_K:
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case GGML_TYPE_IQ2_XXS:
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case GGML_TYPE_IQ2_XS:
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case GGML_TYPE_IQ2_S:
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case GGML_TYPE_IQ3_XXS:
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case GGML_TYPE_IQ3_S:
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case GGML_TYPE_IQ1_S:
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case GGML_TYPE_IQ4_XS:
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case GGML_TYPE_IQ4_NL:
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mmq_supported = true;
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break;
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default:
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mmq_supported = false;
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break;
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}
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if (!mmq_supported) {
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return false;
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}
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if (turing_mma_available(cc)) {
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return true;
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}
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if (ggml_cuda_highest_compiled_arch(cc) < GGML_CUDA_CC_DP4A) {
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return false;
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}
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#ifdef GGML_CUDA_FORCE_MMQ
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return true;
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#endif //GGML_CUDA_FORCE_MMQ
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if (GGML_CUDA_CC_IS_NVIDIA(cc)) {
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return !fp16_mma_hardware_available(cc) || ne11 < MMQ_DP4A_MAX_BATCH_SIZE;
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}
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if (amd_mfma_available(cc)) {
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// As of ROCM 7.0 rocblas/tensile performs very poorly on CDNA3 and hipblaslt (via ROCBLAS_USE_HIPBLASLT)
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// performs better but is currently suffering from a crash on this architecture.
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// TODO: Revisit when hipblaslt is fixed on CDNA3
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if (GGML_CUDA_CC_IS_CDNA3(cc)) {
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return true;
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}
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if (ne11 <= 128 || type == GGML_TYPE_Q4_0 || type == GGML_TYPE_Q4_1 || type == GGML_TYPE_Q5_0 || type == GGML_TYPE_Q5_1) {
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return true;
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}
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if (ne11 <= 256 && (type == GGML_TYPE_Q4_K || type == GGML_TYPE_Q5_K)) {
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return true;
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}
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return false;
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}
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return (!GGML_CUDA_CC_IS_RDNA4(cc) && !GGML_CUDA_CC_IS_RDNA3(cc) && !GGML_CUDA_CC_IS_CDNA(cc)) || ne11 < MMQ_DP4A_MAX_BATCH_SIZE;
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}
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