From ca4844062b3f0679a39b76b2fe95ba87cd6fb00d Mon Sep 17 00:00:00 2001 From: ixgbe <1113177880@qq.com> Date: Tue, 11 Nov 2025 19:41:51 +0800 Subject: [PATCH] ggml-cpu : add RISC-V RVV (Zvfh) optimization for FP16 to FP32 conversion (#17161) Signed-off-by: Wang Yang --- ggml/src/ggml-cpu/ggml-cpu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/ggml/src/ggml-cpu/ggml-cpu.c b/ggml/src/ggml-cpu/ggml-cpu.c index 086708bae0..d8e3c48c60 100644 --- a/ggml/src/ggml-cpu/ggml-cpu.c +++ b/ggml/src/ggml-cpu/ggml-cpu.c @@ -3274,6 +3274,13 @@ void ggml_cpu_fp16_to_fp32(const ggml_fp16_t * x, float * y, int64_t n) { __m128 y_vec = _mm_cvtph_ps(x_vec); _mm_storeu_ps(y + i, y_vec); } +#elif defined(__riscv_zvfh) + for (int vl; i < n; i += vl) { + vl = __riscv_vsetvl_e16m1(n - i); + vfloat16m1_t vx = __riscv_vle16_v_f16m1((_Float16 *)&x[i], vl); + vfloat32m2_t vy = __riscv_vfwcvt_f_f_v_f32m2(vx, vl); + __riscv_vse32_v_f32m2(&y[i], vy, vl); + } #endif for (; i < n; ++i) {