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CUDA: refactor and deduplicate vector FA kernels (#16208)
* CUDA: refactor and deduplicate vector FA kernels
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@@ -586,17 +586,42 @@ static __device__ __forceinline__ void ggml_cuda_mad(float & acc, const half2 v,
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#endif // defined(GGML_USE_HIP) && (defined(RDNA2) || defined(RDNA3) || defined(RDNA4) || defined(GCN5) || defined(CDNA))
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}
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static __device__ __forceinline__ void ggml_cuda_mad(half2 & acc, const half2 v, const half2 u) {
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#ifdef FAST_FP16_AVAILABLE
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acc += v*u;
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#else
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const float2 tmpv = __half22float2(v);
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const float2 tmpu = __half22float2(u);
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float2 tmpacc = __half22float2(acc);
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tmpacc.x += tmpv.x * tmpu.x;
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tmpacc.y += tmpv.y * tmpu.y;
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acc = make_half2(tmpacc.x, tmpacc.y);
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#endif // FAST_FP16_AVAILABLE
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}
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// Aligned memory transfers of 8/16 bytes can be faster than 2 transfers with 4 bytes, especially on AMD.
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template <int nbytes>
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template <int nbytes, int alignment = 0>
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static __device__ __forceinline__ void ggml_cuda_memcpy_1(void * __restrict__ dst, const void * __restrict__ src) {
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if constexpr (nbytes == 4) {
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*(int *) dst = *(const int *) src;
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} else if constexpr (nbytes == 8) {
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*(int2 *) dst = *(const int2 *) src;
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} else if constexpr (nbytes == 16) {
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*(int4 *) dst = *(const int4 *) src;
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} else {
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static_assert(nbytes == 0 && nbytes == -1, "bad nbytes");
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if constexpr (alignment != 0) {
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static_assert(nbytes % alignment == 0, "bad alignment");
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}
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constexpr int nb_per_cpy = alignment == 0 ? nbytes : alignment;
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#pragma unroll
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for (int i = 0; i < nbytes/nb_per_cpy; ++i) {
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if constexpr (nb_per_cpy == 1) {
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((char *) dst)[i] = ((const char *) src)[i];
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} else if constexpr (nb_per_cpy == 2) {
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((short *) dst)[i] = ((const short *) src)[i];
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} else if constexpr (nb_per_cpy == 4) {
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((int *) dst)[i] = ((const int *) src)[i];
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} else if constexpr (nb_per_cpy == 8) {
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((int2 *) dst)[i] = ((const int2 *) src)[i];
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} else if constexpr (nb_per_cpy == 16) {
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((int4 *) dst)[i] = ((const int4 *) src)[i];
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} else {
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static_assert(nbytes == 0 && nbytes == -1, "bad nbytes");
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}
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}
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}
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