diff --git a/.devops/cann.Dockerfile b/.devops/cann.Dockerfile new file mode 100644 index 0000000000..02f3e03b5e --- /dev/null +++ b/.devops/cann.Dockerfile @@ -0,0 +1,130 @@ +# ============================================================================== +# ARGUMENTS +# ============================================================================== + +# Define the CANN base image for easier version updates later +ARG CANN_BASE_IMAGE=quay.io/ascend/cann:8.1.rc1-910b-openeuler22.03-py3.10 + +# ============================================================================== +# BUILD STAGE +# Compile all binary files and libraries +# ============================================================================== +FROM ${CANN_BASE_IMAGE} AS build + +# Define the Ascend chip model for compilation. Default is Ascend910B3 +ARG ASCEND_SOC_TYPE=Ascend910B3 + +# -- Install build dependencies -- +RUN yum install -y gcc g++ cmake make git libcurl-devel python3 python3-pip && \ + yum clean all && \ + rm -rf /var/cache/yum + +# -- Set the working directory -- +WORKDIR /app + +# -- Copy project files -- +COPY . . + +# -- Set CANN environment variables (required for compilation) -- +# Using ENV instead of `source` allows environment variables to persist across the entire image layer +ENV ASCEND_TOOLKIT_HOME=/usr/local/Ascend/ascend-toolkit/latest +ENV LD_LIBRARY_PATH=${ASCEND_TOOLKIT_HOME}/lib64:${LD_LIBRARY_PATH} +ENV PATH=${ASCEND_TOOLKIT_HOME}/bin:${PATH} +ENV ASCEND_OPP_PATH=${ASCEND_TOOLKIT_HOME}/opp +ENV LD_LIBRARY_PATH=${ASCEND_TOOLKIT_HOME}/runtime/lib64/stub:$LD_LIBRARY_PATH +# ... You can add other environment variables from the original file as needed ... +# For brevity, only core variables are listed here. You can paste the original ENV list here. + +# -- Build llama.cpp -- +# Use the passed ASCEND_SOC_TYPE argument and add general build options +RUN source /usr/local/Ascend/ascend-toolkit/set_env.sh --force \ + && \ + cmake -B build \ + -DGGML_CANN=ON \ + -DCMAKE_BUILD_TYPE=Release \ + -DSOC_TYPE=${ASCEND_SOC_TYPE} \ + . && \ + cmake --build build --config Release -j$(nproc) + +# -- Organize build artifacts for copying in later stages -- +# Create a lib directory to store all .so files +RUN mkdir -p /app/lib && \ + find build -name "*.so" -exec cp {} /app/lib \; + +# Create a full directory to store all executables and Python scripts +RUN mkdir -p /app/full && \ + cp build/bin/* /app/full/ && \ + cp *.py /app/full/ && \ + cp -r gguf-py /app/full/ && \ + cp -r requirements /app/full/ && \ + cp requirements.txt /app/full/ + # If you have a tools.sh script, make sure it is copied here + # cp .devops/tools.sh /app/full/tools.sh + +# ============================================================================== +# BASE STAGE +# Create a minimal base image with CANN runtime and common libraries +# ============================================================================== +FROM ${CANN_BASE_IMAGE} AS base + +# -- Install runtime dependencies -- +RUN yum install -y libgomp curl && \ + yum clean all && \ + rm -rf /var/cache/yum + +# -- Set CANN environment variables (required for runtime) -- +ENV ASCEND_TOOLKIT_HOME=/usr/local/Ascend/ascend-toolkit/latest +ENV LD_LIBRARY_PATH=/app:${ASCEND_TOOLKIT_HOME}/lib64:${LD_LIBRARY_PATH} +ENV PATH=${ASCEND_TOOLKIT_HOME}/bin:${PATH} +ENV ASCEND_OPP_PATH=${ASCEND_TOOLKIT_HOME}/opp +# ... You can add other environment variables from the original file as needed ... + +WORKDIR /app + +# Copy compiled .so files from the build stage +COPY --from=build /app/lib/ /app + +# ============================================================================== +# FINAL STAGES (TARGETS) +# ============================================================================== + +### Target: full +# Complete image with all tools, Python bindings, and dependencies +# ============================================================================== +FROM base AS full + +COPY --from=build /app/full /app + +# Install Python dependencies +RUN yum install -y git python3 python3-pip && \ + pip3 install --no-cache-dir --upgrade pip setuptools wheel && \ + pip3 install --no-cache-dir -r requirements.txt && \ + yum clean all && \ + rm -rf /var/cache/yum + +# You need to provide a tools.sh script as the entrypoint +ENTRYPOINT ["/app/tools.sh"] +# If there is no tools.sh, you can set the default to start the server +# ENTRYPOINT ["/app/llama-server"] + +### Target: light +# Lightweight image containing only llama-cli +# ============================================================================== +FROM base AS light + +COPY --from=build /app/full/llama-cli /app + +ENTRYPOINT [ "/app/llama-cli" ] + +### Target: server +# Dedicated server image containing only llama-server +# ============================================================================== +FROM base AS server + +ENV LLAMA_ARG_HOST=0.0.0.0 + +COPY --from=build /app/full/llama-server /app + +HEALTHCHECK --interval=5m CMD [ "curl", "-f", "http://localhost:8080/health" ] + +ENTRYPOINT [ "/app/llama-server" ] diff --git a/.devops/cloud-v-pipeline b/.devops/cloud-v-pipeline deleted file mode 100644 index af8c0cea61..0000000000 --- a/.devops/cloud-v-pipeline +++ /dev/null @@ -1,22 +0,0 @@ -node('x86_runner1'){ // Running on x86 runner containing latest vector qemu, latest vector gcc and all the necessary libraries - stage('Cleanup'){ - cleanWs() // Cleaning previous CI build in workspace - } - stage('checkout repo'){ - retry(5){ // Retry if the cloning fails due to some reason - checkout scm // Clone the repo on Runner - } - } - stage('Compiling llama.cpp'){ - sh'''#!/bin/bash - make RISCV=1 RISCV_CROSS_COMPILE=1 # Compiling llama for RISC-V - ''' - } - stage('Running llama.cpp'){ - sh'''#!/bin/bash - module load gnu-bin2/0.1 # loading latest versions of vector qemu and vector gcc - qemu-riscv64 -L /softwares/gnu-bin2/sysroot -cpu rv64,v=true,vlen=256,elen=64,vext_spec=v1.0 ./llama-cli -m /home/alitariq/codellama-7b.Q4_K_M.gguf -p "Anything" -n 9 > llama_log.txt # Running llama.cpp on vector qemu-riscv64 - cat llama_log.txt # Printing results - ''' - } -} diff --git a/.devops/cpu.Dockerfile b/.devops/cpu.Dockerfile index 9459f08c10..e1bb7d4675 100644 --- a/.devops/cpu.Dockerfile +++ b/.devops/cpu.Dockerfile @@ -4,8 +4,6 @@ FROM ubuntu:$UBUNTU_VERSION AS build ARG TARGETARCH -ARG GGML_CPU_ARM_ARCH=armv8-a - RUN apt-get update && \ apt-get install -y build-essential git cmake libcurl4-openssl-dev @@ -13,10 +11,8 @@ WORKDIR /app COPY . . -RUN if [ "$TARGETARCH" = "amd64" ]; then \ +RUN if [ "$TARGETARCH" = "amd64" ] || [ "$TARGETARCH" = "arm64" ]; then \ cmake -S . -B build -DCMAKE_BUILD_TYPE=Release -DGGML_NATIVE=OFF -DLLAMA_BUILD_TESTS=OFF -DGGML_BACKEND_DL=ON -DGGML_CPU_ALL_VARIANTS=ON; \ - elif [ "$TARGETARCH" = "arm64" ]; then \ - cmake -S . -B build -DCMAKE_BUILD_TYPE=Release -DGGML_NATIVE=OFF -DLLAMA_BUILD_TESTS=OFF -DGGML_CPU_ARM_ARCH=${GGML_CPU_ARM_ARCH}; \ else \ echo "Unsupported architecture"; \ exit 1; \ diff --git a/.devops/cuda.Dockerfile b/.devops/cuda.Dockerfile index 94f1433972..f9dc7f3163 100644 --- a/.devops/cuda.Dockerfile +++ b/.devops/cuda.Dockerfile @@ -60,8 +60,7 @@ RUN apt-get update \ git \ python3 \ python3-pip \ - && pip install --upgrade pip setuptools wheel \ - && pip install -r requirements.txt \ + && pip install --break-system-packages -r requirements.txt \ && apt autoremove -y \ && apt clean -y \ && rm -rf /tmp/* /var/tmp/* \ diff --git a/.devops/musa.Dockerfile b/.devops/musa.Dockerfile index 87ce2393f6..b0c86dccd5 100644 --- a/.devops/musa.Dockerfile +++ b/.devops/musa.Dockerfile @@ -1,10 +1,10 @@ ARG UBUNTU_VERSION=22.04 # This needs to generally match the container host's environment. -ARG MUSA_VERSION=rc4.0.1 +ARG MUSA_VERSION=rc4.2.0 # Target the MUSA build image -ARG BASE_MUSA_DEV_CONTAINER=mthreads/musa:${MUSA_VERSION}-mudnn-devel-ubuntu${UBUNTU_VERSION} +ARG BASE_MUSA_DEV_CONTAINER=mthreads/musa:${MUSA_VERSION}-devel-ubuntu${UBUNTU_VERSION}-amd64 -ARG BASE_MUSA_RUN_CONTAINER=mthreads/musa:${MUSA_VERSION}-mudnn-runtime-ubuntu${UBUNTU_VERSION} +ARG BASE_MUSA_RUN_CONTAINER=mthreads/musa:${MUSA_VERSION}-runtime-ubuntu${UBUNTU_VERSION}-amd64 FROM ${BASE_MUSA_DEV_CONTAINER} AS build diff --git a/.devops/rocm.Dockerfile b/.devops/rocm.Dockerfile index 1c00f1b9c2..cf19e6e028 100644 --- a/.devops/rocm.Dockerfile +++ b/.devops/rocm.Dockerfile @@ -1,8 +1,8 @@ ARG UBUNTU_VERSION=24.04 # This needs to generally match the container host's environment. -ARG ROCM_VERSION=6.3 -ARG AMDGPU_VERSION=6.3 +ARG ROCM_VERSION=6.4 +ARG AMDGPU_VERSION=6.4 # Target the CUDA build image ARG BASE_ROCM_DEV_CONTAINER=rocm/dev-ubuntu-${UBUNTU_VERSION}:${ROCM_VERSION}-complete diff --git a/.github/workflows/build-riscv-native.yml b/.github/workflows/build-riscv-native.yml new file mode 100644 index 0000000000..a968f6d519 --- /dev/null +++ b/.github/workflows/build-riscv-native.yml @@ -0,0 +1,43 @@ +name: Build on RISCV Linux Machine by Cloud-V +on: + workflow_dispatch: + workflow_call: + +jobs: + bianbu-riscv64-native: # Bianbu 2.2 + runs-on: self-hosted + + steps: + - name: Install prerequisites + run: | + sudo apt-get update || true + sudo apt-get install -y libatomic1 + - uses: actions/checkout@v4 + - name: Setup Riscv + run: | + sudo apt-get update || true + sudo apt-get install -y --no-install-recommends \ + build-essential \ + gcc-14-riscv64-linux-gnu \ + g++-14-riscv64-linux-gnu \ + cmake + + - name: Build + run: | + cmake -B build -DLLAMA_CURL=OFF \ + -DCMAKE_BUILD_TYPE=Release \ + -DGGML_OPENMP=OFF \ + -DLLAMA_BUILD_EXAMPLES=ON \ + -DLLAMA_BUILD_TOOLS=ON \ + -DLLAMA_BUILD_TESTS=OFF \ + -DCMAKE_SYSTEM_NAME=Linux \ + -DCMAKE_SYSTEM_PROCESSOR=riscv64 \ + -DCMAKE_C_COMPILER=riscv64-linux-gnu-gcc-14 \ + -DCMAKE_CXX_COMPILER=riscv64-linux-gnu-g++-14 \ + -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ + -DCMAKE_FIND_ROOT_PATH=/usr/lib/riscv64-linux-gnu \ + -DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=NEVER \ + -DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \ + -DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=BOTH + + cmake --build build --config Release -j $(nproc) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 5bd988b7f7..d4ed3ce7e1 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -159,31 +159,15 @@ jobs: - name: Dawn Dependency id: dawn-depends run: | - ARTIFACTS_JSON=$(curl -s -L \ - -H "Accept: application/vnd.github+json" \ - -H "Authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \ - -H "X-GitHub-Api-Version: 2022-11-28" \ - "https://api.github.com/repos/google/dawn/actions/artifacts") - echo "Finding latest macos-latest-Release artifact..." - DOWNLOAD_URL=$(echo "$ARTIFACTS_JSON" | jq -r '.artifacts - | sort_by(.created_at) - | reverse - | map(select(.name | test("macos-latest-Release$"))) - | .[0].archive_download_url') - if [ "$DOWNLOAD_URL" = "null" ] || [ -z "$DOWNLOAD_URL" ]; then - echo "No suitable Dawn artifact found!" - exit 1 - fi - echo "Downloading from: $DOWNLOAD_URL" - curl -L \ - -H "Accept: application/vnd.github+json" \ - -H "Authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \ - -o artifact.zip "$DOWNLOAD_URL" - unzip artifact.zip + DAWN_VERSION="v1.0.0" + DAWN_OWNER="reeselevine" + DAWN_REPO="dawn" + DAWN_ASSET_NAME="Dawn-a1a6b45cced25a3b7f4fb491e0ae70796cc7f22b-macos-latest-Release.tar.gz" + echo "Fetching release asset from https://github.com/${DAWN_OWNER}/${DAWN_REPO}/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}" + curl -L -o artifact.tar.gz \ + "https://github.com/${DAWN_OWNER}/${DAWN_REPO}/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}" mkdir dawn - tar_file=$(find . -name '*.tar.gz' | head -n 1) - echo "Extracting: $tar_file" - tar -xvf "$tar_file" -C dawn --strip-components=1 + tar -xvf artifact.tar.gz -C dawn --strip-components=1 - name: Build id: cmake_build @@ -433,31 +417,15 @@ jobs: id: dawn-depends run: | sudo apt-get install -y libxrandr-dev libxinerama-dev libxcursor-dev mesa-common-dev libx11-xcb-dev libxi-dev - ARTIFACTS_JSON=$(curl -s -L \ - -H "Accept: application/vnd.github+json" \ - -H "Authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \ - -H "X-GitHub-Api-Version: 2022-11-28" \ - "https://api.github.com/repos/google/dawn/actions/artifacts") - echo "Finding latest ubuntu-latest-Release artifact..." - DOWNLOAD_URL=$(echo "$ARTIFACTS_JSON" | jq -r '.artifacts - | sort_by(.created_at) - | reverse - | map(select(.name | test("ubuntu-latest-Release$"))) - | .[0].archive_download_url') - if [ "$DOWNLOAD_URL" = "null" ] || [ -z "$DOWNLOAD_URL" ]; then - echo "No suitable Dawn artifact found!" - exit 1 - fi - echo "Downloading from: $DOWNLOAD_URL" - curl -L \ - -H "Accept: application/vnd.github+json" \ - -H "Authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \ - -o artifact.zip "$DOWNLOAD_URL" - unzip artifact.zip + DAWN_VERSION="v1.0.0" + DAWN_OWNER="reeselevine" + DAWN_REPO="dawn" + DAWN_ASSET_NAME="Dawn-a1a6b45cced25a3b7f4fb491e0ae70796cc7f22b-ubuntu-latest-Release.tar.gz" + echo "Fetching release asset from https://github.com/${DAWN_OWNER}/${DAWN_REPO}/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}" + curl -L -o artifact.tar.gz \ + "https://github.com/${DAWN_OWNER}/${DAWN_REPO}/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}" mkdir dawn - tar_file=$(find . -name '*.tar.gz' | head -n 1) - echo "Extracting: $tar_file" - tar -xvf "$tar_file" -C dawn --strip-components=1 + tar -xvf artifact.tar.gz -C dawn --strip-components=1 - name: Build id: cmake_build @@ -475,7 +443,7 @@ jobs: ubuntu-22-cmake-hip: runs-on: ubuntu-22.04 - container: rocm/dev-ubuntu-22.04:6.0.2 + container: rocm/dev-ubuntu-22.04:6.1.2 steps: - name: Clone @@ -503,19 +471,9 @@ jobs: -DGGML_HIP=ON cmake --build build --config Release -j $(nproc) - - name: Build with legacy HIP support - id: cmake_build_legacy_hip - run: | - cmake -B build2 -S . \ - -DCMAKE_C_COMPILER=hipcc \ - -DCMAKE_CXX_COMPILER=hipcc \ - -DGGML_HIP_ROCWMMA_FATTN=ON \ - -DGGML_HIP=ON - cmake --build build2 --config Release -j $(nproc) - ubuntu-22-cmake-musa: runs-on: ubuntu-22.04 - container: mthreads/musa:rc4.0.1-mudnn-devel-ubuntu22.04 + container: mthreads/musa:rc4.2.0-devel-ubuntu22.04-amd64 steps: - name: Clone diff --git a/.github/workflows/close-issue.yml b/.github/workflows/close-issue.yml index 276a217d45..19e7854745 100644 --- a/.github/workflows/close-issue.yml +++ b/.github/workflows/close-issue.yml @@ -17,7 +17,7 @@ jobs: steps: - uses: actions/stale@v5 with: - exempt-issue-labels: "refactor,help wanted,good first issue,research,bug,roadmap" + exempt-issue-labels: "refactoring,help wanted,good first issue,research,bug,roadmap" days-before-issue-stale: 30 days-before-issue-close: 14 stale-issue-label: "stale" diff --git a/.github/workflows/copilot-setup-steps.yml b/.github/workflows/copilot-setup-steps.yml new file mode 100644 index 0000000000..a6553187ef --- /dev/null +++ b/.github/workflows/copilot-setup-steps.yml @@ -0,0 +1,53 @@ +name: "Copilot Setup Steps" + +# Automatically run the setup steps when they are changed to allow for easy validation, and +# allow manual testing through the repository's "Actions" tab +on: + workflow_dispatch: + push: + paths: + - .github/workflows/copilot-setup-steps.yml + pull_request: + paths: + - .github/workflows/copilot-setup-steps.yml + +jobs: + # The job MUST be called `copilot-setup-steps` or it will not be picked up by Copilot. + copilot-setup-steps: + runs-on: ubuntu-latest + + # Set the permissions to the lowest permissions possible needed for your steps. + # Copilot will be given its own token for its operations. + permissions: + # If you want to clone the repository as part of your setup steps, for example to install dependencies, you'll need the `contents: read` permission. If you don't clone the repository in your setup steps, Copilot will do this for you automatically after the steps complete. + contents: read + + # You can define any steps you want, and they will run before the agent starts. + # If you do not check out your code, Copilot will do this for you. + steps: + - name: Checkout code + uses: actions/checkout@v4 + + - name: ccache + uses: hendrikmuhs/ccache-action@v1.2.16 + with: + key: copilot-setup-steps + evict-old-files: 1d + + - name: Dependencies + id: depends + run: | + sudo apt-get update + sudo apt-get install build-essential libcurl4-openssl-dev + + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: '3.11' + + - name: Install Python dependencies + run: | + python3 -m venv .venv + .venv/bin/activate + pip install -r requirements/requirements-all.txt -r tools/server/tests/requirements.txt + pip install flake8 pyright diff --git a/.github/workflows/pre-tokenizer-hashes.yml b/.github/workflows/pre-tokenizer-hashes.yml new file mode 100644 index 0000000000..dff998e239 --- /dev/null +++ b/.github/workflows/pre-tokenizer-hashes.yml @@ -0,0 +1,45 @@ +name: Check Pre-Tokenizer Hashes + +on: + push: + paths: + - 'convert_hf_to_gguf.py' + - 'convert_hf_to_gguf_update.py' + pull_request: + paths: + - 'convert_hf_to_gguf.py' + - 'convert_hf_to_gguf_update.py' + +jobs: + pre-tokenizer-hashes: + runs-on: ubuntu-latest + + steps: + - name: Checkout repository + uses: actions/checkout@v4 + + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: '3.11' + + - name: Install Python dependencies + run: | + python3 -m venv .venv + .venv/bin/pip install -r requirements/requirements-convert_hf_to_gguf_update.txt + + - name: Update pre-tokenizer hashes + run: | + cp convert_hf_to_gguf.py /tmp + .venv/bin/python convert_hf_to_gguf_update.py --check-missing + + - name: Check if committed pre-tokenizer hashes matches generated version + run: | + if ! diff -q convert_hf_to_gguf.py /tmp/convert_hf_to_gguf.py; then + echo "Model pre-tokenizer hashes (in convert_hf_to_gguf.py) do not match generated hashes (from convert_hf_to_gguf_update.py)." + echo "To fix: run ./convert_hf_to_gguf_update.py and commit the updated convert_hf_to_gguf.py along with your changes" + echo "Differences found:" + diff convert_hf_to_gguf.py /tmp/convert_hf_to_gguf.py || true + exit 1 + fi + echo "Model pre-tokenizer hashes are up to date." diff --git a/.gitignore b/.gitignore index f8ceb1560a..f48ce4cacd 100644 --- a/.gitignore +++ b/.gitignore @@ -82,6 +82,7 @@ models/* models-mnt !models/.editorconfig !models/ggml-vocab-*.gguf* +!models/templates # Zig zig-out/ diff --git a/CMakeLists.txt b/CMakeLists.txt index c79ccd09e0..36a2078e4c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -12,6 +12,8 @@ if (NOT XCODE AND NOT MSVC AND NOT CMAKE_BUILD_TYPE) set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS "Debug" "Release" "MinSizeRel" "RelWithDebInfo") endif() +message("CMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}") + # Add path to modules list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake/") diff --git a/README.md b/README.md index 6768d5a3d7..11d9290786 100644 --- a/README.md +++ b/README.md @@ -17,6 +17,8 @@ LLM inference in C/C++ ## Hot topics +- **[[FEEDBACK] Better packaging for llama.cpp to support downstream consumers 🤗](https://github.com/ggml-org/llama.cpp/discussions/15313)** +- Support for the `gpt-oss` model with native MXFP4 format has been added | [PR](https://github.com/ggml-org/llama.cpp/pull/15091) | [Collaboration with NVIDIA](https://blogs.nvidia.com/blog/rtx-ai-garage-openai-oss) | [Comment](https://github.com/ggml-org/llama.cpp/discussions/15095) - Hot PRs: [All](https://github.com/ggml-org/llama.cpp/pulls?q=is%3Apr+label%3Ahot+) | [Open](https://github.com/ggml-org/llama.cpp/pulls?q=is%3Apr+label%3Ahot+is%3Aopen) - Multimodal support arrived in `llama-server`: [#12898](https://github.com/ggml-org/llama.cpp/pull/12898) | [documentation](./docs/multimodal.md) - VS Code extension for FIM completions: https://github.com/ggml-org/llama.vscode @@ -239,7 +241,7 @@ Instructions for adding support for new models: [HOWTO-add-model.md](docs/develo
Infrastructure -- [Paddler](https://github.com/distantmagic/paddler) - Stateful load balancer custom-tailored for llama.cpp +- [Paddler](https://github.com/intentee/paddler) - Open-source LLMOps platform for hosting and scaling AI in your own infrastructure - [GPUStack](https://github.com/gpustack/gpustack) - Manage GPU clusters for running LLMs - [llama_cpp_canister](https://github.com/onicai/llama_cpp_canister) - llama.cpp as a smart contract on the Internet Computer, using WebAssembly - [llama-swap](https://github.com/mostlygeek/llama-swap) - transparent proxy that adds automatic model switching with llama-server @@ -270,7 +272,6 @@ Instructions for adding support for new models: [HOWTO-add-model.md](docs/develo | [CANN](docs/build.md#cann) | Ascend NPU | | [OpenCL](docs/backend/OPENCL.md) | Adreno GPU | | [WebGPU [In Progress]](docs/build.md#webgpu) | All | - | [RPC](https://github.com/ggml-org/llama.cpp/tree/master/tools/rpc) | All | ## Obtaining and quantizing models diff --git a/ci/README.md b/ci/README.md index 6e297f1a82..8eebe988d5 100644 --- a/ci/README.md +++ b/ci/README.md @@ -54,7 +54,7 @@ docker run --privileged -it \ -v $HOME/llama.cpp/ci-cache:/ci-cache \ -v $HOME/llama.cpp/ci-results:/ci-results \ -v $PWD:/ws -w /ws \ - mthreads/musa:rc4.0.1-mudnn-devel-ubuntu22.04 + mthreads/musa:rc4.2.0-devel-ubuntu22.04-amd64 ``` Inside the container, execute the following commands: diff --git a/common/arg.cpp b/common/arg.cpp index c1151f51da..98baac4c14 100644 --- a/common/arg.cpp +++ b/common/arg.cpp @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -748,6 +749,39 @@ std::pair> common_remote_get_content(const std::string & // utils // +// Helper function to parse tensor buffer override strings +static void parse_tensor_buffer_overrides(const std::string & value, std::vector & overrides) { + std::map buft_list; + for (size_t i = 0; i < ggml_backend_dev_count(); ++i) { + auto * dev = ggml_backend_dev_get(i); + auto * buft = ggml_backend_dev_buffer_type(dev); + if (buft) { + buft_list[ggml_backend_buft_name(buft)] = buft; + } + } + + for (const auto & override : string_split(value, ',')) { + std::string::size_type pos = override.find('='); + if (pos == std::string::npos) { + throw std::invalid_argument("invalid value"); + } + std::string tensor_name = override.substr(0, pos); + std::string buffer_type = override.substr(pos + 1); + + if (buft_list.find(buffer_type) == buft_list.end()) { + printf("Available buffer types:\n"); + for (const auto & it : buft_list) { + printf(" %s\n", ggml_backend_buft_name(it.second)); + } + throw std::invalid_argument("unknown buffer type"); + } + // keep strings alive and avoid leaking memory by storing them in a static vector + static std::list buft_overrides; + buft_overrides.push_back(tensor_name); + overrides.push_back({buft_overrides.back().c_str(), buft_list.at(buffer_type)}); + } +} + struct handle_model_result { bool found_mmproj = false; common_params_model mmproj; @@ -977,6 +1011,10 @@ static bool common_params_parse_ex(int argc, char ** argv, common_params_context for (auto & seq_breaker : params.sampling.dry_sequence_breakers) { string_process_escapes(seq_breaker); } + for (auto & pair : params.speculative.replacements) { + string_process_escapes(pair.first); + string_process_escapes(pair.second); + } } if (!params.kv_overrides.empty()) { @@ -988,6 +1026,10 @@ static bool common_params_parse_ex(int argc, char ** argv, common_params_context params.tensor_buft_overrides.push_back({nullptr, nullptr}); } + if (!params.speculative.tensor_buft_overrides.empty()) { + params.speculative.tensor_buft_overrides.push_back({nullptr, nullptr}); + } + if (!params.chat_template.empty() && !common_chat_verify_template(params.chat_template, params.use_jinja)) { throw std::runtime_error(string_format( "error: the supplied chat template is not supported: %s%s\n", @@ -1196,6 +1238,7 @@ bool common_params_parse(int argc, char ** argv, common_params & params, llama_e common_params_print_completion(ctx_arg); exit(0); } + params.lr.init(); } catch (const std::invalid_argument & ex) { fprintf(stderr, "%s\n", ex.what()); ctx_arg.params = params_org; @@ -1464,6 +1507,14 @@ common_params_context common_params_parser_init(common_params & params, llama_ex params.swa_full = true; } ).set_env("LLAMA_ARG_SWA_FULL")); + add_opt(common_arg( + {"--swa-checkpoints"}, "N", + string_format("max number of SWA checkpoints per slot to create (default: %d)\n" + "[(more info)](https://github.com/ggml-org/llama.cpp/pull/15293)", params.n_swa_checkpoints), + [](common_params & params, int value) { + params.n_swa_checkpoints = value; + } + ).set_env("LLAMA_ARG_SWA_CHECKPOINTS").set_examples({LLAMA_EXAMPLE_SERVER})); add_opt(common_arg( {"--kv-unified", "-kvu"}, string_format("use single unified KV buffer for the KV cache of all sequences (default: %s)\n" @@ -1612,7 +1663,7 @@ common_params_context common_params_parser_init(common_params & params, llama_ex [](common_params & params, const std::string & value) { params.antiprompt.emplace_back(value); } - ).set_examples({LLAMA_EXAMPLE_MAIN})); + ).set_examples({LLAMA_EXAMPLE_MAIN, LLAMA_EXAMPLE_SERVER})); add_opt(common_arg( {"-sp", "--special"}, string_format("special tokens output enabled (default: %s)", params.special ? "true" : "false"), @@ -2091,6 +2142,13 @@ common_params_context common_params_parser_init(common_params & params, llama_ex params.no_kv_offload = true; } ).set_env("LLAMA_ARG_NO_KV_OFFLOAD")); + add_opt(common_arg( + {"-nr", "--no-repack"}, + "disable weight repacking", + [](common_params & params) { + params.no_extra_bufts = true; + } + ).set_env("LLAMA_ARG_NO_REPACK")); add_opt(common_arg( {"-ctk", "--cache-type-k"}, "TYPE", string_format( @@ -2337,38 +2395,58 @@ common_params_context common_params_parser_init(common_params & params, llama_ex add_opt(common_arg( {"--override-tensor", "-ot"}, "=,...", "override tensor buffer type", [](common_params & params, const std::string & value) { - /* static */ std::map buft_list; - if (buft_list.empty()) { - // enumerate all the devices and add their buffer types to the list - for (size_t i = 0; i < ggml_backend_dev_count(); ++i) { - auto * dev = ggml_backend_dev_get(i); - auto * buft = ggml_backend_dev_buffer_type(dev); - if (buft) { - buft_list[ggml_backend_buft_name(buft)] = buft; - } - } - } - - for (const auto & override : string_split(value, ',')) { - std::string::size_type pos = override.find('='); - if (pos == std::string::npos) { - throw std::invalid_argument("invalid value"); - } - std::string tensor_name = override.substr(0, pos); - std::string buffer_type = override.substr(pos + 1); - - if (buft_list.find(buffer_type) == buft_list.end()) { - printf("Available buffer types:\n"); - for (const auto & it : buft_list) { - printf(" %s\n", ggml_backend_buft_name(it.second)); - } - throw std::invalid_argument("unknown buffer type"); - } - // FIXME: this leaks memory - params.tensor_buft_overrides.push_back({strdup(tensor_name.c_str()), buft_list.at(buffer_type)}); - } + parse_tensor_buffer_overrides(value, params.tensor_buft_overrides); } )); + add_opt(common_arg( + {"--override-tensor-draft", "-otd"}, "=,...", + "override tensor buffer type for draft model", [](common_params & params, const std::string & value) { + parse_tensor_buffer_overrides(value, params.speculative.tensor_buft_overrides); + } + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER})); + add_opt(common_arg( + {"--cpu-moe", "-cmoe"}, + "keep all Mixture of Experts (MoE) weights in the CPU", + [](common_params & params) { + params.tensor_buft_overrides.push_back({"\\.ffn_(up|down|gate)_exps", ggml_backend_cpu_buffer_type()}); + } + ).set_env("LLAMA_ARG_CPU_MOE")); + add_opt(common_arg( + {"--n-cpu-moe", "-ncmoe"}, "N", + "keep the Mixture of Experts (MoE) weights of the first N layers in the CPU", + [](common_params & params, int value) { + if (value < 0) { + throw std::invalid_argument("invalid value"); + } + for (int i = 0; i < value; ++i) { + // keep strings alive and avoid leaking memory by storing them in a static vector + static std::list buft_overrides; + buft_overrides.push_back(string_format("blk\\.%d\\.ffn_(up|down|gate)_exps", i)); + params.tensor_buft_overrides.push_back({buft_overrides.back().c_str(), ggml_backend_cpu_buffer_type()}); + } + } + ).set_env("LLAMA_ARG_N_CPU_MOE")); + add_opt(common_arg( + {"--cpu-moe-draft", "-cmoed"}, + "keep all Mixture of Experts (MoE) weights in the CPU for the draft model", + [](common_params & params) { + params.speculative.tensor_buft_overrides.push_back({"\\.ffn_(up|down|gate)_exps", ggml_backend_cpu_buffer_type()}); + } + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_CPU_MOE_DRAFT")); + add_opt(common_arg( + {"--n-cpu-moe-draft", "-ncmoed"}, "N", + "keep the Mixture of Experts (MoE) weights of the first N layers in the CPU for the draft model", + [](common_params & params, int value) { + if (value < 0) { + throw std::invalid_argument("invalid value"); + } + for (int i = 0; i < value; ++i) { + static std::list buft_overrides_draft; + buft_overrides_draft.push_back(string_format("blk\\.%d\\.ffn_(up|down|gate)_exps", i)); + params.speculative.tensor_buft_overrides.push_back({buft_overrides_draft.back().c_str(), ggml_backend_cpu_buffer_type()}); + } + } + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_N_CPU_MOE_DRAFT")); add_opt(common_arg( {"-ngl", "--gpu-layers", "--n-gpu-layers"}, "N", "number of layers to store in VRAM", @@ -2619,7 +2697,7 @@ common_params_context common_params_parser_init(common_params & params, llama_ex [](common_params & params, const std::string & value) { params.out_file = value; } - ).set_examples({LLAMA_EXAMPLE_IMATRIX, LLAMA_EXAMPLE_CVECTOR_GENERATOR, LLAMA_EXAMPLE_EXPORT_LORA, LLAMA_EXAMPLE_TTS})); + ).set_examples({LLAMA_EXAMPLE_IMATRIX, LLAMA_EXAMPLE_CVECTOR_GENERATOR, LLAMA_EXAMPLE_EXPORT_LORA, LLAMA_EXAMPLE_TTS, LLAMA_EXAMPLE_FINETUNE})); add_opt(common_arg( {"-ofreq", "--output-frequency"}, "N", string_format("output the imatrix every N iterations (default: %d)", params.n_out_freq), @@ -2627,6 +2705,15 @@ common_params_context common_params_parser_init(common_params & params, llama_ex params.n_out_freq = value; } ).set_examples({LLAMA_EXAMPLE_IMATRIX})); + add_opt(common_arg( + {"--output-format"}, "{gguf,dat}", + string_format("output format for imatrix file (default: %s)", params.imat_dat > 0 ? "dat" : "gguf"), + [](common_params & params, const std::string & value) { + /**/ if (value == "gguf") { params.imat_dat = -1; } + else if (value == "dat") { params.imat_dat = 1; } + else { throw std::invalid_argument("invalid output format"); } + } + ).set_examples({LLAMA_EXAMPLE_IMATRIX})); add_opt(common_arg( {"--save-frequency"}, "N", string_format("save an imatrix copy every N iterations (default: %d)", params.n_save_freq), @@ -2655,6 +2742,13 @@ common_params_context common_params_parser_init(common_params & params, llama_ex params.i_chunk = value; } ).set_examples({LLAMA_EXAMPLE_IMATRIX})); + add_opt(common_arg( + {"--show-statistics"}, + string_format("show imatrix statistics and then exit (default: %s)", params.show_statistics ? "true" : "false"), + [](common_params & params) { + params.show_statistics = true; + } + ).set_examples({LLAMA_EXAMPLE_IMATRIX})); add_opt(common_arg( {"--parse-special"}, string_format("prase special tokens (chat, tool, etc) (default: %s)", params.parse_special ? "true" : "false"), @@ -2895,12 +2989,9 @@ common_params_context common_params_parser_init(common_params & params, llama_ex "controls whether thought tags are allowed and/or extracted from the response, and in which format they're returned; one of:\n" "- none: leaves thoughts unparsed in `message.content`\n" "- deepseek: puts thoughts in `message.reasoning_content` (except in streaming mode, which behaves as `none`)\n" - "(default: deepseek)", + "(default: auto)", [](common_params & params, const std::string & value) { - /**/ if (value == "deepseek") { params.reasoning_format = COMMON_REASONING_FORMAT_DEEPSEEK; } - else if (value == "deepseek-legacy") { params.reasoning_format = COMMON_REASONING_FORMAT_DEEPSEEK_LEGACY; } - else if (value == "none") { params.reasoning_format = COMMON_REASONING_FORMAT_NONE; } - else { throw std::invalid_argument("invalid value"); } + params.reasoning_format = common_reasoning_format_from_name(value); } ).set_examples({LLAMA_EXAMPLE_SERVER, LLAMA_EXAMPLE_MAIN}).set_env("LLAMA_ARG_THINK")); add_opt(common_arg( @@ -3081,7 +3172,7 @@ common_params_context common_params_parser_init(common_params & params, llama_ex params.speculative.cpuparams.n_threads = std::thread::hardware_concurrency(); } } - ).set_examples({LLAMA_EXAMPLE_SPECULATIVE})); + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER})); add_opt(common_arg( {"-tbd", "--threads-batch-draft"}, "N", "number of threads to use during batch and prompt processing (default: same as --threads-draft)", @@ -3091,7 +3182,7 @@ common_params_context common_params_parser_init(common_params & params, llama_ex params.speculative.cpuparams_batch.n_threads = std::thread::hardware_concurrency(); } } - ).set_examples({LLAMA_EXAMPLE_SPECULATIVE})); + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER})); add_opt(common_arg( {"-Cd", "--cpu-mask-draft"}, "M", "Draft model CPU affinity mask. Complements cpu-range-draft (default: same as --cpu-mask)", @@ -3242,6 +3333,13 @@ common_params_context common_params_parser_init(common_params & params, llama_ex params.speculative.model.path = value; } ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_MODEL_DRAFT")); + add_opt(common_arg( + {"--spec-replace"}, "TARGET", "DRAFT", + "translate the string in TARGET into DRAFT if the draft model and main model are not compatible", + [](common_params & params, const std::string & tgt, const std::string & dft) { + params.speculative.replacements.push_back({ tgt, dft }); + } + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER})); add_opt(common_arg( {"-ctkd", "--cache-type-k-draft"}, "TYPE", string_format( @@ -3431,28 +3529,11 @@ common_params_context common_params_parser_init(common_params & params, llama_ex } ).set_examples({LLAMA_EXAMPLE_SERVER})); - // diffusion parameters add_opt(common_arg( { "--diffusion-steps" }, "N", string_format("number of diffusion steps (default: %d)", params.diffusion.steps), [](common_params & params, int value) { params.diffusion.steps = value; } ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); - add_opt(common_arg( - { "--diffusion-eps" }, "F", - string_format("epsilon for timesteps (default: %.6f)", (double) params.diffusion.eps), - [](common_params & params, const std::string & value) { params.diffusion.eps = std::stof(value); } - ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); - add_opt(common_arg( - { "--diffusion-algorithm" }, "N", - string_format("diffusion algorithm: 0=ORIGIN, 1=MASKGIT_PLUS, 2=TOPK_MARGIN, 3=ENTROPY (default: %d)", - params.diffusion.algorithm), - [](common_params & params, int value) { params.diffusion.algorithm = value; } - ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); - add_opt(common_arg( - { "--diffusion-alg-temp" }, "F", - string_format("algorithm temperature (default: %.3f)", (double) params.diffusion.alg_temp), - [](common_params & params, const std::string & value) { params.diffusion.alg_temp = std::stof(value); } - ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); add_opt(common_arg( { "--diffusion-visual" }, string_format("enable visual diffusion mode (show progressive generation) (default: %s)", @@ -3460,5 +3541,85 @@ common_params_context common_params_parser_init(common_params & params, llama_ex [](common_params & params) { params.diffusion.visual_mode = true; } ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + add_opt(common_arg( + { "--diffusion-eps" }, "F", + string_format("epsilon for timesteps (default: %.6f)", (double) params.diffusion.eps), + [](common_params & params, const std::string & value) { params.diffusion.eps = std::stof(value); } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + add_opt(common_arg( + { "--diffusion-algorithm" }, "N", + string_format("diffusion algorithm: 0=ORIGIN, 1=ENTROPY_BASED, 2=MARGIN_BASED, 3=RANDOM, 4=LOW_CONFIDENCE (default: %d)", + params.diffusion.algorithm), + [](common_params & params, int value) { params.diffusion.algorithm = value; } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + add_opt(common_arg( + { "--diffusion-alg-temp" }, "F", + string_format("dream algorithm temperature (default: %.3f)", (double) params.diffusion.alg_temp), + [](common_params & params, const std::string & value) { params.diffusion.alg_temp = std::stof(value); } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + + add_opt(common_arg( + { "--diffusion-block-length" }, "N", + string_format("llada block length for generation (default: %d)", params.diffusion.block_length), + [](common_params & params, int value) { params.diffusion.block_length = value; } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + add_opt(common_arg( + { "--diffusion-cfg-scale" }, "F", + string_format("llada classifier-free guidance scale (default: %.3f)", (double) params.diffusion.cfg_scale), + [](common_params & params, const std::string & value) { params.diffusion.cfg_scale = std::stof(value); } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + add_opt(common_arg( + { "--diffusion-add-gumbel-noise" }, "F", + string_format("add gumbel noise to the logits if temp > 0.0 (default: %s)", params.diffusion.add_gumbel_noise ? "true" : "false"), + [](common_params & params, const std::string & value) { params.diffusion.add_gumbel_noise = std::stof(value); } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + + + add_opt( + common_arg({ "-lr", "--learning-rate" }, "ALPHA", + string_format( + "adamw or sgd optimizer alpha (default: %.2g); note: sgd alpha recommended ~10x (no momentum)", + (double) params.lr.lr0), + [](common_params & params, const std::string & value) { params.lr.lr0 = std::stof(value); }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt( + common_arg({ "-lr-min", "--learning-rate-min" }, "ALPHA", + string_format( + "(if >0) final learning rate after decay (if -decay-epochs is set, default=%.2g)", + (double) params.lr.lr_min), + [](common_params & params, const std::string & value) { params.lr.lr_min = std::stof(value); }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt( + common_arg({ "-decay-epochs", "--learning-rate-decay-epochs" }, "ALPHA", + string_format( + "(if >0) decay learning rate to -lr-min after this many epochs (exponential decay, default=%.2g)", + (double) params.lr.decay_epochs), + [](common_params & params, const std::string & value) { params.lr.decay_epochs = std::stof(value); }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt(common_arg( + { "-wd", "--weight-decay" }, "WD", + string_format( + "adamw or sgd optimizer weight decay (0 is off; recommend very small e.g. 1e-9) (default: %.2g).", + (double) params.lr.wd), + [](common_params & params, const std::string & value) { params.lr.wd = std::stof(value); }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt(common_arg({ "-val-split", "--val-split" }, "FRACTION", + string_format("fraction of data to use as validation set for training (default: %.2g).", + (double) params.val_split), + [](common_params & params, const std::string & value) { params.val_split = std::stof(value); }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt(common_arg({ "-epochs", "--epochs" }, "N", + string_format("optimizer max # of epochs (default: %d)", params.lr.epochs), + [](common_params & params, int epochs) { params.lr.epochs = epochs; }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt(common_arg({ "-opt", "--optimizer" }, "sgd|adamw", "adamw or sgd", + [](common_params & params, const std::string & name) { + params.optimizer = common_opt_get_optimizer(name.c_str()); + if (params.optimizer == GGML_OPT_OPTIMIZER_TYPE_COUNT) { + throw std::invalid_argument("invalid --optimizer, valid options: adamw, sgd"); + } + }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + return ctx_arg; } diff --git a/common/chat-parser.cpp b/common/chat-parser.cpp index 18a30e49aa..96ba8f533e 100644 --- a/common/chat-parser.cpp +++ b/common/chat-parser.cpp @@ -55,7 +55,15 @@ bool common_chat_msg_parser::add_tool_call(const std::string & name, const std:: bool common_chat_msg_parser::add_tool_call(const json & tool_call) { std::string name = tool_call.contains("name") ? tool_call.at("name") : ""; std::string id = tool_call.contains("id") ? tool_call.at("id") : ""; - std::string arguments = tool_call.contains("arguments") ? tool_call.at("arguments") : ""; + std::string arguments = ""; + if (tool_call.contains("arguments")) { + if (tool_call.at("arguments").is_object()) { + arguments = tool_call.at("arguments").dump(); + } else { + arguments = tool_call.at("arguments"); + } + } + return add_tool_call(name, id, arguments); } diff --git a/common/chat.cpp b/common/chat.cpp index 114dbfccdb..00f30994b5 100644 --- a/common/chat.cpp +++ b/common/chat.cpp @@ -126,6 +126,8 @@ std::vector common_chat_msg_diff::compute_diffs(const comm typedef minja::chat_template common_chat_template; struct common_chat_templates { + bool add_bos; + bool add_eos; bool has_explicit_template; // Model had builtin template or template overridde was specified. std::unique_ptr template_default; // always set (defaults to chatml) std::unique_ptr template_tool_use; @@ -143,6 +145,8 @@ struct templates_params { bool enable_thinking = true; std::chrono::system_clock::time_point now = std::chrono::system_clock::now(); json extra_context; + bool add_bos; + bool add_eos; }; common_chat_tool_choice common_chat_tool_choice_parse_oaicompat(const std::string & tool_choice) { @@ -292,6 +296,7 @@ json common_chat_msgs_to_json_oaicompat(const std::vector & msg } if (!msg.reasoning_content.empty()) { jmsg["reasoning_content"] = msg.reasoning_content; + jmsg["thinking"] = msg.reasoning_content; // gpt-oss } if (!msg.tool_name.empty()) { jmsg["name"] = msg.tool_name; @@ -445,6 +450,8 @@ std::string common_chat_format_single( common_chat_templates_inputs inputs; inputs.use_jinja = use_jinja; + inputs.add_bos = tmpls->add_bos; + inputs.add_eos = tmpls->add_eos; std::string fmt_past_msg; if (!past_msg.empty()) { @@ -466,9 +473,12 @@ std::string common_chat_format_single( return ss.str(); } -std::string common_chat_format_example(const struct common_chat_templates * tmpls, bool use_jinja) { +std::string common_chat_format_example(const struct common_chat_templates * tmpls, bool use_jinja, const std::map & chat_template_kwargs) { common_chat_templates_inputs inputs; inputs.use_jinja = use_jinja; + inputs.add_bos = tmpls->add_bos; + inputs.add_eos = tmpls->add_eos; + inputs.chat_template_kwargs = chat_template_kwargs; auto add_simple_msg = [&](auto role, auto content) { common_chat_msg msg; msg.role = role; @@ -544,8 +554,21 @@ common_chat_templates_ptr common_chat_templates_init( default_template_src = CHATML_TEMPLATE_SRC; } } + + // TODO @ngxson : this is a temporary hack to prevent chat template from throwing an error + // Ref: https://github.com/ggml-org/llama.cpp/pull/15230#issuecomment-3173959633 + if (default_template_src.find("<|channel|>") != std::string::npos + // search for the error message and patch it + && default_template_src.find("in message.content or") != std::string::npos) { + string_replace_all(default_template_src, + "{%- if \"<|channel|>analysis<|message|>\" in message.content or \"<|channel|>final<|message|>\" in message.content %}", + "{%- if false %}"); + } + std::string token_bos = bos_token_override; std::string token_eos = eos_token_override; + bool add_bos = false; + bool add_eos = false; if (model) { const auto * vocab = llama_model_get_vocab(model); const auto get_token = [&](llama_token token, const char * name, const char * jinja_variable_name) { @@ -560,9 +583,13 @@ common_chat_templates_ptr common_chat_templates_init( }; token_bos = get_token(llama_vocab_bos(vocab), "BOS", "bos_token"); token_eos = get_token(llama_vocab_eos(vocab), "EOS", "eos_token"); + add_bos = llama_vocab_get_add_bos(vocab); + add_eos = llama_vocab_get_add_eos(vocab); } common_chat_templates_ptr tmpls(new common_chat_templates()); tmpls->has_explicit_template = has_explicit_template; + tmpls->add_bos = add_bos; + tmpls->add_eos = add_eos; try { tmpls->template_default = std::make_unique(default_template_src, token_bos, token_eos); } catch (const std::exception & e) { @@ -592,6 +619,8 @@ const char * common_chat_format_name(common_chat_format format) { case COMMON_CHAT_FORMAT_FUNCTIONARY_V3_1_LLAMA_3_1: return "Functionary v3.1 Llama 3.1"; case COMMON_CHAT_FORMAT_HERMES_2_PRO: return "Hermes 2 Pro"; case COMMON_CHAT_FORMAT_COMMAND_R7B: return "Command R7B"; + case COMMON_CHAT_FORMAT_GRANITE: return "Granite"; + case COMMON_CHAT_FORMAT_GPT_OSS: return "GPT-OSS"; default: throw std::runtime_error("Unknown chat format"); } @@ -600,13 +629,28 @@ const char * common_chat_format_name(common_chat_format format) { const char * common_reasoning_format_name(common_reasoning_format format) { switch (format) { case COMMON_REASONING_FORMAT_NONE: return "none"; + case COMMON_REASONING_FORMAT_AUTO: return "auto"; case COMMON_REASONING_FORMAT_DEEPSEEK: return "deepseek"; case COMMON_REASONING_FORMAT_DEEPSEEK_LEGACY: return "deepseek-legacy"; + case COMMON_REASONING_FORMAT_GRANITE: return "granite"; default: throw std::runtime_error("Unknown reasoning format"); } } +common_reasoning_format common_reasoning_format_from_name(const std::string & format) { + if (format == "none") { + return COMMON_REASONING_FORMAT_NONE; + } else if (format == "auto") { + return COMMON_REASONING_FORMAT_AUTO; + } else if (format == "deepseek") { + return COMMON_REASONING_FORMAT_DEEPSEEK; + } else if (format == "deepseek-legacy") { + return COMMON_REASONING_FORMAT_DEEPSEEK_LEGACY; + } + throw std::runtime_error("Unknown reasoning format: " + format); +} + static std::string wrap_code_as_arguments(common_chat_msg_parser & builder, const std::string & code) { std::string arguments; if (builder.is_partial()) { @@ -748,10 +792,10 @@ static std::string apply( // instead of using `chat_template_options.use_bos_token = false`, since these tokens // may be needed inside the template / between messages too. auto result = tmpl.apply(tmpl_inputs, tmpl_opts); - if (string_starts_with(result, tmpl.bos_token())) { + if (inputs.add_bos && string_starts_with(result, tmpl.bos_token())) { result = result.substr(tmpl.bos_token().size()); } - if (string_ends_with(result, tmpl.eos_token())) { + if (inputs.add_eos && string_ends_with(result, tmpl.eos_token())) { result = result.substr(0, result.size() - tmpl.eos_token().size()); } return result; @@ -1289,6 +1333,174 @@ static void common_chat_parse_deepseek_r1(common_chat_msg_parser & builder) { tool_calls_end); } +static common_chat_params common_chat_params_init_gpt_oss(const common_chat_template & tmpl, const struct templates_params & inputs) { + common_chat_params data; + auto prompt = apply(tmpl, inputs); + + data.prompt = prompt; + data.format = COMMON_CHAT_FORMAT_GPT_OSS; + + // These special tokens are required to parse properly, so we include them + // even if parse_tool_calls is false. + data.preserved_tokens = { + "<|channel|>", + "<|constrain|>", + "<|message|>", + "<|start|>", + "<|end|>", + }; + + if (inputs.tools.is_array() && !inputs.tools.empty()) { + data.grammar_lazy = inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_REQUIRED; + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + // tool calls can appear in commentary or analysis channels + auto channel = builder.add_rule("channel", "\"<|channel|>\" ( \"commentary\" | \"analysis\" )"); + + std::vector tool_rules_recipient_in_role; + std::vector tool_rules_recipient_in_channel; + foreach_function(inputs.tools, [&](const json & tool) { + const auto & function = tool.at("function"); + std::string name = function.at("name"); + auto parameters = function.at("parameters"); + builder.resolve_refs(parameters); + + tool_rules_recipient_in_role.push_back( + builder.add_rule(name + "-call", + "\"" + name + "\"" + channel + " \" <|constrain|>json\"? \"<|message|>\" " + + builder.add_schema(name + "-args", parameters) + ) + ); + + tool_rules_recipient_in_channel.push_back( + builder.add_rule(name + "-call", + "\"" + name + "\"" + " \" <|constrain|>json\"? \"<|message|>\" " + + builder.add_schema(name + "-args", parameters) + ) + ); + }); + + auto recipient_in_role = builder.add_rule("recipient_in_role", + "\"<|start|>assistant\"? \" to=functions.\" ( " + + string_join(tool_rules_recipient_in_role, " | ") + " )" + ); + + auto recipient_in_channel = builder.add_rule("recipient_in_channel", + channel + " \" to=functions.\" ( " + + string_join(tool_rules_recipient_in_channel, " | ") + " )" + ); + + builder.add_rule("root", recipient_in_role + " | " + recipient_in_channel); + + // Trigger on tool calls that appear in the commentary channel + data.grammar_triggers.push_back({ + COMMON_GRAMMAR_TRIGGER_TYPE_PATTERN, + "<\\|channel\\|>(commentary|analysis) to" + }); + + // Trigger tool calls that appear in the role section, either at the + // start or in the middle. + data.grammar_triggers.push_back({ + COMMON_GRAMMAR_TRIGGER_TYPE_PATTERN_FULL, + "^ to" + }); + + data.grammar_triggers.push_back({ + COMMON_GRAMMAR_TRIGGER_TYPE_PATTERN, + "<\\|start\\|>assistant to" + }); + }); + } + + return data; +} +static void common_chat_parse_gpt_oss(common_chat_msg_parser & builder) { + static const std::string constraint = "(?: (<\\|constrain\\|>)?([a-zA-Z0-9_-]+))"; + static const std::string recipient("(?: to=functions\\.([^<\\s]+))"); + + static const common_regex start_regex("<\\|start\\|>assistant"); + static const common_regex analysis_regex("<\\|channel\\|>analysis"); + static const common_regex final_regex("<\\|channel\\|>final" + constraint + "?"); + static const common_regex preamble_regex("<\\|channel\\|>commentary"); + static const common_regex tool_call1_regex(recipient + "<\\|channel\\|>(analysis|commentary)" + constraint + "?"); + static const common_regex tool_call2_regex("<\\|channel\\|>(analysis|commentary)" + recipient + constraint + "?"); + + auto consume_end = [&](bool include_end = false) { + if (auto res = builder.try_find_literal("<|end|>")) { + return res->prelude + (include_end ? builder.str(res->groups[0]) : ""); + } + return builder.consume_rest(); + }; + + auto handle_tool_call = [&](const std::string & name) { + if (auto args = builder.try_consume_json_with_dumped_args({{}})) { + if (builder.syntax().parse_tool_calls) { + if (!builder.add_tool_call(name, "", args->value) || args->is_partial) { + throw common_chat_msg_partial_exception("incomplete tool call"); + } + } else if (args->is_partial) { + throw common_chat_msg_partial_exception("incomplete tool call"); + } + } + }; + + auto regex_match = [](const common_regex & regex, const std::string & input) -> std::optional { + auto match = regex.search(input, 0, true); + if (match.type == COMMON_REGEX_MATCH_TYPE_FULL) { + return match; + } + return std::nullopt; + }; + + do { + auto header_start_pos = builder.pos(); + auto content_start = builder.try_find_literal("<|message|>"); + if (!content_start) { + throw common_chat_msg_partial_exception("incomplete header"); + } + + auto header = content_start->prelude; + + if (auto match = regex_match(tool_call1_regex, header)) { + auto group = match->groups[1]; + auto name = header.substr(group.begin, group.end - group.begin); + handle_tool_call(name); + continue; + } + + if (auto match = regex_match(tool_call2_regex, header)) { + auto group = match->groups[2]; + auto name = header.substr(group.begin, group.end - group.begin); + handle_tool_call(name); + continue; + } + + if (regex_match(analysis_regex, header)) { + builder.move_to(header_start_pos); + if (builder.syntax().reasoning_format == COMMON_REASONING_FORMAT_NONE || builder.syntax().reasoning_in_content) { + builder.add_content(consume_end(true)); + } else { + builder.try_parse_reasoning("<|channel|>analysis<|message|>", "<|end|>"); + } + continue; + } + + if(regex_match(final_regex, header) || regex_match(preamble_regex, header)) { + builder.add_content(consume_end()); + continue; + } + + // Possibly a malformed message, attempt to recover by rolling + // back to pick up the next <|start|> + LOG_DBG("%s: unknown header from message: %s\n", __func__, header.c_str()); + builder.move_to(header_start_pos); + } while (builder.try_find_regex(start_regex, std::string::npos, false)); + + auto remaining = builder.consume_rest(); + if (!remaining.empty()) { + LOG_DBG("%s: content after last message: %s\n", __func__, remaining.c_str()); + } +} + static common_chat_params common_chat_params_init_firefunction_v2(const common_chat_template & tmpl, const struct templates_params & inputs) { LOG_DBG("%s\n", __func__); common_chat_params data; @@ -1646,7 +1858,7 @@ static void common_chat_parse_hermes_2_pro(common_chat_msg_parser & builder) { "|" // match 5 (function name again) ); - if (auto res = builder.try_find_regex(open_regex)) { + while (auto res = builder.try_find_regex(open_regex)) { const auto & block_start = res->groups[1]; std::string block_end = block_start.empty() ? "" : "```"; @@ -1668,7 +1880,6 @@ static void common_chat_parse_hermes_2_pro(common_chat_msg_parser & builder) { builder.consume_literal(block_end); builder.consume_spaces(); } - builder.add_content(builder.consume_rest()); } else { throw common_chat_msg_partial_exception("failed to parse tool call"); } @@ -1693,7 +1904,124 @@ static void common_chat_parse_hermes_2_pro(common_chat_msg_parser & builder) { builder.consume_spaces(); } } - builder.add_content(builder.consume_rest()); + } + } + + builder.add_content(builder.consume_rest()); +} + +static common_chat_params common_chat_params_init_granite(const common_chat_template & tmpl, const struct templates_params & inputs) { + common_chat_params data; + + // Pass thinking context for Granite template + json additional_context = { + {"thinking", inputs.enable_thinking}, + }; + + data.prompt = apply(tmpl, inputs, /* messages_override= */ std::nullopt, /* tools_override= */ std::nullopt, additional_context); + data.format = COMMON_CHAT_FORMAT_GRANITE; + + if (string_ends_with(data.prompt, "\n") || string_ends_with(data.prompt, "")) { + if (!inputs.enable_thinking) { + data.prompt += ""; + } else { + data.thinking_forced_open = true; + } + } + + if (!inputs.tools.is_null()) { + // Granite uses <|tool_call|> followed by JSON list + data.grammar_lazy = inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_REQUIRED; + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + std::vector tool_rules; + foreach_function(inputs.tools, [&](const json & tool) { + const auto & function = tool.at("function"); + std::string name = function.at("name"); + auto parameters = function.at("parameters"); + builder.resolve_refs(parameters); + tool_rules.push_back(builder.add_rule(name + "-call", builder.add_schema(name + +"-args", { + {"type", "object"}, + {"properties", { + {"name", {{"const", name}}}, + {"arguments", parameters}, + }}, + {"required", json::array({"name", "arguments"})}, + }))); + }); + + auto tool_call = builder.add_rule("tool_call", string_join(tool_rules, " | ")); + auto tool_list = builder.add_rule("tool_list", "\"[\" space " + tool_call + " (\",\" space " + tool_call + ")* space \"]\""); + + if (data.thinking_forced_open) { + builder.add_rule("root", "\"\" space \"\" space [^<]* \"\" space \"<|tool_call|>\" space " + tool_list); + } else { + builder.add_rule("root", "\"<|tool_call|>\" space " + tool_list); + } + + data.grammar_triggers.push_back({ + COMMON_GRAMMAR_TRIGGER_TYPE_WORD, + "<|tool_call|>" + }); + + data.preserved_tokens = { + "", + "", + "", + "", + "<|tool_call|>", + }; + }); + } else { + // Handle thinking tags for non-tool responses + if (data.thinking_forced_open && inputs.enable_thinking) { + data.grammar_lazy = false; + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + builder.add_rule("root", "\"\" space \"\" space .* \"\" space"); + }); + data.preserved_tokens = { + "", + "", + "", + "", + }; + } + } + + return data; +} + +static void common_chat_parse_granite(common_chat_msg_parser & builder) { + // Parse thinking tags + builder.try_parse_reasoning("", ""); + + // Parse response tags using regex + static const common_regex response_regex("([\\s\\S]*?)"); + if (auto res = builder.try_find_regex(response_regex)) { + // Extract the content between the tags (capture group 1) + auto content = builder.str(res->groups[1]); + builder.add_content(content); + builder.move_to(res->groups[0].end); + } + + if (!builder.syntax().parse_tool_calls) { + builder.add_content(builder.consume_rest()); + return; + } + + // Look for tool calls + static const common_regex tool_call_regex(regex_escape("<|tool_call|>")); + if (auto res = builder.try_find_regex(tool_call_regex)) { + builder.move_to(res->groups[0].end); + + // Expect JSON array of tool calls + auto tool_calls_data = builder.consume_json(); + if (tool_calls_data.json.is_array()) { + if (!builder.add_tool_calls(tool_calls_data.json)) { + builder.add_content("<|tool_call|>" + tool_calls_data.json.dump()); + } + } else { + builder.add_content("<|tool_call|>" + tool_calls_data.json.dump()); } } else { builder.add_content(builder.consume_rest()); @@ -1733,6 +2061,8 @@ static common_chat_params common_chat_templates_apply_jinja( params.enable_thinking = inputs.enable_thinking; params.grammar = inputs.grammar; params.now = inputs.now; + params.add_bos = inputs.add_bos; + params.add_eos = inputs.add_eos; params.extra_context = json::object(); for (auto el : inputs.chat_template_kwargs) { @@ -1769,11 +2099,21 @@ static common_chat_params common_chat_templates_apply_jinja( return common_chat_params_init_command_r7b(tmpl, params); } + // Granite (IBM) - detects thinking / tools support + if (src.find("elif thinking") != std::string::npos && src.find("<|tool_call|>") != std::string::npos) { + return common_chat_params_init_granite(tmpl, params); + } + // Hermes 2/3 Pro, Qwen 2.5 Instruct (w/ tools) if (src.find("") != std::string::npos && params.json_schema.is_null()) { return common_chat_params_init_hermes_2_pro(tmpl, params); } + // GPT-OSS + if (src.find("<|channel|>") != std::string::npos && params.json_schema.is_null()) { + return common_chat_params_init_gpt_oss(tmpl, params); + } + // Use generic handler when mixing tools + JSON schema. // TODO: support that mix in handlers below. if ((params.tools.is_array() && params.json_schema.is_object())) { @@ -1824,6 +2164,7 @@ static common_chat_params common_chat_templates_apply_legacy( int alloc_size = 0; std::vector chat; std::vector contents; + for (const auto & msg : inputs.messages) { auto content = msg.content; for (const auto & part : msg.content_parts) { @@ -1925,6 +2266,12 @@ static void common_chat_parse(common_chat_msg_parser & builder) { case COMMON_CHAT_FORMAT_COMMAND_R7B: common_chat_parse_command_r7b(builder); break; + case COMMON_CHAT_FORMAT_GRANITE: + common_chat_parse_granite(builder); + break; + case COMMON_CHAT_FORMAT_GPT_OSS: + common_chat_parse_gpt_oss(builder); + break; default: throw std::runtime_error(std::string("Unsupported format: ") + common_chat_format_name(builder.syntax().format)); } @@ -1944,6 +2291,8 @@ common_chat_msg common_chat_parse(const std::string & input, bool is_partial, co } } auto msg = builder.result(); - LOG_DBG("Parsed message: %s\n", common_chat_msgs_to_json_oaicompat({msg}).at(0).dump().c_str()); + if (!is_partial) { + LOG_DBG("Parsed message: %s\n", common_chat_msgs_to_json_oaicompat({msg}).at(0).dump().c_str()); + } return msg; } diff --git a/common/chat.h b/common/chat.h index ca807c145e..d1e480c918 100644 --- a/common/chat.h +++ b/common/chat.h @@ -109,6 +109,8 @@ enum common_chat_format { COMMON_CHAT_FORMAT_FUNCTIONARY_V3_1_LLAMA_3_1, COMMON_CHAT_FORMAT_HERMES_2_PRO, COMMON_CHAT_FORMAT_COMMAND_R7B, + COMMON_CHAT_FORMAT_GRANITE, + COMMON_CHAT_FORMAT_GPT_OSS, COMMON_CHAT_FORMAT_COUNT, // Not a format, just the # formats }; @@ -127,6 +129,8 @@ struct common_chat_templates_inputs { bool enable_thinking = true; std::chrono::system_clock::time_point now = std::chrono::system_clock::now(); std::map chat_template_kwargs; + bool add_bos = false; + bool add_eos = false; }; struct common_chat_params { @@ -183,10 +187,12 @@ std::string common_chat_format_single( // Returns an example of formatted chat std::string common_chat_format_example( const struct common_chat_templates * tmpls, - bool use_jinja); + bool use_jinja, + const std::map & chat_template_kwargs); const char* common_chat_format_name(common_chat_format format); const char* common_reasoning_format_name(common_reasoning_format format); +common_reasoning_format common_reasoning_format_from_name(const std::string & format); common_chat_msg common_chat_parse(const std::string & input, bool is_partial, const common_chat_syntax & syntax); common_chat_tool_choice common_chat_tool_choice_parse_oaicompat(const std::string & tool_choice); diff --git a/common/common.cpp b/common/common.cpp index d8c4d988b6..67dd5404ff 100644 --- a/common/common.cpp +++ b/common/common.cpp @@ -41,6 +41,7 @@ #endif #include #include +#include #include #include #else @@ -1122,6 +1123,7 @@ struct llama_model_params common_model_params_to_llama(common_params & params) { mparams.use_mmap = params.use_mmap; mparams.use_mlock = params.use_mlock; mparams.check_tensors = params.check_tensors; + mparams.use_extra_bufts = !params.no_extra_bufts; if (params.kv_overrides.empty()) { mparams.kv_overrides = NULL; @@ -1564,3 +1566,56 @@ ggml_opt_dataset_t common_opt_dataset_init(struct llama_context * ctx, const std return result; } + +ggml_opt_optimizer_params common_opt_lr_pars(void * userdata) { + ggml_opt_optimizer_params result = ggml_opt_get_default_optimizer_params(nullptr); + const lr_opt & d = *(lr_opt *) userdata; + result.adamw.alpha = result.sgd.alpha = d.get_lr(d.epoch); + result.sgd.wd = result.adamw.wd = d.wd; + return result; +} + +// TODO make all command line args case-insensitive +static inline bool eq_case_insensitive(char const* a, char const* b) { + return ! +#if defined(_MSC_VER) + _stricmp +#else + strcasecmp +#endif // defined(_MSC_VER) + (a, b); +} + +enum ggml_opt_optimizer_type common_opt_get_optimizer(const char * n) { + if (eq_case_insensitive("adamw", n)) { + return GGML_OPT_OPTIMIZER_TYPE_ADAMW; + } + if (eq_case_insensitive("sgd", n)) { + return GGML_OPT_OPTIMIZER_TYPE_SGD; + } + return GGML_OPT_OPTIMIZER_TYPE_COUNT; +} + +// TODO simplify to use just log and exp +static float const k_log_2 = std::log(2.f); + +void lr_opt::init() { + if (lr_min > 0 && lr_min < lr0) { + float nhalf = std::log(lr0 / lr_min) / k_log_2; + float e = epochs; + if (decay_epochs > 0 && decay_epochs < e) { + e = decay_epochs; + } else { + decay_epochs = e; + } + scale_epoch = nhalf / e; + } +} + +float lr_opt::get_lr(float epoch) const { + float r = lr_min <= 0 ? lr0 : + epoch >= decay_epochs ? lr_min : + lr0 * std::pow(0.5f, epoch * scale_epoch); + LOG_INF("epoch %.2g lr=%.2g\n", epoch, r); + return r; +} diff --git a/common/common.h b/common/common.h index 11427c51f6..75596e6b32 100644 --- a/common/common.h +++ b/common/common.h @@ -2,14 +2,17 @@ #pragma once -#include "llama-cpp.h" - #include +#include #include #include #include #include #include +#include + +#include "ggml-opt.h" +#include "llama-cpp.h" #ifdef _WIN32 #define DIRECTORY_SEPARATOR '\\' @@ -82,6 +85,7 @@ enum llama_example { LLAMA_EXAMPLE_PARALLEL, LLAMA_EXAMPLE_TTS, LLAMA_EXAMPLE_DIFFUSION, + LLAMA_EXAMPLE_FINETUNE, LLAMA_EXAMPLE_COUNT, }; @@ -201,6 +205,8 @@ struct common_params_speculative { int32_t n_gpu_layers = -1; // number of layers to store in VRAM for the draft model (-1 - use default) float p_split = 0.1f; // speculative decoding split probability float p_min = 0.75f; // minimum speculative decoding probability (greedy) + std::vector> replacements; // main to speculative model replacements + std::vector tensor_buft_overrides; ggml_type cache_type_k = GGML_TYPE_F16; // KV cache data type for the K ggml_type cache_type_v = GGML_TYPE_F16; // KV cache data type for the V @@ -220,19 +226,46 @@ struct common_params_vocoder { }; struct common_params_diffusion { - int32_t steps = 64; // number of diffusion steps - float eps = 1e-3f; // epsilon for timesteps - int32_t algorithm = 0; // diffusion algorithm (0=ORIGIN, 1=MASKGIT_PLUS, 2=TOPK_MARGIN, 3=ENTROPY) - float alg_temp = 0.0f; // algorithm temperature - bool visual_mode = false; // show progressive diffusion on screen + int32_t steps = 128; + bool visual_mode = false; + + float eps = 0; // epsilon for timesteps + int32_t block_length = 0; // block length for generation + + int32_t algorithm = 4; // default algorithm: low-confidence + float alg_temp = 0.0f; // algorithm temperature + + float cfg_scale = 0; // classifier-free guidance scale + bool add_gumbel_noise = false; // add gumbel noise to the logits if temp > 0.0 }; enum common_reasoning_format { COMMON_REASONING_FORMAT_NONE, + COMMON_REASONING_FORMAT_AUTO, COMMON_REASONING_FORMAT_DEEPSEEK_LEGACY, // Extract thinking tag contents and return as `message.reasoning_content`, or leave inline in tags in stream mode COMMON_REASONING_FORMAT_DEEPSEEK, // Extract thinking tag contents and return as `message.reasoning_content`, including in streaming deltas. + COMMON_REASONING_FORMAT_GRANITE, // Extract thinking tag contents and return as `message.reasoning_content`, including in streaming deltas. }; + +struct lr_opt { + float lr0 = 1e-5; // learning rate at first epoch + float lr_min = -1; + float decay_epochs = -1; // if >0, the learning rate starts at lr0 and decays to lr_min after this many epochs + float scale_epoch = 0; + float wd = 0; + unsigned epochs = 2; + + unsigned epoch; // set by optimizer outer (epochs) loop + // learning rate decay - constant LR per epoch only for now + float get_lr(float e) const; + float get_lr() const { return get_lr(epoch); } + // must call after arg parse, before get_lr + void init(); +}; + +struct ggml_opt_optimizer_params common_opt_lr_pars(void * userdata); + struct common_params { int32_t n_predict = -1; // new tokens to predict int32_t n_ctx = 4096; // context size @@ -352,6 +385,7 @@ struct common_params { bool warmup = true; // warmup run bool check_tensors = false; // validate tensor data bool no_op_offload = false; // globally disable offload host tensor operations to device + bool no_extra_bufts = false; // disable extra buffer types (used for weight repacking) bool single_turn = false; // single turn chat conversation @@ -366,6 +400,11 @@ struct common_params { bool no_mmproj = false; // explicitly disable multimodal model std::vector image; // path to image file(s) + // finetune + struct lr_opt lr; + enum ggml_opt_optimizer_type optimizer = GGML_OPT_OPTIMIZER_TYPE_ADAMW; + float val_split = 0.05f; // fraction of the data used for the validation set + // embedding bool embedding = false; // get only sentence embedding int32_t embd_normalize = 2; // normalisation for embeddings (-1=none, 0=max absolute int16, 1=taxicab, 2=euclidean, >2=p-norm) @@ -374,11 +413,12 @@ struct common_params { std::string cls_sep = "\t"; // separator of classification sequences // server params - int32_t port = 8080; // server listens on this network port - int32_t timeout_read = 600; // http read timeout in seconds - int32_t timeout_write = timeout_read; // http write timeout in seconds - int32_t n_threads_http = -1; // number of threads to process HTTP requests (TODO: support threadpool) - int32_t n_cache_reuse = 0; // min chunk size to reuse from the cache via KV shifting + int32_t port = 8080; // server listens on this network port + int32_t timeout_read = 600; // http read timeout in seconds + int32_t timeout_write = timeout_read; // http write timeout in seconds + int32_t n_threads_http = -1; // number of threads to process HTTP requests (TODO: support threadpool) + int32_t n_cache_reuse = 0; // min chunk size to reuse from the cache via KV shifting + int32_t n_swa_checkpoints = 3; // max number of SWA checkpoints per slot std::string hostname = "127.0.0.1"; std::string public_path = ""; // NOLINT @@ -386,7 +426,7 @@ struct common_params { std::string chat_template = ""; // NOLINT bool use_jinja = false; // NOLINT bool enable_chat_template = true; - common_reasoning_format reasoning_format = COMMON_REASONING_FORMAT_DEEPSEEK; + common_reasoning_format reasoning_format = COMMON_REASONING_FORMAT_AUTO; int reasoning_budget = -1; bool prefill_assistant = true; // if true, any trailing assistant message will be prefilled into the response @@ -431,10 +471,12 @@ struct common_params { int32_t n_out_freq = 10; // output the imatrix every n_out_freq iterations int32_t n_save_freq = 0; // save the imatrix every n_save_freq iterations int32_t i_chunk = 0; // start processing from this chunk + int8_t imat_dat = 0; // whether the legacy imatrix.dat format should be output (gguf <= 0 < dat) - bool process_output = false; // collect data for the output tensor - bool compute_ppl = true; // whether to compute perplexity - bool parse_special = false; // whether to parse special tokens during imatrix tokenization + bool process_output = false; // collect data for the output tensor + bool compute_ppl = true; // whether to compute perplexity + bool show_statistics = false; // show imatrix statistics per tensor + bool parse_special = false; // whether to parse special tokens during imatrix tokenization // cvector-generator params int n_pca_batch = 100; @@ -691,3 +733,6 @@ const char * const LLM_KV_SPLIT_TENSORS_COUNT = "split.tensors.count"; // ggml_opt_dataset_t common_opt_dataset_init(struct llama_context * ctx, const std::vector & tokens, int64_t stride); + +// "adamw" or "sgd" (case insensitive) +enum ggml_opt_optimizer_type common_opt_get_optimizer(const char *); diff --git a/common/speculative.cpp b/common/speculative.cpp index 843bd1ddbd..262b2c23e7 100644 --- a/common/speculative.cpp +++ b/common/speculative.cpp @@ -1,30 +1,39 @@ #include "speculative.h" +#include "ggml.h" +#include "llama.h" #include "log.h" #include "common.h" #include "sampling.h" #include #include +#include #define SPEC_VOCAB_MAX_SIZE_DIFFERENCE 128 #define SPEC_VOCAB_CHECK_START_TOKEN_ID 5 struct common_speculative { - struct llama_context * ctx; + struct llama_context * ctx_tgt; // only used for retokenizing from ctx_dft + struct llama_context * ctx_dft; struct common_sampler * smpl; llama_batch batch; - llama_tokens prompt; + llama_tokens prompt_dft; + bool vocab_dft_compatible = true; // whether retokenization is needed + std::map tgt_dft_replacements = {}; }; struct common_speculative * common_speculative_init( + struct llama_context * ctx_tgt, struct llama_context * ctx_dft) { auto * result = new common_speculative { - /* .ctx = */ ctx_dft, - /* .smpl = */ nullptr, - /* .batch = */ llama_batch_init(llama_n_batch(ctx_dft), 0, 1), - /* .prompt = */ {}, + /* .ctx_tgt = */ ctx_tgt, + /* .ctx_dft = */ ctx_dft, + /* .smpl = */ nullptr, + /* .batch = */ llama_batch_init(llama_n_batch(ctx_dft), 0, 1), + /* .prompt_dft = */ {}, + /* .vocab_dft_compatible = */ false, }; // TODO: optimize or pass from outside? @@ -59,6 +68,9 @@ struct common_speculative * common_speculative_init( } #endif + result->vocab_dft_compatible = common_speculative_are_compatible(ctx_tgt, ctx_dft); + LOG_DBG("vocab_dft_compatible = %d\n", result->vocab_dft_compatible); + return result; } @@ -75,8 +87,8 @@ void common_speculative_free(struct common_speculative * spec) { } bool common_speculative_are_compatible( - const struct llama_context * ctx_tgt, - const struct llama_context * ctx_dft) { + const struct llama_context * ctx_tgt, + const struct llama_context * ctx_dft) { const struct llama_model * model_tgt = llama_get_model(ctx_tgt); const struct llama_model * model_dft = llama_get_model(ctx_dft); @@ -90,31 +102,32 @@ bool common_speculative_are_compatible( LOG_DBG("%s: vocab_type dft: %d\n", __func__, vocab_type_dft); if (vocab_type_tgt != vocab_type_dft) { - LOG_ERR("%s: draft model vocab type must match target model to use speculation but " - "vocab_type_dft = %d while vocab_type_tgt = %d\n", __func__, vocab_type_dft, vocab_type_tgt); + LOG_DBG("%s: draft model vocab type must match target model to use speculation but ", __func__); + LOG_DBG("vocab_type_dft = %d while vocab_type_tgt = %d\n", vocab_type_dft, vocab_type_tgt); return false; } - if (llama_vocab_get_add_bos(vocab_tgt) != llama_vocab_get_add_bos(vocab_dft) || + if ( + llama_vocab_get_add_bos(vocab_tgt) != llama_vocab_get_add_bos(vocab_dft) || llama_vocab_get_add_eos(vocab_tgt) != llama_vocab_get_add_eos(vocab_dft) || llama_vocab_bos(vocab_tgt) != llama_vocab_bos(vocab_dft) || - llama_vocab_eos(vocab_tgt) != llama_vocab_eos(vocab_dft)) { - LOG_ERR("%s: draft vocab special tokens must match target vocab to use speculation\n", __func__); - LOG_ERR("%s: tgt: bos = %d (%d), eos = %d (%d)\n", __func__, llama_vocab_bos(vocab_tgt), llama_vocab_get_add_bos(vocab_tgt), llama_vocab_eos(vocab_tgt), llama_vocab_get_add_eos(vocab_tgt)); - LOG_ERR("%s: dft: bos = %d (%d), eos = %d (%d)\n", __func__, llama_vocab_bos(vocab_dft), llama_vocab_get_add_bos(vocab_dft), llama_vocab_eos(vocab_dft), llama_vocab_get_add_eos(vocab_dft)); + llama_vocab_eos(vocab_tgt) != llama_vocab_eos(vocab_dft) + ) { + LOG_DBG("%s: draft model special tokens must match target model to use speculation\n", __func__); return false; } { const int n_vocab_tgt = llama_vocab_n_tokens(vocab_tgt); const int n_vocab_dft = llama_vocab_n_tokens(vocab_dft); - - const int vocab_diff = std::abs(n_vocab_tgt - n_vocab_dft); + const int vocab_diff = n_vocab_tgt > n_vocab_dft + ? n_vocab_tgt - n_vocab_dft + : n_vocab_dft - n_vocab_tgt; if (vocab_diff > SPEC_VOCAB_MAX_SIZE_DIFFERENCE) { - LOG_ERR("%s: draft model vocab must closely match target model to use speculation but " - "target vocab size %d does not match draft vocab size %d - difference %d, max allowed %d\n", - __func__, n_vocab_tgt, llama_vocab_n_tokens(vocab_dft), vocab_diff, SPEC_VOCAB_MAX_SIZE_DIFFERENCE); + LOG_DBG("%s: draft model vocab must closely match target model to use speculation but ", __func__); + LOG_DBG("target vocab size %d does not match draft vocab size %d - difference %d, max allowed %d\n", + n_vocab_tgt, llama_vocab_n_tokens(vocab_dft), vocab_diff, SPEC_VOCAB_MAX_SIZE_DIFFERENCE); return false; } @@ -122,8 +135,8 @@ bool common_speculative_are_compatible( const char * token_text_tgt = llama_vocab_get_text(vocab_tgt, i); const char * token_text_dft = llama_vocab_get_text(vocab_dft, i); if (std::strcmp(token_text_tgt, token_text_dft) != 0) { - LOG_ERR("%s: draft vocab vocab must match target vocab to use speculation but " - "token %d content differs - target '%s', draft '%s'\n", __func__, i, + LOG_DBG("%s: draft model vocab must match target model to use speculation but ", __func__); + LOG_DBG("token %d content differs - target '%s', draft '%s'\n", i, common_token_to_piece(ctx_tgt, i).c_str(), common_token_to_piece(ctx_dft, i).c_str()); return false; @@ -134,32 +147,93 @@ bool common_speculative_are_compatible( return true; } +void common_speculative_add_replacement_tgt_dft( + struct common_speculative * spec, + const char *source, const char *dest) { + spec->tgt_dft_replacements[source] = dest; +} + +static std::string replace_to_dft( + struct common_speculative * spec, + const std::string& input) { + std::string result = input; + for (const auto & pair : spec->tgt_dft_replacements) { + size_t pos = result.find(pair.first); + while (pos != std::string::npos) { + result.replace(pos, pair.first.length(), pair.second); + pos = result.find(pair.first, pos + pair.second.length()); + } + } + return result; +} + +static std::string replace_to_tgt( + struct common_speculative * spec, + const std::string& input) { + std::string result = input; + for (const auto& pair : spec->tgt_dft_replacements) { + size_t pos = result.find(pair.second); + while (pos != std::string::npos) { + result.replace(pos, pair.second.length(), pair.first); + pos = result.find(pair.second, pos + pair.first.length()); + } + } + return result; +} + + llama_tokens common_speculative_gen_draft( struct common_speculative * spec, struct common_speculative_params params, - const llama_tokens & prompt_tgt, + const llama_tokens & prompt_tgt_main_model, // specified in target model vocab llama_token id_last) { auto & batch = spec->batch; - auto & ctx = spec->ctx; + auto & ctx_tgt = spec->ctx_tgt; + auto & ctx_dft = spec->ctx_dft; auto & smpl = spec->smpl; - auto & prompt = spec->prompt; + auto & prompt_dft = spec->prompt_dft; - auto * mem = llama_get_memory(ctx); + auto * mem_dft = llama_get_memory(ctx_dft); int reuse_i = 0; int reuse_n = 0; - const int n_ctx = llama_n_ctx(ctx) - params.n_draft; + const int n_ctx = llama_n_ctx(ctx_dft) - params.n_draft; + + llama_tokens prompt_tgt_draft_model; + if (!spec->vocab_dft_compatible) { + std::string text; + text = common_detokenize(ctx_tgt, prompt_tgt_main_model, true); + text = replace_to_dft(spec, text); + LOG_DBG("%s: main->draft detokenized string: '%s'\n", __func__, text.c_str()); + prompt_tgt_draft_model = common_tokenize(ctx_dft, text, false, true); + + // convert id_last to draft vocab. llama_detokenize is called directly to avoid an allocation + const auto * model_tgt = llama_get_model(ctx_tgt); + const auto * vocab_tgt = llama_model_get_vocab(model_tgt); + + int32_t n_chars = llama_detokenize(vocab_tgt, &id_last, 1, nullptr, 0, false, false); + GGML_ASSERT(n_chars < 0 && "failed to detokenize id_last"); + text.resize(-n_chars); + llama_detokenize(vocab_tgt, &id_last, 1, text.data(), text.size(), false, false); + text = replace_to_dft(spec, text); + + LOG_DBG("main->draft detokenized id_last(%d): '%s'\n", id_last, text.c_str()); + id_last = common_tokenize(ctx_dft, text, false, true)[0]; + } + // prompt_tgt's tokens will always be compatible with ctx_dft + const llama_tokens &prompt_tgt = + spec->vocab_dft_compatible ? prompt_tgt_main_model : prompt_tgt_draft_model; const int i_start = std::max(0, (int) prompt_tgt.size() - n_ctx); // reuse as much as possible from the old draft context // ideally, the draft context should be as big as the target context and we will always reuse the entire prompt - for (int i = 0; i < (int) prompt.size(); ++i) { + for (int i = 0; i < (int) prompt_dft.size(); ++i) { int cur = 0; while (i_start + cur < (int) prompt_tgt.size() && - i + cur < (int) prompt.size() && - prompt_tgt[i_start + cur] == prompt[i + cur]) { + i + cur < (int) prompt_dft.size() && + prompt_tgt[i_start + cur] == prompt_dft[i + cur]) { cur++; } @@ -169,21 +243,20 @@ llama_tokens common_speculative_gen_draft( } } - LOG_DBG("%s: reuse_i = %d, reuse_n = %d, prompt = %d\n", __func__, reuse_i, reuse_n, (int) prompt.size()); + LOG_DBG("%s: reuse_i = %d, reuse_n = %d, prompt = %d\n", __func__, reuse_i, reuse_n, (int) prompt_dft.size()); llama_tokens result; result.reserve(params.n_draft); if (reuse_n == 0) { - llama_memory_clear(mem, false); - - prompt.clear(); + llama_memory_clear(mem_dft, false); + prompt_dft.clear(); } else { // this happens when a previous draft has been discarded (for example, due to being too small), but the // target model agreed with it. in this case, we simply pass back the previous results to save compute - if (reuse_i + reuse_n < (int) prompt.size() && prompt[reuse_i + reuse_n] == id_last) { - for (int i = reuse_i + reuse_n + 1; i < (int) prompt.size(); ++i) { - result.push_back(prompt[i]); + if (reuse_i + reuse_n < (int) prompt_dft.size() && prompt_dft[reuse_i + reuse_n] == id_last) { + for (int i = reuse_i + reuse_n + 1; i < (int) prompt_dft.size(); ++i) { + result.push_back(prompt_dft[i]); if (params.n_draft <= (int) result.size()) { break; @@ -194,16 +267,15 @@ llama_tokens common_speculative_gen_draft( } if (reuse_i > 0) { - llama_memory_seq_rm (mem, 0, 0, reuse_i); - llama_memory_seq_add(mem, 0, reuse_i, -1, -reuse_i); + llama_memory_seq_rm (mem_dft, 0, 0, reuse_i); + llama_memory_seq_add(mem_dft, 0, reuse_i, -1, -reuse_i); - prompt.erase(prompt.begin(), prompt.begin() + reuse_i); + prompt_dft.erase(prompt_dft.begin(), prompt_dft.begin() + reuse_i); } - if (reuse_n < (int) prompt.size()) { - llama_memory_seq_rm (mem, 0, reuse_n, -1); - - prompt.erase(prompt.begin() + reuse_n, prompt.end()); + if (reuse_n < (int) prompt_dft.size()) { + llama_memory_seq_rm (mem_dft, 0, reuse_n, -1); + prompt_dft.erase(prompt_dft.begin() + reuse_n, prompt_dft.end()); } } @@ -214,28 +286,28 @@ llama_tokens common_speculative_gen_draft( //LOG_DBG("i = %d, i_start = %d, reuse_n = %d, i - i_start = %d, id = %6d\n", i, i_start, reuse_n, i - i_start, prompt_tgt[i]); common_batch_add(batch, prompt_tgt[i], i - i_start, { 0 }, false); - prompt.push_back(prompt_tgt[i]); + prompt_dft.push_back(prompt_tgt[i]); } // we should rarely end-up here during normal decoding if (batch.n_tokens > 0) { //LOG_DBG("%s: draft prompt batch: %s\n", __func__, string_from(ctx, batch).c_str()); - llama_decode(ctx, batch); + llama_decode(ctx_dft, batch); } - const llama_pos n_past = prompt.size(); + const llama_pos n_past = prompt_dft.size(); LOG_DBG("%s: n_past = %d\n", __func__, n_past); common_batch_clear(batch); common_batch_add (batch, id_last, n_past, { 0 }, true); - prompt.push_back(id_last); + prompt_dft.push_back(id_last); - //LOG_DBG("%s: draft prompt: %s\n", __func__, string_from(ctx, prompt).c_str()); + LOG_DBG("%s: draft prompt: %s\n", __func__, string_from(ctx_dft, prompt_dft).c_str()); - llama_decode(ctx, batch); + llama_decode(ctx_dft, batch); common_sampler_reset(smpl); @@ -243,13 +315,13 @@ llama_tokens common_speculative_gen_draft( for (int i = 0; i < params.n_draft; ++i) { common_batch_clear(batch); - common_sampler_sample(smpl, ctx, 0, true); + common_sampler_sample(smpl, ctx_dft, 0, true); const auto * cur_p = common_sampler_get_candidates(smpl); for (int k = 0; k < std::min(3, (int) cur_p->size); ++k) { LOG_DBG(" - draft candidate %3d, pos %3d: %6d (%8.3f) '%s'\n", - k, i, cur_p->data[k].id, cur_p->data[k].p, common_token_to_piece(ctx, cur_p->data[k].id).c_str()); + k, i, cur_p->data[k].id, cur_p->data[k].p, common_token_to_piece(ctx_dft, cur_p->data[k].id).c_str()); } // add drafted token for each sequence @@ -271,10 +343,19 @@ llama_tokens common_speculative_gen_draft( common_batch_add(batch, id, n_past + i + 1, { 0 }, true); // evaluate the drafted tokens on the draft model - llama_decode(ctx, batch); + llama_decode(ctx_dft, batch); - prompt.push_back(id); + prompt_dft.push_back(id); } + if (!spec->vocab_dft_compatible) { + std::string detokenized = common_detokenize(ctx_dft, result, true); + detokenized = replace_to_tgt(spec, detokenized); + LOG_DBG("draft->main detokenized string: '%s'\n", detokenized.c_str()); + result = common_tokenize(ctx_tgt, detokenized, false, true); + if (result.size() > (size_t)params.n_draft) { + result.resize(params.n_draft); + } + } return result; } diff --git a/common/speculative.h b/common/speculative.h index 2b51a70ca1..e69d7aaa1e 100644 --- a/common/speculative.h +++ b/common/speculative.h @@ -12,7 +12,10 @@ struct common_speculative_params { float p_min = 0.75f; // min probability required to accept a token in the draft }; -struct common_speculative * common_speculative_init(struct llama_context * ctx_dft); +struct common_speculative * common_speculative_init( + struct llama_context * ctx_tgt, + struct llama_context * ctx_dft +); void common_speculative_free(struct common_speculative * spec); @@ -20,6 +23,10 @@ bool common_speculative_are_compatible( const struct llama_context * ctx_tgt, const struct llama_context * ctx_dft); +void common_speculative_add_replacement_tgt_dft( + struct common_speculative * spec, + const char *source, const char *dest); + // sample up to n_draft tokens and add them to the batch using the draft model llama_tokens common_speculative_gen_draft( struct common_speculative * spec, diff --git a/convert_hf_to_gguf.py b/convert_hf_to_gguf.py index 7364c55e35..a7c5e210f7 100755 --- a/convert_hf_to_gguf.py +++ b/convert_hf_to_gguf.py @@ -28,6 +28,14 @@ if TYPE_CHECKING: if 'NO_LOCAL_GGUF' not in os.environ: sys.path.insert(1, str(Path(__file__).parent / 'gguf-py')) import gguf +from gguf.vocab import MistralTokenizerType, MistralVocab +from mistral_common.tokens.tokenizers.base import TokenizerVersion +from mistral_common.tokens.tokenizers.multimodal import DATASET_MEAN, DATASET_STD +from mistral_common.tokens.tokenizers.tekken import Tekkenizer +from mistral_common.tokens.tokenizers.sentencepiece import ( + SentencePieceTokenizer, +) + logger = logging.getLogger("hf-to-gguf") @@ -79,6 +87,8 @@ class ModelBase: block_count: int tensor_map: gguf.TensorNameMap + is_mistral_format: bool = False + def __init__(self, dir_model: Path, ftype: gguf.LlamaFileType, fname_out: Path, *, is_big_endian: bool = False, use_temp_file: bool = False, eager: bool = False, metadata_override: Path | None = None, model_name: str | None = None, @@ -97,7 +107,7 @@ class ModelBase: self.use_temp_file = use_temp_file self.lazy = not eager or (remote_hf_model_id is not None) self.remote_hf_model_id = remote_hf_model_id - self.hparams = ModelBase.load_hparams(self.dir_model) if hparams is None else hparams + self.hparams = ModelBase.load_hparams(self.dir_model, self.is_mistral_format) if hparams is None else hparams self.model_tensors = self.index_tensors(remote_hf_model_id=remote_hf_model_id) self.metadata_override = metadata_override self.model_name = model_name @@ -147,25 +157,29 @@ class ModelBase: return tensors - part_names: list[str] = ModelBase.get_model_part_names(self.dir_model, "model", ".safetensors") + prefix = "model" if not self.is_mistral_format else "consolidated" + part_names: list[str] = ModelBase.get_model_part_names(self.dir_model, prefix, ".safetensors") is_safetensors: bool = len(part_names) > 0 if not is_safetensors: part_names = ModelBase.get_model_part_names(self.dir_model, "pytorch_model", ".bin") tensor_names_from_index: set[str] = set() - index_name = "model.safetensors" if is_safetensors else "pytorch_model.bin" - index_name += ".index.json" - index_file = self.dir_model / index_name + if not self.is_mistral_format: + index_name = "model.safetensors" if is_safetensors else "pytorch_model.bin" + index_name += ".index.json" + index_file = self.dir_model / index_name - if index_file.is_file(): - logger.info(f"gguf: loading model weight map from '{index_name}'") - with open(index_file, "r", encoding="utf-8") as f: - index: dict[str, Any] = json.load(f) - weight_map = index.get("weight_map") - if weight_map is None or not isinstance(weight_map, dict): - raise ValueError(f"Can't load 'weight_map' from {index_name!r}") - tensor_names_from_index.update(weight_map.keys()) + if index_file.is_file(): + logger.info(f"gguf: loading model weight map from '{index_name}'") + with open(index_file, "r", encoding="utf-8") as f: + index: dict[str, Any] = json.load(f) + weight_map = index.get("weight_map") + if weight_map is None or not isinstance(weight_map, dict): + raise ValueError(f"Can't load 'weight_map' from {index_name!r}") + tensor_names_from_index.update(weight_map.keys()) + else: + weight_map = {} else: weight_map = {} @@ -556,7 +570,12 @@ class ModelBase: return part_names @staticmethod - def load_hparams(dir_model: Path): + def load_hparams(dir_model: Path, is_mistral_format: bool): + if is_mistral_format: + with open(dir_model / "params.json", "r", encoding="utf-8") as f: + config = json.load(f) + return config + try: # for security reason, we don't allow loading remote code by default # if a model need remote code, we will fallback to config.json @@ -606,7 +625,10 @@ class TextModel(ModelBase): def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) - self.hf_arch = get_model_architecture(self.hparams, self.model_type) + if not self.is_mistral_format: + self.hf_arch = get_model_architecture(self.hparams, self.model_type) + else: + self.hf_arch = "" if "text_config" in self.hparams: # move the text_config to the root level @@ -672,14 +694,14 @@ class TextModel(ModelBase): self.gguf_writer.add_head_count(n_head) logger.info(f"gguf: head count = {n_head}") - if (n_head_kv := self.hparams.get("num_key_value_heads")) is not None: + if (n_head_kv := self.find_hparam(["num_key_value_heads", "n_kv_heads"], optional=True)) is not None: self.gguf_writer.add_head_count_kv(n_head_kv) logger.info(f"gguf: key-value head count = {n_head_kv}") if (rope_theta := self.hparams.get("rope_theta")) is not None: self.gguf_writer.add_rope_freq_base(rope_theta) logger.info(f"gguf: rope theta = {rope_theta}") - if (f_rms_eps := self.hparams.get("rms_norm_eps")) is not None: + if (f_rms_eps := self.find_hparam(["rms_norm_eps", "norm_eps"], optional=True)) is not None: self.gguf_writer.add_layer_norm_rms_eps(f_rms_eps) logger.info(f"gguf: rms norm epsilon = {f_rms_eps}") if (f_norm_eps := self.find_hparam(["layer_norm_eps", "layer_norm_epsilon", "norm_epsilon"], optional=True)) is not None: @@ -808,12 +830,18 @@ class TextModel(ModelBase): if chkhsh == "a1336059768a55c99a734006ffb02203cd450fed003e9a71886c88acf24fdbc2": # ref: https://huggingface.co/THUDM/glm-4-9b-hf res = "glm4" + if chkhsh == "9ca2dd618e8afaf09731a7cf6e2105b373ba6a1821559f258b272fe83e6eb902": + # ref: https://huggingface.co/zai-org/GLM-4.5-Air + res = "glm4" if chkhsh == "1431a23e583c97432bc230bff598d103ddb5a1f89960c8f1d1051aaa944d0b35": # ref: https://huggingface.co/sapienzanlp/Minerva-7B-base-v1.0 res = "minerva-7b" if chkhsh == "7e57df22b1fe23a7b1e1c7f3dc4e3f96d43a4eb0836d0c6bdc3436d7b2f1c664": # ref: https://huggingface.co/tencent/Hunyuan-A13B-Instruct res = "hunyuan" + if chkhsh == "bba3b3366b646dbdded5dbc42d59598b849371afc42f7beafa914afaa5b70aa6": + # ref: https://huggingface.co/tencent/Hunyuan-4B-Instruct + res = "hunyuan-dense" if chkhsh == "a6b57017d60e6edb4d88ecc2845188e0eb333a70357e45dcc9b53964a73bbae6": # ref: https://huggingface.co/tiiuae/Falcon-H1-0.5B-Base res = "falcon-h1" @@ -829,6 +857,9 @@ class TextModel(ModelBase): if chkhsh == "81212dc7cdb7e0c1074ca62c5aeab0d43c9f52b8a737be7b12a777c953027890": # ref: https://huggingface.co/moonshotai/Kimi-K2-Base res = "kimi-k2" + if chkhsh == "d4540891389ea895b53b399da6ac824becc30f2fba0e9ddbb98f92e55ca0e97c": + # ref: https://huggingface.co/Qwen/Qwen3-Embedding-0.6B + res = "qwen2" if chkhsh == "0ef9807a4087ebef797fc749390439009c3b9eda9ad1a097abbe738f486c01e5": # ref: https://huggingface.co/meta-llama/Meta-Llama-3-8B res = "llama-bpe" @@ -976,6 +1007,9 @@ class TextModel(ModelBase): if chkhsh == "2085e1638f6c377a0aa4ead21b27bb4cb941bf800df86ed391011769c1758dfb": # ref: https://huggingface.co/LGAI-EXAONE/EXAONE-4.0-32B res = "exaone4" + if chkhsh == "a1e163ecab2e718a4c829d1148b6e86824ec36163bb71941c3dca9cd5ac25756": + # ref: https://huggingface.co/JetBrains/Mellum-4b-base + res = "mellum" if res is None: logger.warning("\n") @@ -1328,12 +1362,19 @@ class MmprojModel(ModelBase): raise TypeError("MmprojModel must be subclassed with model_arch = gguf.MODEL_ARCH.MMPROJ") # get n_embd of the text model - if "text_config" not in self.hparams: - self.hparams["text_config"] = {} - if "audio_config" not in self.hparams: - self.hparams["audio_config"] = {} - text_config = {**self.hparams, **self.hparams["text_config"]} - self.n_embd_text = text_config.get("hidden_size", text_config.get("n_embd", 0)) + if not self.is_mistral_format: + if "text_config" not in self.hparams: + self.hparams["text_config"] = {} + if "audio_config" not in self.hparams: + self.hparams["audio_config"] = {} + text_config = {**self.hparams, **self.hparams["text_config"]} + self.n_embd_text = text_config.get("hidden_size", text_config.get("n_embd", 0)) + else: + text_config = { + k: v for k, v in self.hparams.items() if k not in ["vision_encoder", "audio_encoder"] + } + self.n_embd_text = text_config.get("hidden_dim", 0) + assert self.n_embd_text > 0, "n_embd not found in hparams" # move vision config to the top level, while preserving the original hparams in global_config @@ -1354,11 +1395,13 @@ class MmprojModel(ModelBase): self.tensor_map = gguf.get_tensor_name_map(gguf.MODEL_ARCH.MMPROJ, self.block_count) # load preprocessor config - with open(self.dir_model / "preprocessor_config.json", "r", encoding="utf-8") as f: - self.preprocessor_config = json.load(f) + if not self.is_mistral_format: + with open(self.dir_model / "preprocessor_config.json", "r", encoding="utf-8") as f: + self.preprocessor_config = json.load(f) def get_vision_config(self) -> dict[str, Any] | None: - return self.global_config.get("vision_config") + config_name = "vision_config" if not self.is_mistral_format else "vision_encoder" + return self.global_config.get(config_name) def get_audio_config(self) -> dict[str, Any] | None: return self.global_config.get("audio_config") @@ -1382,8 +1425,11 @@ class MmprojModel(ModelBase): self.gguf_writer.add_vision_head_count(self.find_vparam(["num_attention_heads"])) # preprocessor config - self.gguf_writer.add_vision_image_mean(self.preprocessor_config["image_mean"]) - self.gguf_writer.add_vision_image_std(self.preprocessor_config["image_std"]) + image_mean = DATASET_MEAN if self.is_mistral_format else self.preprocessor_config["image_mean"] + image_std = DATASET_STD if self.is_mistral_format else self.preprocessor_config["image_std"] + + self.gguf_writer.add_vision_image_mean(image_mean) + self.gguf_writer.add_vision_image_std(image_std) if self.has_audio_encoder: self.gguf_writer.add_clip_has_audio_encoder(True) @@ -2030,6 +2076,7 @@ class StableLMModel(TextModel): "MixtralForCausalLM", "VLlama3ForCausalLM", "LlavaForConditionalGeneration", + "VoxtralForConditionalGeneration", "LlamaModel") class LlamaModel(TextModel): model_arch = gguf.MODEL_ARCH.LLAMA @@ -2041,7 +2088,64 @@ class LlamaModel(TextModel): if self.hf_arch == "VLlama3ForCausalLM": self.hparams["num_attention_heads"] = self.hparams.get("num_attention_heads", 32) + def _set_vocab_mistral(self): + vocab = MistralVocab(self.dir_model) + logger.info( + f"Converting tokenizer {vocab.tokenizer_type} of size {vocab.vocab_size}." + ) + + self.gguf_writer.add_tokenizer_model(vocab.gguf_tokenizer_model) + + tokens = [] + scores = [] + toktypes = [] + + for text, score, toktype in vocab.all_tokens(): + tokens.append(text) + scores.append(score) + toktypes.append(toktype) + + assert len(tokens) == vocab.vocab_size, ( + f"token count ({len(tokens)}) != vocab size ({vocab.vocab_size})" + ) + + if vocab.tokenizer_type == MistralTokenizerType.tekken: + self.gguf_writer.add_tokenizer_pre("tekken") + self.gguf_writer.add_token_merges( + vocab.extract_vocab_merges_from_model() + ) + + logger.info( + f"Setting bos, eos, unk and pad token IDs to {vocab.bos_id}, {vocab.eos_id}, {vocab.unk_id}, {vocab.pad_id}." + ) + + self.gguf_writer.add_bos_token_id(vocab.bos_id) + self.gguf_writer.add_eos_token_id(vocab.eos_id) + self.gguf_writer.add_unk_token_id(vocab.unk_id) + self.gguf_writer.add_pad_token_id(vocab.pad_id) + + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_scores(scores) + self.gguf_writer.add_token_types(toktypes) + self.gguf_writer.add_vocab_size(vocab.vocab_size) + + self.gguf_writer.add_add_bos_token(True) + self.gguf_writer.add_add_eos_token(False) + + template_dir = Path(__file__).parent / "models/templates/" + + template = MistralModel.get_community_chat_template(vocab, template_dir) + self.gguf_writer.add_chat_template(template) + def set_vocab(self): + if self.is_mistral_format: + return self._set_vocab_mistral() + + path_tekken_json = self.dir_model / "tekken.json" + path_tokenizer_json = self.dir_model / "tokenizer.json" + if path_tekken_json.is_file() and not path_tokenizer_json.is_file(): + self._set_vocab_mistral() + try: self._set_vocab_sentencepiece() except FileNotFoundError: @@ -2077,7 +2181,9 @@ class LlamaModel(TextModel): def set_gguf_parameters(self): super().set_gguf_parameters() hparams = self.hparams - self.gguf_writer.add_vocab_size(hparams["vocab_size"]) + + if not self.is_mistral_format: + self.gguf_writer.add_vocab_size(hparams["vocab_size"]) if (rope_dim := hparams.get("head_dim")) is None: rope_dim = hparams["hidden_size"] // hparams["num_attention_heads"] @@ -2099,14 +2205,27 @@ class LlamaModel(TextModel): _experts: list[dict[str, Tensor]] | None = None def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: - n_head = self.hparams["num_attention_heads"] - n_kv_head = self.hparams.get("num_key_value_heads") - is_vision_tensor = "vision_tower" in name \ - or "vision_model" in name \ - or "model.connector" in name \ - or "multi_modal_projector" in name + n_head = self.find_hparam(["n_heads", "num_attention_heads"]) + n_kv_head = self.find_hparam(["n_kv_heads", "num_key_value_heads"]) - if is_vision_tensor: + vision_prefixes = [ + "vision_encoder.", + "vision_language_adapter.", + "patch_merger.", + "pre_mm_projector_norm", + ] + + is_multimodal_tensor = "vision_tower" in name \ + or "vision_model" in name \ + or "audio_tower" in name \ + or "model.connector" in name \ + or "multi_modal_projector" in name \ + or any( + name.startswith(prefix) + for prefix in vision_prefixes + ) + + if is_multimodal_tensor: return [] # skip vision tensors elif self.hf_arch == "LlamaModel": name = "model." + name @@ -2220,13 +2339,18 @@ class LlavaVisionModel(MmprojModel): def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) - if self.hparams["model_type"] == "pixtral": + if self.hparams.get("model_type") == "pixtral": # layer_norm_eps is not in config.json, it is hard-coded in modeling_pixtral.py self.hparams["layer_norm_eps"] = self.hparams.get("layer_norm_eps", 1e-5) self.img_break_tok_id = self.get_token_id("[IMG_BREAK]") - logger.info(f"Image break token id: {self.img_break_tok_id}") + elif self.is_mistral_format: + # hparams is already vision config here so norm_eps is only defined in global_config. + self.hparams["norm_eps"] = self.global_config.get("norm_eps", None) + assert self.hparams["norm_eps"] is not None, "norm_eps not found in params.json" + self.img_break_tok_id = self.find_vparam(["image_break_token_id"]) else: raise ValueError(f"Unsupported model type: {self.hparams['model_type']}") + logger.info(f"Image break token id: {self.img_break_tok_id}") def get_token_id(self, token: str) -> int: tokenizer_config_file = self.dir_model / 'tokenizer_config.json' @@ -2240,7 +2364,7 @@ class LlavaVisionModel(MmprojModel): def set_gguf_parameters(self): super().set_gguf_parameters() hparams = self.hparams - if hparams["model_type"] == "pixtral": + if hparams.get("model_type") == "pixtral": self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.PIXTRAL) self.gguf_writer.add_vision_attention_layernorm_eps(hparams["layer_norm_eps"]) @@ -2258,18 +2382,30 @@ class LlavaVisionModel(MmprojModel): def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: del bid # unused - n_head = self.hparams["num_attention_heads"] + n_head = ( + self.hparams["num_attention_heads"] if not self.is_mistral_format else self.find_vparam(["num_attention_heads"]) + ) n_kv_head = n_head - if name.startswith("multi_modal_projector.") or name.startswith("vision_tower."): + valid_prefixes = ( + "multi_modal_projector.", + "vision_tower.", + "vision_encoder.", + "vision_language_adapter.", + "patch_merger.", + "pre_mm_projector_norm", + ) + + if any(name.startswith(prefix) for prefix in valid_prefixes): # process vision tensors - if name.endswith(("q_proj.weight", "q_proj.bias")): + if name.endswith(("q_proj.weight", "q_proj.bias")) and not self.is_mistral_format: data_torch = LlamaModel.permute(data_torch, n_head, n_head) - if name.endswith(("k_proj.weight", "k_proj.bias")): + if name.endswith(("k_proj.weight", "k_proj.bias")) and not self.is_mistral_format: data_torch = LlamaModel.permute(data_torch, n_head, n_kv_head) return [(self.map_tensor_name(name), data_torch)] - if self.img_break_tok_id > 0 and "embed_tokens.weight" in name: + embed_key = "embed_tokens.weight" if not self.is_mistral_format else "tok_embeddings.weight" + if self.img_break_tok_id > 0 and embed_key in name: logger.info(f"Extracting [IMG_BREAK] token embedding from {name}") # for pixtral model, we need to extract the [IMG_BREAK] token embedding img_break_embd = data_torch[self.img_break_tok_id] @@ -2981,6 +3117,107 @@ class DreamModel(TextModel): yield from super().modify_tensors(data_torch, name, bid) +@ModelBase.register("LLaDAModelLM") +class LLaDAModel(TextModel): + model_arch = gguf.MODEL_ARCH.LLADA + undo_permute = True + + def get_vocab_base(self) -> tuple[list[str], list[int], str]: + tokens: list[str] = [] + toktypes: list[int] = [] + + from transformers import AutoTokenizer + tokenizer = AutoTokenizer.from_pretrained(self.dir_model, trust_remote_code=True) + + vocab_dict = tokenizer.get_vocab() + vocab_size = self.hparams.get("vocab_size", len(vocab_dict)) + assert max(vocab_dict.values()) < vocab_size + + tokpre = self.get_vocab_base_pre(tokenizer) + + reverse_vocab = {id_: encoded_tok for encoded_tok, id_ in vocab_dict.items()} + added_vocab = tokenizer.get_added_vocab() + + for i in range(vocab_size): + if i not in reverse_vocab: + tokens.append(f"[PAD{i}]") + toktypes.append(gguf.TokenType.UNUSED) + elif reverse_vocab[i] in added_vocab: + tokens.append(reverse_vocab[i]) + # Check if it's a special token - treat special tokens as CONTROL tokens + if hasattr(tokenizer, 'added_tokens_decoder') and i in tokenizer.added_tokens_decoder: + if tokenizer.added_tokens_decoder[i].special: + toktypes.append(gguf.TokenType.CONTROL) + else: + toktypes.append(gguf.TokenType.USER_DEFINED) + else: + # Fallback: treat all added vocab as control tokens for special tokens like <|im_start|> + toktypes.append(gguf.TokenType.CONTROL) + else: + tokens.append(reverse_vocab[i]) + toktypes.append(gguf.TokenType.NORMAL) + + return tokens, toktypes, tokpre + + def set_vocab(self): + self._set_vocab_gpt2() + + # LLaDA specific parameters + self.gguf_writer.add_add_bos_token(True) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self._try_set_pooling_type() + + # Add parameters similar to LlamaModel + hparams = self.hparams + self.gguf_writer.add_vocab_size(hparams["vocab_size"]) + + if (rope_dim := hparams.get("head_dim")) is None: + n_heads = hparams.get("num_attention_heads", hparams.get("n_heads")) + rope_dim = hparams.get("hidden_size", hparams.get("d_model")) // n_heads + self.gguf_writer.add_rope_dimension_count(rope_dim) + + # Set context length for LLaDA + context_length = self.hparams.get("max_sequence_length", 4096) + self.gguf_writer.add_context_length(context_length) + + # Set embedding length (dimension size) + embedding_length = self.hparams.get("d_model", 4096) + self.gguf_writer.add_embedding_length(embedding_length) + + # Set feed forward length (MLP hidden size) + feed_forward_length = self.hparams.get("mlp_hidden_size", 12288) + self.gguf_writer.add_feed_forward_length(feed_forward_length) + + # LLaDA models use non-causal attention for diffusion, similar to Dream + self.gguf_writer.add_causal_attention(False) + + # LLaDA models don't shift their logits + self.gguf_writer.add_diffusion_shift_logits(False) + + @staticmethod + def permute(weights: Tensor, n_head: int, n_head_kv: int | None): + if n_head_kv is not None and n_head != n_head_kv: + n_head = n_head_kv + return (weights.reshape(n_head, 2, weights.shape[0] // n_head // 2, *weights.shape[1:]) + .swapaxes(1, 2) + .reshape(weights.shape)) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + n_head = self.hparams.get("num_attention_heads", self.hparams.get("n_heads")) + n_kv_head = self.hparams.get("num_key_value_heads", self.hparams.get("n_kv_heads")) + + if self.undo_permute: + if name.endswith(("q_proj.weight", "q_proj.bias")): + data_torch = LLaDAModel.permute(data_torch, n_head, n_head) + if name.endswith(("k_proj.weight", "k_proj.bias")): + data_torch = LLaDAModel.permute(data_torch, n_head, n_kv_head) + + # LLaDA model tensors should be mapped directly since it's the base model + yield from super().modify_tensors(data_torch, name, bid) + + @ModelBase.register("Ernie4_5_ForCausalLM") class Ernie4_5Model(TextModel): model_arch = gguf.MODEL_ARCH.ERNIE4_5 @@ -3292,7 +3529,13 @@ class Qwen25OmniModel(Qwen2VLVisionModel): @ModelBase.register("InternVisionModel") class InternVisionModel(MmprojModel): def set_gguf_parameters(self): + assert self.hparams_vision is not None + if isinstance(self.hparams_vision['image_size'], list): + self.hparams_vision['image_size'] = self.hparams_vision['image_size'][0] + if isinstance(self.hparams_vision['patch_size'], list): + self.hparams_vision['patch_size'] = self.hparams_vision['patch_size'][0] super().set_gguf_parameters() + hparams = self.hparams self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.INTERNVL) self.gguf_writer.add_vision_attention_layernorm_eps(hparams["layer_norm_eps"]) @@ -3316,14 +3559,30 @@ class InternVisionModel(MmprojModel): return gguf.GGMLQuantizationType.F32 return False + def _mapping_interns1_name(self, name): + names_map = { + "model.multi_modal_projector.layer_norm.bias": "mlp1.0.bias", + "model.multi_modal_projector.layer_norm.weight": "mlp1.0.weight", + "model.multi_modal_projector.linear_1.bias": "mlp1.1.bias", + "model.multi_modal_projector.linear_1.weight": "mlp1.1.weight", + "model.multi_modal_projector.linear_2.bias": "mlp1.3.bias", + "model.multi_modal_projector.linear_2.weight": "mlp1.3.weight", + } + if name in names_map: + name = names_map[name] + return name + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: del bid # unused - if name.startswith("vision_model") or name.startswith("mlp"): + vision_prefix = ['vision_model', 'mlp', 'model.vision_tower', 'model.multi_modal_projector'] + # deal with intern-s1 special case + name = self._mapping_interns1_name(name) + if any([name.startswith(prefix) for prefix in vision_prefix]): # process visual tensors # correct name if name.startswith("vision_model"): name = "vision_tower." + name - if (".ls" in name or "position_embedding" in name) and not name.endswith(".weight"): + if (".ls" in name or ".lambda_" in name or "position_embedding" in name) and not name.endswith(".weight"): name += ".weight" # split QKV tensors if needed if ".qkv." in name: @@ -3409,6 +3668,10 @@ class Qwen2MoeModel(TextModel): def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: # process the experts separately + name = name.replace("language_model.", "") # InternVL + if name.startswith("mlp") or name.startswith("vision_model") or name.startswith("model.vision_tower") or name.startswith("model.multi_modal_projector"): + # skip visual tensors + return [] if name.find("experts") != -1: n_experts = self.hparams["num_experts"] assert bid is not None @@ -3462,6 +3725,85 @@ class Qwen3Model(Qwen2Model): class Qwen3MoeModel(Qwen2MoeModel): model_arch = gguf.MODEL_ARCH.QWEN3MOE + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + hparams = ModelBase.load_hparams(self.dir_model, False) + self.origin_hf_arch = hparams.get('architectures', [None])[0] + + def set_vocab(self): + # deal with intern-s1 + if self.origin_hf_arch == 'InternS1ForConditionalGeneration': + self._set_vocab_interns1() + return + + try: + self._set_vocab_sentencepiece() + except FileNotFoundError: + self._set_vocab_gpt2() + + def _set_vocab_interns1(self): + tokens: list[str] = [] + toktypes: list[int] = [] + + from transformers import AutoTokenizer + tokenizer = AutoTokenizer.from_pretrained(self.dir_model, trust_remote_code=True) + vocab = getattr(tokenizer, 'vocab', tokenizer.get_vocab()) + vocab_size = self.hparams.get("vocab_size", len(vocab)) + assert max(vocab.values()) < vocab_size + + tokpre = self.get_vocab_base_pre(tokenizer) + + reverse_vocab = {id_: encoded_tok for encoded_tok, id_ in vocab.items()} + added_vocab = tokenizer.get_added_vocab() + + added_tokens_decoder = tokenizer.added_tokens_decoder + + for i in range(vocab_size): + if i not in reverse_vocab: + tokens.append(f"[PAD{i}]") + toktypes.append(gguf.TokenType.UNUSED) + else: + token: str = reverse_vocab[i] + if token in added_vocab: + # The tokenizer in llama.cpp assumes the CONTROL and USER_DEFINED tokens are pre-normalized. + # To avoid unexpected issues - we make sure to normalize non-normalized tokens + if not added_tokens_decoder[i].normalized: + previous_token = token + token = tokenizer.decode(tokenizer.encode(token, add_special_tokens=False)) + if previous_token != token: + logger.info(f"{repr(previous_token)} is encoded and decoded back to {repr(token)} using AutoTokenizer") + + if added_tokens_decoder[i].special or self.does_token_look_special(token): + toktypes.append(gguf.TokenType.CONTROL) + else: + toktypes.append(gguf.TokenType.USER_DEFINED) + else: + toktypes.append(gguf.TokenType.NORMAL) + tokens.append(token) + + self.gguf_writer.add_tokenizer_model("gpt2") + self.gguf_writer.add_tokenizer_pre(tokpre) + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_types(toktypes) + + special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=True) + special_tokens_map_file = self.dir_model / 'special_tokens_map.json' + additional_special_tokens = [] + if special_tokens_map_file.is_file(): + with open(special_tokens_map_file, encoding = 'utf-8') as f: + additional_special_tokens = json.load(f).get('additional_special_tokens', []) + tokenizer_cfg_file = self.dir_model / 'special_tokens_map.json' + if tokenizer_cfg_file.is_file(): + with open(tokenizer_cfg_file, encoding = 'utf-8') as f: + added_tokens_decoder = json.load(f).get('added_tokens_decoder', {}) + token2ids_map = {data['content'] : int(token) for token, data in added_tokens_decoder.items() if data['special']} + for token in additional_special_tokens: + if token in token2ids_map: + special_vocab._set_special_token(token, token2ids_map[token]) + special_vocab._set_special_token('eos', 151645) + special_vocab._set_special_token("bos", 151643) + special_vocab.add_to_gguf(self.gguf_writer) + @ModelBase.register("GPT2LMHeadModel") class GPT2Model(TextModel): @@ -3921,7 +4263,7 @@ class Plamo2Model(TextModel): self.gguf_writer.add_block_count(block_count) self.gguf_writer.add_head_count(hparams.get("num_attention_heads", 32)) self.gguf_writer.add_layer_norm_rms_eps(hparams.get("rms_norm_eps", 1e-06)) - self.gguf_writer.add_rope_freq_base(hparams.get("rope_theta", 1000000.0)) + self.gguf_writer.add_rope_freq_base(hparams.get("rope_theta", 10000)) # Mamba parameters self.gguf_writer.add_ssm_state_size(hparams.get("mamba_d_state", 64)) @@ -3932,7 +4274,7 @@ class Plamo2Model(TextModel): self.gguf_writer.add_ssm_group_count(0) # MLP feed forward parameters (for attention layers) - self.gguf_writer.add_feed_forward_length(hparams.get("intermediate_size", 16384)) + self.gguf_writer.add_feed_forward_length(hparams.get("intermediate_size", 13312)) self.gguf_writer.add_file_type(self.ftype) def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: @@ -4521,7 +4863,7 @@ class NomicBertModel(BertModel): def __init__(self, dir_model: Path, ftype: gguf.LlamaFileType, fname_out: Path, **kwargs: Any): hparams = kwargs.pop("hparams", None) if hparams is None: - hparams = ModelBase.load_hparams(dir_model) + hparams = ModelBase.load_hparams(dir_model, False) self.is_moe = bool(hparams.get("moe_every_n_layers")) self.model_arch = gguf.MODEL_ARCH.NOMIC_BERT_MOE if self.is_moe else gguf.MODEL_ARCH.NOMIC_BERT @@ -6008,6 +6350,7 @@ class DeepseekModel(TextModel): @ModelBase.register("DeepseekV2ForCausalLM") @ModelBase.register("DeepseekV3ForCausalLM") +@ModelBase.register("KimiVLForConditionalGeneration") class DeepseekV2Model(TextModel): model_arch = gguf.MODEL_ARCH.DEEPSEEK2 @@ -6110,6 +6453,13 @@ class DeepseekV2Model(TextModel): _experts: list[dict[str, Tensor]] | None = None def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + # skip vision tensors and remove "language_model." for Kimi-VL + if "vision_tower" in name or "multi_modal_projector" in name: + return [] + + if name.startswith("language_model."): + name = name.replace("language_model.", "") + # rename e_score_correction_bias tensors if name.endswith("e_score_correction_bias"): name = name.replace("e_score_correction_bias", "e_score_correction.bias") @@ -6595,7 +6945,7 @@ class JaisModel(TextModel): self.gguf_writer.add_max_alibi_bias(self.max_alibi_bias) -@ModelBase.register("Glm4ForCausalLM") +@ModelBase.register("Glm4ForCausalLM", "Glm4vForConditionalGeneration") class Glm4Model(TextModel): model_arch = gguf.MODEL_ARCH.GLM4 @@ -6617,7 +6967,8 @@ class Glm4Model(TextModel): def set_gguf_parameters(self): super().set_gguf_parameters() - rope_dim = self.hparams["head_dim"] + if (rope_dim := self.hparams.get("head_dim")) is None: + rope_dim = self.hparams["hidden_size"] // self.hparams["num_attention_heads"] self.gguf_writer.add_rope_dimension_count(int(rope_dim * self.hparams.get("partial_rotary_factor", 0.5))) rope_scaling = self.hparams.get("rope_scaling") or {} if rope_scaling.get("rope_type", rope_scaling.get("type")) == "yarn" and "factor" in rope_scaling: @@ -6625,6 +6976,146 @@ class Glm4Model(TextModel): self.gguf_writer.add_rope_scaling_factor(rope_scaling["factor"]) self.gguf_writer.add_rope_scaling_orig_ctx_len(rope_scaling["original_max_position_embeddings"]) + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.startswith("model.visual."): # ignore visual part of Glm4v + return [] + elif name.startswith("model.language_model."): + name = name.replace("language_model.", "") # for Glm4v + return super().modify_tensors(data_torch, name, bid) + + +@ModelBase.register("Glm4MoeForCausalLM") +class Glm4MoeModel(TextModel): + model_arch = gguf.MODEL_ARCH.GLM4_MOE + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + # GLM4_MOE has num_hidden_layers + 1 actual layers (including NextN layer) + self.block_count = self.hparams["num_hidden_layers"] + self.hparams.get("num_nextn_predict_layers", 0) + self.tensor_map = gguf.get_tensor_name_map(self.model_arch, self.block_count) + + def set_vocab(self): + from transformers import AutoTokenizer + + tokenizer = AutoTokenizer.from_pretrained(self.dir_model) + special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=True) + tokens, toktypes, tokpre = self.get_vocab_base() + self.gguf_writer.add_tokenizer_model("gpt2") + self.gguf_writer.add_tokenizer_pre(tokpre) + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_types(toktypes) + + # Special tokens + # Note: Using <|endoftext|> (151329) for eot causes endless generation + special_vocab._set_special_token("bos", tokenizer.get_added_vocab()["[gMASK]"]) # 151331 + special_vocab._set_special_token("eot", tokenizer.get_added_vocab()["<|user|>"]) # 151336 + special_vocab._set_special_token("unk", tokenizer.get_added_vocab()["<|endoftext|>"]) # 151329 + special_vocab._set_special_token("eom", tokenizer.get_added_vocab()["<|observation|>"]) # 151338 + + # Patch broken chat template + if isinstance(special_vocab.chat_template, str) and "visible_text(m.content).endswith" in special_vocab.chat_template: + special_vocab.chat_template = special_vocab.chat_template.replace( + """{{ visible_text(m.content) }}\n{{- '/nothink' if (enable_thinking is defined and not enable_thinking and not visible_text(m.content).endswith("/nothink")) else '' -}}""", + """{% set content = visible_text(m.content) %}{{ content }}\n{{- '/nothink' if (enable_thinking is defined and not enable_thinking and not content.endswith("/nothink")) else '' -}}""") + + special_vocab.add_to_gguf(self.gguf_writer) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + if (rope_dim := self.hparams.get("head_dim")) is None: + rope_dim = ( + self.hparams["hidden_size"] // self.hparams["num_attention_heads"] + ) + self.gguf_writer.add_rope_dimension_count( + int(rope_dim * self.hparams.get("partial_rotary_factor", 0.5)) + ) + + # MoE parameters - Use only routed expert count (shared experts handled separately) + if (n_routed_experts := self.hparams.get("n_routed_experts")) is not None: + self.gguf_writer.add_expert_count(n_routed_experts) + if (moe_intermediate_size := self.hparams.get("moe_intermediate_size")) is not None: + self.gguf_writer.add_expert_feed_forward_length(moe_intermediate_size) + if (n_shared_experts := self.hparams.get("n_shared_experts")) is not None: + self.gguf_writer.add_expert_shared_count(n_shared_experts) + if (first_k_dense_replace := self.hparams.get("first_k_dense_replace")) is not None: + self.gguf_writer.add_leading_dense_block_count(first_k_dense_replace) + + # Expert gating function (sigmoid for GLM4_MOE) + self.gguf_writer.add_expert_gating_func(gguf.ExpertGatingFuncType.SIGMOID) + + # Routed scaling factor + if (routed_scaling_factor := self.hparams.get("routed_scaling_factor")) is not None: + self.gguf_writer.add_expert_weights_scale(routed_scaling_factor) + + # Normalise topk probabilities + if (norm_topk_prob := self.hparams.get("norm_topk_prob")) is not None: + self.gguf_writer.add_expert_weights_norm(norm_topk_prob) + + # NextN/MTP prediction layers + if (num_nextn_predict_layers := self.hparams.get("num_nextn_predict_layers")) is not None: + self.gguf_writer.add_nextn_predict_layers(num_nextn_predict_layers) + + _experts: list[dict[str, Tensor]] | None = None + + def modify_tensors( + self, data_torch: Tensor, name: str, bid: int | None + ) -> Iterable[tuple[str, Tensor]]: + if name.startswith("model.visual."): # ignore visual part + return [] + elif name.startswith("model.language_model."): + name = name.replace("language_model.", "") # for multimodal variants + + # Handle main token embedding (but not layer-specific NextN embeddings) + if name == "model.embed_tokens.weight" and ".layers." not in name: + return [(self.map_tensor_name("token_embd.weight"), data_torch)] + + # Handle routed experts + if name.find("mlp.experts") != -1: + n_experts = self.hparams["n_routed_experts"] + assert bid is not None + + if self._experts is None: + self._experts = [{} for _ in range(self.block_count)] + + self._experts[bid][name] = data_torch + + if len(self._experts[bid]) >= n_experts * 3: + tensors: list[tuple[str, Tensor]] = [] + + # merge the experts into a single 3d tensor + for w_name in ["down_proj", "gate_proj", "up_proj"]: + datas: list[Tensor] = [] + + for xid in range(n_experts): + ename = f"model.layers.{bid}.mlp.experts.{xid}.{w_name}.weight" + datas.append(self._experts[bid][ename]) + del self._experts[bid][ename] + + data_torch = torch.stack(datas, dim=0) + + merged_name = f"model.layers.{bid}.mlp.experts.{w_name}.weight" + + new_name = self.map_tensor_name(merged_name) + tensors.append((new_name, data_torch)) + return tensors + else: + return [] + + if name.endswith("e_score_correction_bias"): + name = name.replace("e_score_correction_bias", "e_score_correction.bias") + + new_name = self.map_tensor_name(name) + + return [(new_name, data_torch)] + + def prepare_tensors(self): + super().prepare_tensors() + if self._experts is not None: + # flatten `list[dict[str, Tensor]]` into `list[str]` + experts = [k for d in self._experts for k in d.keys()] + if len(experts) > 0: + raise ValueError(f"Unprocessed experts: {experts}") + @ModelBase.register("GlmForCausalLM", "ChatGLMModel", "ChatGLMForConditionalGeneration") class ChatGLMModel(TextModel): @@ -7332,9 +7823,10 @@ class WhisperEncoderModel(MmprojModel): def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) - self.hparams["hidden_size"] = self.hparams["d_model"] - self.hparams["intermediate_size"] = self.hparams["encoder_ffn_dim"] - self.hparams["num_attention_heads"] = self.hparams["encoder_attention_heads"] + if "hidden_size" not in self.hparams and "intermediate_size" not in self.hparams: + self.hparams["hidden_size"] = self.hparams["d_model"] + self.hparams["intermediate_size"] = self.hparams["encoder_ffn_dim"] + self.hparams["num_attention_heads"] = self.hparams["encoder_attention_heads"] def set_gguf_parameters(self): super().set_gguf_parameters() @@ -7373,9 +7865,21 @@ class UltravoxWhisperEncoderModel(WhisperEncoderModel): def set_gguf_parameters(self): super().set_gguf_parameters() + self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.ULTRAVOX) self.gguf_writer.add_audio_stack_factor(self.global_config["stack_factor"]) +@ModelBase.register("VoxtralForConditionalGeneration") +class VoxtralWhisperEncoderModel(WhisperEncoderModel): + has_vision_encoder = False # no vision encoder + has_audio_encoder = True + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.VOXTRAL) + self.gguf_writer.add_audio_stack_factor(4) # == intermediate_size // hidden_size + + @ModelBase.register("FalconH1ForCausalLM") class FalconH1Model(Mamba2Model): model_arch = gguf.MODEL_ARCH.FALCON_H1 @@ -7487,11 +7991,6 @@ class FalconH1Model(Mamba2Model): class HunYuanMoEModel(TextModel): model_arch = gguf.MODEL_ARCH.HUNYUAN_MOE - def __init__(self, *args, **kwargs): - super().__init__(*args, **kwargs) - # For handling tied embeddings - self._tok_embd = None - def set_vocab(self): from transformers import AutoTokenizer tokenizer = AutoTokenizer.from_pretrained(self.dir_model, trust_remote_code=True) @@ -7585,9 +8084,6 @@ class HunYuanMoEModel(TextModel): _experts: list[dict[str, Tensor]] | None = None def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: - if name == "model.embed_tokens.weight": - self._tok_embd = data_torch.clone() - if name == "lm_head.weight": if self.hparams.get("tie_word_embeddings", False): logger.info("Skipping tied output layer 'lm_head.weight'") @@ -7632,6 +8128,98 @@ class HunYuanMoEModel(TextModel): raise ValueError(f"Unprocessed experts: {experts}") +@ModelBase.register("HunYuanDenseV1ForCausalLM") +class HunYuanModel(TextModel): + model_arch = gguf.MODEL_ARCH.HUNYUAN_DENSE + + def set_vocab(self): + if (self.dir_model / "tokenizer.json").is_file(): + self._set_vocab_gpt2() + else: + from transformers import AutoTokenizer + tokenizer = AutoTokenizer.from_pretrained(self.dir_model, trust_remote_code=True) + + # 1. Get the pre-tokenizer identifier hash + tokpre = self.get_vocab_base_pre(tokenizer) + + # 2. Reverse-engineer the merges list from mergeable_ranks + merges = [] + vocab = {} + mergeable_ranks = tokenizer.mergeable_ranks + for token, rank in mergeable_ranks.items(): + vocab[QwenModel.token_bytes_to_string(token)] = rank + if len(token) == 1: + continue + merged = QwenModel.bpe(mergeable_ranks, token, max_rank=rank) + if len(merged) == 2: + merges.append(' '.join(map(QwenModel.token_bytes_to_string, merged))) + + # 3. Generate the tokens and toktypes lists + vocab_size = self.hparams["vocab_size"] + assert tokenizer.vocab_size == vocab_size + special_tokens = tokenizer.special_tokens + reverse_vocab = {id_ : encoded_tok for encoded_tok, id_ in {**vocab, **special_tokens}.items()} + tokens: list[str] = [] + toktypes: list[int] = [] + for i in range(vocab_size): + if i not in reverse_vocab: + tokens.append(f"[PAD{i}]") + toktypes.append(gguf.TokenType.UNUSED) + else: + token = reverse_vocab[i] + tokens.append(token) + if i in special_tokens.values(): + toktypes.append(gguf.TokenType.CONTROL) + else: + toktypes.append(gguf.TokenType.NORMAL) + + # 4. Write all vocab-related fields to the GGUF writer + self.gguf_writer.add_tokenizer_model("gpt2") + self.gguf_writer.add_tokenizer_pre(tokpre) + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_types(toktypes) + self.gguf_writer.add_token_merges(merges) + + # 5. Add special tokens and chat templates + special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=False) + special_vocab.add_to_gguf(self.gguf_writer) + # FIX for BOS token: Overwrite incorrect id read from config.json + if self.hparams['hidden_size'] == 4096: + self.gguf_writer.add_bos_token_id(127958) # only for 7b dense, fix <|bos|> token + + def set_gguf_parameters(self): + super().set_gguf_parameters() + hparams = self.hparams + + # Rope + rope_scaling = hparams.get("rope_scaling", {}) + if rope_scaling.get("type") == "dynamic": + # HunYuan uses NTK Aware Alpha based scaling. Original implementation: https://www.reddit.com/r/LocalLLaMA/comments/14lz7j5/ntkaware_scaled_rope_allows_llama_models_to_have/ + # 1000 corresponds to a usable context length of 256k (https://github.com/Tencent-Hunyuan/Hunyuan-A13B/blob/main/report/Hunyuan_A13B_Technical_Report.pdf) + alpha = rope_scaling.get("alpha", 50) + base = hparams.get("rope_theta", 10000.0) + dim = hparams["head_dim"] + scaled_base = base * (alpha ** (dim / (dim - 2))) + self.gguf_writer.add_rope_freq_base(scaled_base) + self.gguf_writer.add_rope_scaling_type(gguf.RopeScalingType.NONE) + self.gguf_writer.add_rope_scaling_factor(1) + # There is no consistent way to calculate ctx from alpha, and the config is incorrectly set to 32k + self.gguf_writer.add_rope_scaling_orig_ctx_len(256 * 1024) # 256k context length + self.gguf_writer.add_context_length(256 * 1024) # 256k context length + + # if any of our assumptions about the values are wrong, something has changed and this may need to be updated + assert base == 10000.0 and self.hparams["max_position_embeddings"] in [32 * 1024, 256 * 1024] , \ + "HunYuan dynamic RoPE scaling assumptions changed, please update the logic or context length manually" + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name == "lm_head.weight": + if self.hparams.get("tie_word_embeddings", False): + logger.info("Skipping tied output layer 'lm_head.weight'") + return [] + + return [(self.map_tensor_name(name), data_torch)] + + @ModelBase.register("SmolLM3ForCausalLM") class SmolLM3Model(LlamaModel): model_arch = gguf.MODEL_ARCH.SMOLLM3 @@ -7647,6 +8235,130 @@ class SmolLM3Model(LlamaModel): self.gguf_writer.add_chat_template(chat_template) +@ModelBase.register("GptOssForCausalLM") +class GptOssModel(TextModel): + model_arch = gguf.MODEL_ARCH.GPT_OSS + + def transform_nibble_layout(self, tensor): + assert tensor.dtype == torch.uint8 + assert tensor.shape[-1] == 16 + # swap nibbles + t_lo = tensor & 0x0F + t_hi = tensor & 0xF0 + t_swapped = (t_lo << 4) | (t_hi >> 4) + tensor = t_swapped + # transform aaaa...bbbb... to abababab... + blk_a, blk_b = tensor.chunk(2, dim=-1) + # get a_ + blk_a0 = (blk_a & 0xF0).view(-1, 1) + blk_a1 = (blk_a << 4).view(-1, 1) + blk_a = torch.stack((blk_a0, blk_a1), dim=2).view(tensor.shape) + # get _b + blk_b0 = (blk_b >> 4).view(-1, 1) + blk_b1 = (blk_b & 0x0F).view(-1, 1) + blk_b = torch.stack((blk_b0, blk_b1), dim=2).view(tensor.shape) + # swap once more + out = blk_a | blk_b + out_h = out & 0xF0 + out_l = out & 0x0F + out = (out_h >> 4) | (out_l << 4) + return out + + def repack_mxfp4(self, new_name: str, blocks: Tensor, scales: Tensor): + assert blocks.dtype == torch.uint8 + assert scales.dtype == torch.uint8 + scales = scales.unsqueeze(-1) + assert len(blocks.shape) == 4 + assert len(scales.shape) == 4 + blocks = self.transform_nibble_layout(blocks) + new_data = torch.concat((scales, blocks), dim=-1) + new_shape = [new_data.shape[0], new_data.shape[1], new_data.shape[2] * 32] + logger.info(f"Repacked {new_name} with shape {new_shape} and quantization MXFP4") + # flatten last dim + new_data = new_data.view(new_data.shape[0], new_data.shape[1], new_data.shape[2] * new_data.shape[3]) + new_data = new_data.numpy() + self.gguf_writer.add_tensor(new_name, new_data, raw_dtype=gguf.GGMLQuantizationType.MXFP4) + + def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: + blocks0: Tensor = torch.zeros(1) + blocks1: Tensor = torch.zeros(1) + # we assume that tensors are loaded in the correct order + for name, data_torch in self.get_tensors(): + if "mlp.experts.down_proj_blocks" in name: + blocks0 = data_torch + elif "mlp.experts.down_proj_scales" in name: + new_name = self.map_tensor_name(name.replace("_scales", ".weight")) + self.repack_mxfp4(new_name, blocks0, data_torch) + elif "mlp.experts.gate_up_proj_blocks" in name: + blocks0, blocks1 = data_torch[:, ::2, :, :], data_torch[:, 1::2, :, :] + elif "mlp.experts.gate_up_proj_scales" in name: + scales0, scales1 = data_torch[:, ::2, :], data_torch[:, 1::2, :] + new_name_gate = self.map_tensor_name(name.replace("gate_up_proj_scales", "gate_proj.weight")) + new_name_up = self.map_tensor_name(name.replace("gate_up_proj_scales", "up_proj.weight")) + self.repack_mxfp4(new_name_gate, blocks0, scales0) + self.repack_mxfp4(new_name_up, blocks1, scales1) + return [] + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + del bid # unused + + if "sinks" in name: + name += ".weight" + + # correct naming for down_proj + if "down_proj" in name: + if name.endswith("_bias"): + name = name.replace("down_proj_bias", "down_proj.bias") + elif "_blocks" not in name and "_scales" not in name: + logger.warning(f"{name} is not in MXFP4, performance may be degraded") + name = name.replace("down_proj", "down_proj.weight") + data_torch = data_torch.transpose(-1, -2) + else: + # otherwise, it should already be repacked to ggml MXFP4 format + return [] + + # split the gate_up into gate and up + if "gate_up_proj" in name: + if name.endswith("_bias"): + name_up = name.replace("gate_up_proj_bias", "up_proj.bias") + name_gate = name.replace("gate_up_proj_bias", "gate_proj.bias") + gate_proj_bias, up_proj_bias = data_torch[..., ::2], data_torch[..., 1::2] + return [ + (self.map_tensor_name(name_gate), gate_proj_bias), + (self.map_tensor_name(name_up), up_proj_bias) + ] + elif "_blocks" not in name and "_scales" not in name: + logger.warning(f"{name} is not in MXFP4, performance may be degraded") + name_up = name.replace("gate_up_proj", "up_proj.weight") + name_gate = name.replace("gate_up_proj", "gate_proj.weight") + data_torch = data_torch.transpose(-1, -2) + gate_proj_weight, up_proj_weight = data_torch[:, ::2, :], data_torch[:, 1::2, :] + return [ + (self.map_tensor_name(name_gate), gate_proj_weight), + (self.map_tensor_name(name_up), up_proj_weight) + ] + else: + # otherwise, it should already be repacked to ggml MXFP4 format + return [] + + return [(self.map_tensor_name(name), data_torch)] + + def set_vocab(self): + self._set_vocab_gpt2() + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_sliding_window(self.hparams["sliding_window"]) + self.gguf_writer.add_expert_feed_forward_length(self.hparams["intermediate_size"]) + + rope_scaling = self.hparams.get("rope_scaling") or {} + rope_type = rope_scaling.get("rope_type", rope_scaling.get("type")) + assert rope_type == "yarn", f"GPT-OSS only supports yarn rope scaling, got {rope_type}" + self.gguf_writer.add_rope_scaling_type(gguf.RopeScalingType.YARN) + self.gguf_writer.add_rope_scaling_factor(rope_scaling["factor"]) + self.gguf_writer.add_rope_scaling_orig_ctx_len(rope_scaling.get("original_max_position_embeddings", 4096)) + + @ModelBase.register("Lfm2ForCausalLM") @ModelBase.register("LFM2ForCausalLM") class LFM2Model(TextModel): @@ -7690,6 +8402,159 @@ class LFM2Model(TextModel): return [(self.map_tensor_name(name), data_torch)] +@ModelBase.register("SmallThinkerForCausalLM") +class SmallThinkerModel(TextModel): + model_arch = gguf.MODEL_ARCH.SMALLTHINKER + + def set_gguf_parameters(self): + super().set_gguf_parameters() + if (n_experts := self.hparams.get("num_experts", self.hparams.get("moe_num_primary_experts"))) is not None: + self.gguf_writer.add_expert_count(n_experts) + if (n_experts_used := self.hparams.get("num_experts_per_tok", self.hparams.get("moe_num_active_primary_experts"))) is not None: + self.gguf_writer.add_expert_used_count(n_experts_used) + if (moe_intermediate_size := self.hparams.get("moe_ffn_hidden_size")) is not None: + self.gguf_writer.add_expert_feed_forward_length(moe_intermediate_size) + self.gguf_writer.add_feed_forward_length(moe_intermediate_size) + logger.info(f"gguf: expert feed forward length = {moe_intermediate_size}") + if (self.hparams.get('moe_primary_router_apply_softmax')): + self.gguf_writer.add_expert_gating_func(gguf.ExpertGatingFuncType.SOFTMAX) + else: + self.gguf_writer.add_expert_gating_func(gguf.ExpertGatingFuncType.SIGMOID) + # YaRN is not enabled by default + # To enable it, please refer to this guide: https://huggingface.co/Qwen/Qwen3-30B-A3B#processing-long-texts + rope_scaling = self.hparams.get("rope_scaling") or {} + if rope_scaling.get("rope_type", rope_scaling.get("type")) == "yarn" and "factor" in rope_scaling: + self.gguf_writer.add_rope_scaling_type(gguf.RopeScalingType.YARN) + self.gguf_writer.add_rope_scaling_factor(rope_scaling["factor"]) + self.gguf_writer.add_rope_scaling_orig_ctx_len(rope_scaling["original_max_position_embeddings"]) + + sliding_window_layout = self.hparams.get("sliding_window_layout") + if sliding_window_layout: + for i in sliding_window_layout: + if i != 0: + sliding_window = self.hparams.get("sliding_window_size") + if sliding_window: + self.gguf_writer.add_sliding_window(sliding_window) + break + + _experts: list[dict[str, Tensor]] | None = None + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + # process the experts separately + if name.find("experts") != -1: + n_experts = self.hparams.get("num_experts", self.hparams.get("moe_num_primary_experts")) + assert bid is not None + + if self._experts is None: + self._experts = [{} for _ in range(self.block_count)] + + self._experts[bid][name] = data_torch + + if len(self._experts[bid]) >= n_experts * 3: + tensors: list[tuple[str, Tensor]] = [] + + # merge the experts into a single 3d tensor + for w_name in ["down", "gate", "up"]: + datas: list[Tensor] = [] + + for xid in range(n_experts): + ename = f"model.layers.{bid}.block_sparse_moe.experts.{xid}.{w_name}.weight" + datas.append(self._experts[bid][ename]) + del self._experts[bid][ename] + + data_torch = torch.stack(datas, dim=0) + + merged_name = f"model.layers.{bid}.block_sparse_moe.experts.{w_name}.weight" + + new_name = self.map_tensor_name(merged_name) + + tensors.append((new_name, data_torch)) + return tensors + else: + return [] + + return [(self.map_tensor_name(name), data_torch)] + + def prepare_tensors(self): + super().prepare_tensors() + + if self._experts is not None: + # flatten `list[dict[str, Tensor]]` into `list[str]` + experts = [k for d in self._experts for k in d.keys()] + if len(experts) > 0: + raise ValueError(f"Unprocessed experts: {experts}") + + +class MistralModel(LlamaModel): + model_arch = gguf.MODEL_ARCH.LLAMA + model_name = "Mistral" + hf_arch = "" + is_mistral_format = True + undo_permute = False + + @staticmethod + def get_community_chat_template(vocab: MistralVocab, templates_dir: Path): + assert TokenizerVersion is not None, "mistral_common is not installed" + assert isinstance(vocab.tokenizer, (Tekkenizer, SentencePieceTokenizer)), ( + f"Expected Tekkenizer or SentencePieceTokenizer, got {type(vocab.tokenizer)}" + ) + + if vocab.tokenizer.version == TokenizerVersion.v1: + return "mistral-v1" + elif vocab.tokenizer.version == TokenizerVersion.v3 and vocab.tokenizer_type == MistralTokenizerType.spm: + return "mistral-v3" + elif vocab.tokenizer.version == TokenizerVersion.v3 and vocab.tokenizer_type == MistralTokenizerType.tekken: + return "mistral-v3-tekken" + elif vocab.tokenizer.version == TokenizerVersion.v7 and vocab.tokenizer_type == MistralTokenizerType.spm: + return "mistral-v7" + elif vocab.tokenizer.version == TokenizerVersion.v7 and vocab.tokenizer_type == MistralTokenizerType.tekken: + return "mistral-v7-tekken" + elif vocab.tokenizer.version == TokenizerVersion.v11: + template_file = "Mistral-Small-3.2-24B-Instruct-2506.jinja" + elif vocab.tokenizer.version == TokenizerVersion.v13: + template_file = "unsloth-mistral-Devstral-Small-2507.jinja" + else: + raise ValueError(f"Unknown tokenizer type: {vocab.tokenizer_type} and version {vocab.tokenizer.version}") + + template_path = templates_dir / template_file + if not template_path.exists(): + raise FileNotFoundError(f"Template file not found: {template_path}") + + with open(template_path, "r", encoding="utf-8") as f: + template = f.read() + + return template + + +class PixtralModel(LlavaVisionModel): + model_name = "Pixtral" + hf_arch = "" + is_mistral_format = True + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.PIXTRAL) + + self.gguf_writer.add_vision_attention_layernorm_eps( + self.find_hparam(["norm_eps"]) + ) + self.gguf_writer.add_rope_freq_base(self.find_vparam(["rope_theta"])) + + self.gguf_writer.add_vision_use_silu(True) + + # spatial_merge_size + if self.find_vparam(["mm_projector_id"]) == "patch_merge": + self.gguf_writer.add_vision_spatial_merge_size( + self.find_vparam(["spatial_merge_size"]) + ) + + def map_tensor_name(self, name: str, try_suffixes: Sequence[str] = (".weight", ".bias")) -> str: + if name == "vision_language_adapter.w_in.weight": + return "mm.1.weight" + elif name == "vision_language_adapter.w_out.weight": + return "mm.2.weight" + return super().map_tensor_name(name, try_suffixes) + ###### CONVERSION LOGIC ###### @@ -7704,6 +8569,7 @@ class LazyTorchTensor(gguf.LazyBase): _dtype_map: dict[torch.dtype, type] = { torch.float16: np.float16, torch.float32: np.float32, + torch.uint8: np.uint8, } # used for safetensors slices @@ -7839,6 +8705,10 @@ def parse_args() -> argparse.Namespace: "--mmproj", action="store_true", help="(Experimental) Export multimodal projector (mmproj) for vision models. This will only work on some vision models. A prefix 'mmproj-' will be added to the output file name.", ) + parser.add_argument( + "--mistral-format", action="store_true", + help="Whether the model is stored following the Mistral format.", + ) args = parser.parse_args() if not args.print_supported_models and args.model is None: @@ -7944,17 +8814,25 @@ def main() -> None: if "mmproj" not in fname_out.name: fname_out = ModelBase.add_prefix_to_filename(fname_out, "mmproj-") + is_mistral_format = args.mistral_format + with torch.inference_mode(): output_type = ftype_map[args.outtype] model_type = ModelType.MMPROJ if args.mmproj else ModelType.TEXT - hparams = ModelBase.load_hparams(dir_model) - model_architecture = get_model_architecture(hparams, model_type) - logger.info(f"Model architecture: {model_architecture}") - try: - model_class = ModelBase.from_model_architecture(model_architecture, model_type=model_type) - except NotImplementedError: - logger.error(f"Model {model_architecture} is not supported") - sys.exit(1) + hparams = ModelBase.load_hparams(dir_model, is_mistral_format) + if not is_mistral_format: + model_architecture = get_model_architecture(hparams, model_type) + logger.info(f"Model architecture: {model_architecture}") + try: + model_class = ModelBase.from_model_architecture(model_architecture, model_type=model_type) + except NotImplementedError: + logger.error(f"Model {model_architecture} is not supported") + sys.exit(1) + elif args.mmproj: + assert hparams.get("vision_encoder") is not None, "This model does not support multimodal" + model_class = PixtralModel + else: + model_class = MistralModel model_instance = model_class(dir_model, output_type, fname_out, is_big_endian=args.bigendian, use_temp_file=args.use_temp_file, @@ -7963,7 +8841,8 @@ def main() -> None: split_max_tensors=args.split_max_tensors, split_max_size=split_str_to_n_bytes(args.split_max_size), dry_run=args.dry_run, small_first_shard=args.no_tensor_first_split, - remote_hf_model_id=hf_repo_id) + remote_hf_model_id=hf_repo_id, + ) if args.vocab_only: logger.info("Exporting model vocab...") diff --git a/convert_hf_to_gguf_update.py b/convert_hf_to_gguf_update.py index abaf2ea9a1..575e05e193 100755 --- a/convert_hf_to_gguf_update.py +++ b/convert_hf_to_gguf_update.py @@ -59,6 +59,10 @@ parser.add_argument( "--full", action="store_true", help="download full list of models - make sure you have access to all of them", ) +parser.add_argument( + "--check-missing", action="store_true", + help="only check for missing pre-tokenizer hashes", +) parser.add_argument( "hf_token", help="optional HF token", @@ -70,6 +74,10 @@ hf_token = args.hf_token if args.hf_token is not None else hf_token if hf_token is None: logger.warning("HF token not found. You can provide it as an argument or set it in ~/.cache/huggingface/token") +if args.check_missing and args.full: + logger.warning("Downloading full list of models requested, ignoring --check-missing!") + args.check_missing = False + # TODO: this string has to exercise as much pre-tokenizer functionality as possible # will be updated with time - contributions welcome CHK_TXT = '\n \n\n \n\n\n \t \t\t \t\n \n \n \n \n🚀 (normal) 😶‍🌫️ (multiple emojis concatenated) ✅ 🦙🦙 3 33 333 3333 33333 333333 3333333 33333333 3.3 3..3 3...3 កាន់តែពិសេសអាច😁 ?我想在apple工作1314151天～ ------======= нещо на Български \'\'\'\'\'\'```````\"\"\"\"......!!!!!!?????? I\'ve been \'told he\'s there, \'RE you sure? \'M not sure I\'ll make it, \'D you like some tea? We\'Ve a\'lL' @@ -130,6 +138,7 @@ models = [ {"name": "midm-2.0", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/K-intelligence/Midm-2.0-Base-Instruct", }, {"name": "lfm2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/LiquidAI/LFM2-Tokenizer"}, {"name": "exaone4", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/LGAI-EXAONE/EXAONE-4.0-32B", }, + {"name": "mellum", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/JetBrains/Mellum-4b-base", }, ] # some models are known to be broken upstream, so we will skip them as exceptions @@ -138,14 +147,17 @@ pre_computed_hashes = [ {"name": "chatglm-bpe", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/THUDM/glm-4-9b-chat", "chkhsh": "b6e8e1518dc4305be2fe39c313ed643381c4da5db34a98f6a04c093f8afbe99b"}, {"name": "chatglm-bpe", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/THUDM/glm-4-9b-chat", "chkhsh": "81d72c7348a9f0ebe86f23298d37debe0a5e71149e29bd283904c02262b27516"}, {"name": "glm4", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/THUDM/glm-4-9b-hf", "chkhsh": "a1336059768a55c99a734006ffb02203cd450fed003e9a71886c88acf24fdbc2"}, + {"name": "glm4", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/zai-org/GLM-4.5-Air", "chkhsh": "9ca2dd618e8afaf09731a7cf6e2105b373ba6a1821559f258b272fe83e6eb902"}, {"name": "minerva-7b", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/sapienzanlp/Minerva-7B-base-v1.0", "chkhsh": "1431a23e583c97432bc230bff598d103ddb5a1f89960c8f1d1051aaa944d0b35"}, {"name": "hunyuan", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tencent/Hunyuan-A13B-Instruct", "chkhsh": "7e57df22b1fe23a7b1e1c7f3dc4e3f96d43a4eb0836d0c6bdc3436d7b2f1c664"}, + {"name": "hunyuan-dense", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tencent/Hunyuan-4B-Instruct", "chkhsh": "bba3b3366b646dbdded5dbc42d59598b849371afc42f7beafa914afaa5b70aa6"}, # falcon-h1 series uses 4 different tokenizers across model sizes (0.5b - 34b), hence we need to define 4 different hashes {"name": "falcon-h1", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tiiuae/Falcon-H1-0.5B-Base", "chkhsh": "a6b57017d60e6edb4d88ecc2845188e0eb333a70357e45dcc9b53964a73bbae6"}, {"name": "falcon-h1", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tiiuae/Falcon-H1-1B-Base", "chkhsh": "60476e1243776c4fb1b993dbd7a5f15ac22f83c80afdf425fa5ae01c8d44ef86"}, {"name": "falcon-h1", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tiiuae/Falcon-H1-7B-Base", "chkhsh": "3eda48b4c4dc7de733d1a8b3e3b4a85243dbbf704da2ee9d42c6beced8897896"}, {"name": "falcon-h1", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tiiuae/Falcon-H1-34B-Base", "chkhsh": "48f8e02c0359c0bbdd82f26909171fac1c18a457bb47573ed1fe3bbb2c1cfd4b"}, {"name": "kimi-k2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/moonshotai/Kimi-K2-Base", "chkhsh": "81212dc7cdb7e0c1074ca62c5aeab0d43c9f52b8a737be7b12a777c953027890"}, + {"name": "qwen2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/Qwen/Qwen3-Embedding-0.6B", "chkhsh": "d4540891389ea895b53b399da6ac824becc30f2fba0e9ddbb98f92e55ca0e97c"}, ] @@ -220,12 +232,13 @@ if not args.full: all_models = models.copy() models = [model for model in all_models if model["name"] not in existing_models] -logging.info(f"Downloading {len(models)} models...") -for model in models: - try: - download_model(model) - except Exception as e: - logger.error(f"Failed to download model {model['name']}. Error: {e}") +if not args.check_missing: + logging.info(f"Downloading {len(models)} models...") + for model in models: + try: + download_model(model) + except Exception as e: + logger.error(f"Failed to download model {model['name']}. Error: {e}") # generate the source code for the convert_hf_to_gguf.py:get_vocab_base_pre() function: diff --git a/convert_lora_to_gguf.py b/convert_lora_to_gguf.py index 00a6733cbd..a67c0536a4 100755 --- a/convert_lora_to_gguf.py +++ b/convert_lora_to_gguf.py @@ -340,7 +340,7 @@ if __name__ == '__main__': sys.exit(1) else: logger.info(f"Loading base model: {dir_base_model.name}") - hparams = ModelBase.load_hparams(dir_base_model) + hparams = ModelBase.load_hparams(dir_base_model, False) with torch.inference_mode(): try: diff --git a/docs/backend/CANN.md b/docs/backend/CANN.md index 2b001f09ab..325e09bd38 100755 --- a/docs/backend/CANN.md +++ b/docs/backend/CANN.md @@ -310,5 +310,7 @@ Specifies the memory pool management strategy: Controls automatic cleanup of the memory pool. This option is only effective when using the prio or leg memory pool strategies. -## TODO -- Support more models and data types. +### GGML_CANN_WEIGHT_NZ + +Converting the matmul weight format from ND to NZ can significantly improve performance on the 310I DUO NPU. + diff --git a/docs/build-s390x.md b/docs/build-s390x.md index 4c9ebb271c..4d5857753a 100644 --- a/docs/build-s390x.md +++ b/docs/build-s390x.md @@ -42,14 +42,14 @@ cmake --build build --config Release -j $(nproc) cmake --build build --config Release -j $(nproc) ``` -- By default, NNPA is enabled when available. To disable it (not recommended): +- By default, NNPA is disabled by default. To enable it: ```bash cmake -S . -B build \ -DCMAKE_BUILD_TYPE=Release \ -DGGML_BLAS=ON \ -DGGML_BLAS_VENDOR=OpenBLAS \ - -DGGML_NNPA=OFF + -DGGML_NNPA=ON cmake --build build --config Release -j $(nproc) ``` @@ -84,9 +84,9 @@ All models need to be converted to Big-Endian. You can achieve this in three cas ![File Type - gguf](https://img.shields.io/badge/File_Type-gguf-fff) - You can find popular models pre-converted and verified at [s390x Ready Models](https://huggingface.co/collections/taronaeo/s390x-ready-models-672765393af438d0ccb72a08). + You can find popular models pre-converted and verified at [s390x Verified Models](https://huggingface.co/collections/taronaeo/s390x-verified-models-672765393af438d0ccb72a08) or [s390x Runnable Models](https://huggingface.co/collections/taronaeo/s390x-runnable-models-686e951824198df12416017e). - These models have already been converted from `safetensors` to `GGUF Big-Endian` and their respective tokenizers verified to run correctly on IBM z15 and later system. + These models have already been converted from `safetensors` to `GGUF` Big-Endian and their respective tokenizers verified to run correctly on IBM z15 and later system. 2. **Convert safetensors model to GGUF Big-Endian directly (recommended)** @@ -94,6 +94,14 @@ All models need to be converted to Big-Endian. You can achieve this in three cas The model you are trying to convert must be in `safetensors` file format (for example [IBM Granite 3.3 2B](https://huggingface.co/ibm-granite/granite-3.3-2b-instruct)). Make sure you have downloaded the model repository for this case. + Ensure that you have installed the required packages in advance + + ```bash + pip3 install -r requirements.txt + ``` + + Convert the `safetensors` model to `GGUF` + ```bash python3 convert_hf_to_gguf.py \ --outfile model-name-be.f16.gguf \ @@ -116,7 +124,7 @@ All models need to be converted to Big-Endian. You can achieve this in three cas ![File Type - gguf](https://img.shields.io/badge/File_Type-gguf-fff) - The model you are trying to convert must be in `gguf` file format (for example [IBM Granite 3.3 2B](https://huggingface.co/ibm-granite/granite-3.3-2b-instruct-GGUF)). Make sure you have downloaded the model file for this case. + The model you are trying to convert must be in `gguf` file format (for example [IBM Granite 3.3 2B GGUF](https://huggingface.co/ibm-granite/granite-3.3-2b-instruct-GGUF)). Make sure you have downloaded the model file for this case. ```bash python3 gguf-py/gguf/scripts/gguf_convert_endian.py model-name.f16.gguf BIG @@ -141,15 +149,15 @@ Only available in IBM z15 or later system with the `-DGGML_VXE=ON` (turned on by ### 2. NNPA Vector Intrinsics Acceleration -Only available in IBM z16 or later system with the `-DGGML_NNPA=ON` (turned on when available) compile flag. No hardware acceleration is possible with llama.cpp with older systems, such as IBM z15/arch13. In such systems, the APIs can still run but will use a scalar implementation. +Only available in IBM z16 or later system with the `-DGGML_NNPA=ON` (turned off by default) compile flag. No hardware acceleration is possible with llama.cpp with older systems, such as IBM z15/arch13. In such systems, the APIs can still run but will use a scalar implementation. ### 3. zDNN Accelerator -_Only available in IBM z16 or later system. No direction at the moment._ +_Only available in IBM z16 / LinuxONE 4 or later system. No support currently available._ ### 4. Spyre Accelerator -_No direction at the moment._ +_Only available with IBM z17 / LinuxONE 5 or later system. No support currently available._ ## Performance Tuning @@ -189,6 +197,26 @@ IBM VXE/VXE2 SIMD acceleration depends on the BLAS implementation. It is strongl Answer: Please ensure that your GCC compiler is of minimum GCC 15.1.0 version, and have `binutils` updated to the latest version. If this does not fix the problem, kindly open an issue. +4. Failing to install the `sentencepiece` package using GCC 15+ + + Answer: The `sentencepiece` team are aware of this as seen in [this issue](https://github.com/google/sentencepiece/issues/1108). + + As a temporary workaround, please run the installation command with the following environment variables. + + ```bash + export CXXFLAGS="-include cstdint" + ``` + + For example, + + ```bash + CXXFLAGS="-include cstdint" pip3 install -r requirements.txt + ``` + +5. `-DGGML_NNPA=ON` generates gibberish output + + Answer: We are aware of this as detailed in [this issue](https://github.com/ggml-org/llama.cpp/issues/14877). Please either try reducing the number of threads, or disable the compile option using `-DGGML_NNPA=OFF`. + ## Getting Help on IBM Z & LinuxONE 1. **Bugs, Feature Requests** @@ -244,3 +272,5 @@ IBM VXE/VXE2 SIMD acceleration depends on the BLAS implementation. It is strongl - ✅ - acceleration available - 🚫 - acceleration unavailable, will still run using scalar implementation - ❓ - acceleration unknown, please contribute if you can test it yourself + +Last Updated by **Aaron Teo (aaron.teo1@ibm.com)** on July 25, 2025. diff --git a/docs/build.md b/docs/build.md index 849c825269..dd486fe293 100644 --- a/docs/build.md +++ b/docs/build.md @@ -68,6 +68,9 @@ cmake --build build --config Release cmake --build build-x64-windows-llvm-release ``` - Curl usage is enabled by default and can be turned off with `-DLLAMA_CURL=OFF`. Otherwise you need to install development libraries for libcurl. + - **Debian / Ubuntu:** `sudo apt-get install libcurl4-openssl-dev` # (or `libcurl4-gnutls-dev` if you prefer GnuTLS) + - **Fedora / RHEL / Rocky / Alma:** `sudo dnf install libcurl-devel` + - **Arch / Manjaro:** `sudo pacman -S curl` # includes libcurl headers ## BLAS Build diff --git a/docs/development/HOWTO-add-model.md b/docs/development/HOWTO-add-model.md index 51e0b0b20f..5989b873a6 100644 --- a/docs/development/HOWTO-add-model.md +++ b/docs/development/HOWTO-add-model.md @@ -23,11 +23,19 @@ The convert script reads the model configuration, tokenizer, tensor names+data a The required steps to implement for an HF model are: -1. Define the model `Model.register` annotation in a new `Model` subclass, example: +1. Define the model `ModelBase.register` annotation in a new `TextModel` or `MmprojModel` subclass, example: ```python -@Model.register("MyModelForCausalLM") -class MyModel(Model): +@ModelBase.register("MyModelForCausalLM") +class MyModel(TextModel): + model_arch = gguf.MODEL_ARCH.MYMODEL +``` + +or + +```python +@ModelBase.register("MyModelForConditionalGeneration") +class MyModel(MmprojModel): model_arch = gguf.MODEL_ARCH.MYMODEL ``` @@ -75,9 +83,10 @@ block_mappings_cfg: dict[MODEL_TENSOR, tuple[str, ...]] = { `transformer.blocks.{bid}.norm_1` will be mapped to `blk.{bid}.attn_norm` in GGUF. Depending on the model configuration, tokenizer, code and tensors layout, you will have to override: -- `Model#set_gguf_parameters` -- `Model#set_vocab` -- `Model#write_tensors` +- `TextModel#set_gguf_parameters` +- `MmprojModel#set_gguf_parameters` +- `ModelBase#set_vocab` +- `ModelBase#modify_tensors` NOTE: Tensor names must end with `.weight` or `.bias` suffixes, that is the convention and several tools like `quantize` expect this to proceed the weights. diff --git a/docs/docker.md b/docs/docker.md index cbb333ee32..543a51f75c 100644 --- a/docs/docker.md +++ b/docs/docker.md @@ -110,7 +110,7 @@ You may want to pass in some different `ARGS`, depending on the MUSA environment The defaults are: -- `MUSA_VERSION` set to `rc4.0.1` +- `MUSA_VERSION` set to `rc4.2.0` The resulting images, are essentially the same as the non-MUSA images: diff --git a/docs/multimodal.md b/docs/multimodal.md index edbd081df7..e2e12d07df 100644 --- a/docs/multimodal.md +++ b/docs/multimodal.md @@ -97,6 +97,9 @@ NOTE: some models may require large context window, for example: `-c 8192` # Qwen2-Audio and SeaLLM-Audio # note: no pre-quantized GGUF this model, as they have very poor result # ref: https://github.com/ggml-org/llama.cpp/pull/13760 + +# Mistral's Voxtral +(tool_name) -hf ggml-org/Voxtral-Mini-3B-2507-GGUF ``` **Mixed modalities**: diff --git a/docs/multimodal/minicpmo2.6.md b/docs/multimodal/minicpmo2.6.md index 8c6db8efe5..5e74058e5d 100644 --- a/docs/multimodal/minicpmo2.6.md +++ b/docs/multimodal/minicpmo2.6.md @@ -13,7 +13,7 @@ If there are differences in usage, please refer to the official build [documenta Clone llama.cpp: ```bash -git clone https://github.com/ggerganov/llama.cpp +git clone https://github.com/ggml-org/llama.cpp cd llama.cpp ``` @@ -29,8 +29,8 @@ cmake --build build --config Release Convert PyTorch model to gguf files (You can also download the converted [gguf](https://huggingface.co/openbmb/MiniCPM-o-2_6-gguf) by us) ```bash -python ./tools/mtmd/minicpmv-surgery.py -m ../MiniCPM-o-2_6 -python ./tools/mtmd/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-o-2_6 --minicpmv-projector ../MiniCPM-o-2_6/minicpmv.projector --output-dir ../MiniCPM-o-2_6/ --image-mean 0.5 0.5 0.5 --image-std 0.5 0.5 0.5 --minicpmv_version 4 +python ./tools/mtmd/legacy-models/minicpmv-surgery.py -m ../MiniCPM-o-2_6 +python ./tools/mtmd/legacy-models/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-o-2_6 --minicpmv-projector ../MiniCPM-o-2_6/minicpmv.projector --output-dir ../MiniCPM-o-2_6/ --minicpmv_version 4 python ./convert_hf_to_gguf.py ../MiniCPM-o-2_6/model # quantize int4 version diff --git a/docs/multimodal/minicpmo4.0.md b/docs/multimodal/minicpmo4.0.md new file mode 100644 index 0000000000..49125ea05e --- /dev/null +++ b/docs/multimodal/minicpmo4.0.md @@ -0,0 +1,47 @@ +## MiniCPM-o 4 + +### Prepare models and code + +Download [MiniCPM-o-4](https://huggingface.co/openbmb/MiniCPM-o-4) PyTorch model from huggingface to "MiniCPM-o-4" folder. + + +### Build llama.cpp +Readme modification time: 20250206 + +If there are differences in usage, please refer to the official build [documentation](https://github.com/ggerganov/llama.cpp/blob/master/docs/build.md) + +Clone llama.cpp: +```bash +git clone https://github.com/ggerganov/llama.cpp +cd llama.cpp +``` + +Build llama.cpp using `CMake`: +```bash +cmake -B build +cmake --build build --config Release +``` + + +### Usage of MiniCPM-o 4 + +Convert PyTorch model to gguf files (You can also download the converted [gguf](https://huggingface.co/openbmb/MiniCPM-o-4-gguf) by us) + +```bash +python ./tools/mtmd/legacy-models/minicpmv-surgery.py -m ../MiniCPM-o-4 +python ./tools/mtmd/legacy-models/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-o-4 --minicpmv-projector ../MiniCPM-o-4/minicpmv.projector --output-dir ../MiniCPM-o-4/ --minicpmv_version 6 +python ./convert_hf_to_gguf.py ../MiniCPM-o-4/model + +# quantize int4 version +./build/bin/llama-quantize ../MiniCPM-o-4/model/ggml-model-f16.gguf ../MiniCPM-o-4/model/ggml-model-Q4_K_M.gguf Q4_K_M +``` + + +Inference on Linux or Mac +```bash +# run in single-turn mode +./build/bin/llama-mtmd-cli -m ../MiniCPM-o-4/model/ggml-model-f16.gguf --mmproj ../MiniCPM-o-4/mmproj-model-f16.gguf -c 4096 --temp 0.7 --top-p 0.8 --top-k 100 --repeat-penalty 1.05 --image xx.jpg -p "What is in the image?" + +# run in conversation mode +./build/bin/llama-mtmd-cli -m ../MiniCPM-o-4/model/ggml-model-Q4_K_M.gguf --mmproj ../MiniCPM-o-4/mmproj-model-f16.gguf +``` diff --git a/docs/multimodal/minicpmv2.5.md b/docs/multimodal/minicpmv2.5.md index 19b439607d..5eb87bc969 100644 --- a/docs/multimodal/minicpmv2.5.md +++ b/docs/multimodal/minicpmv2.5.md @@ -28,8 +28,8 @@ cmake --build build --config Release Convert PyTorch model to gguf files (You can also download the converted [gguf](https://huggingface.co/openbmb/MiniCPM-Llama3-V-2_5-gguf) by us) ```bash -python ./tools/mtmd/minicpmv-surgery.py -m ../MiniCPM-Llama3-V-2_5 -python ./tools/mtmd/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-Llama3-V-2_5 --minicpmv-projector ../MiniCPM-Llama3-V-2_5/minicpmv.projector --output-dir ../MiniCPM-Llama3-V-2_5/ --image-mean 0.5 0.5 0.5 --image-std 0.5 0.5 0.5 --minicpmv_version 2 +python ./tools/mtmd/legacy-models/minicpmv-surgery.py -m ../MiniCPM-Llama3-V-2_5 +python ./tools/mtmd/legacy-models/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-Llama3-V-2_5 --minicpmv-projector ../MiniCPM-Llama3-V-2_5/minicpmv.projector --output-dir ../MiniCPM-Llama3-V-2_5/ --minicpmv_version 2 python ./convert_hf_to_gguf.py ../MiniCPM-Llama3-V-2_5/model # quantize int4 version diff --git a/docs/multimodal/minicpmv2.6.md b/docs/multimodal/minicpmv2.6.md index 15c1bbd12e..bc874bbd8c 100644 --- a/docs/multimodal/minicpmv2.6.md +++ b/docs/multimodal/minicpmv2.6.md @@ -12,7 +12,7 @@ If there are differences in usage, please refer to the official build [documenta Clone llama.cpp: ```bash -git clone https://github.com/ggerganov/llama.cpp +git clone https://github.com/ggml-org/llama.cpp cd llama.cpp ``` @@ -28,8 +28,8 @@ cmake --build build --config Release Convert PyTorch model to gguf files (You can also download the converted [gguf](https://huggingface.co/openbmb/MiniCPM-V-2_6-gguf) by us) ```bash -python ./tools/mtmd/minicpmv-surgery.py -m ../MiniCPM-V-2_6 -python ./tools/mtmd/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-V-2_6 --minicpmv-projector ../MiniCPM-V-2_6/minicpmv.projector --output-dir ../MiniCPM-V-2_6/ --image-mean 0.5 0.5 0.5 --image-std 0.5 0.5 0.5 --minicpmv_version 3 +python ./tools/mtmd/legacy-models/minicpmv-surgery.py -m ../MiniCPM-V-2_6 +python ./tools/mtmd/legacy-models/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-V-2_6 --minicpmv-projector ../MiniCPM-V-2_6/minicpmv.projector --output-dir ../MiniCPM-V-2_6/ --minicpmv_version 3 python ./convert_hf_to_gguf.py ../MiniCPM-V-2_6/model # quantize int4 version diff --git a/docs/multimodal/minicpmv4.0.md b/docs/multimodal/minicpmv4.0.md new file mode 100644 index 0000000000..65887d9601 --- /dev/null +++ b/docs/multimodal/minicpmv4.0.md @@ -0,0 +1,47 @@ +## MiniCPM-V 4 + +### Prepare models and code + +Download [MiniCPM-V-4](https://huggingface.co/openbmb/MiniCPM-V-4) PyTorch model from huggingface to "MiniCPM-V-4" folder. + + +### Build llama.cpp +Readme modification time: 20250206 + +If there are differences in usage, please refer to the official build [documentation](https://github.com/ggerganov/llama.cpp/blob/master/docs/build.md) + +Clone llama.cpp: +```bash +git clone https://github.com/ggerganov/llama.cpp +cd llama.cpp +``` + +Build llama.cpp using `CMake`: +```bash +cmake -B build +cmake --build build --config Release +``` + + +### Usage of MiniCPM-V 4 + +Convert PyTorch model to gguf files (You can also download the converted [gguf](https://huggingface.co/openbmb/MiniCPM-V-4-gguf) by us) + +```bash +python ./tools/mtmd/legacy-models/minicpmv-surgery.py -m ../MiniCPM-V-4 +python ./tools/mtmd/legacy-models/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-V-4 --minicpmv-projector ../MiniCPM-V-4/minicpmv.projector --output-dir ../MiniCPM-V-4/ --minicpmv_version 5 +python ./convert_hf_to_gguf.py ../MiniCPM-V-4/model + +# quantize int4 version +./build/bin/llama-quantize ../MiniCPM-V-4/model/ggml-model-f16.gguf ../MiniCPM-V-4/model/ggml-model-Q4_K_M.gguf Q4_K_M +``` + + +Inference on Linux or Mac +```bash +# run in single-turn mode +./build/bin/llama-mtmd-cli -m ../MiniCPM-V-4/model/ggml-model-f16.gguf --mmproj ../MiniCPM-V-4/mmproj-model-f16.gguf -c 4096 --temp 0.7 --top-p 0.8 --top-k 100 --repeat-penalty 1.05 --image xx.jpg -p "What is in the image?" + +# run in conversation mode +./build/bin/llama-mtmd-cli -m ../MiniCPM-V-4/model/ggml-model-Q4_K_M.gguf --mmproj ../MiniCPM-V-4/mmproj-model-f16.gguf +``` diff --git a/docs/ops.md b/docs/ops.md index f6a06e3b90..1a474d9047 100644 --- a/docs/ops.md +++ b/docs/ops.md @@ -2,94 +2,101 @@ List of GGML operations and backend support status. +## How to add a backend to this table: + +1. Run `test-backend-ops support --output csv` with your backend name and redirect output to a csv file in `docs/ops/` (e.g., `docs/ops/CUDA.csv`) +2. Regenerate `/docs/ops.md` via `./scripts/create_ops_docs.py` + Legend: - ✅ Fully supported by this backend - 🟡 Partially supported by this backend - ❌ Not supported by this backend -| Operation | BLAS | CPU | CUDA | Metal | -|-----------|------|------|------|------| -| ABS | ❌ | ✅ | 🟡 | ❌ | -| ACC | ❌ | ✅ | ✅ | ✅ | -| ADD | ❌ | ✅ | ✅ | 🟡 | -| ADD1 | ❌ | ✅ | ✅ | ❌ | -| ARANGE | ❌ | ✅ | ✅ | ✅ | -| ARGMAX | ❌ | ✅ | ✅ | ✅ | -| ARGSORT | ❌ | ✅ | ✅ | ✅ | -| CLAMP | ❌ | ✅ | ✅ | 🟡 | -| CONCAT | ❌ | ✅ | 🟡 | ✅ | -| CONT | ❌ | ✅ | 🟡 | ✅ | -| CONV_2D_DW | ❌ | ✅ | ✅ | ❌ | -| CONV_TRANSPOSE_1D | ❌ | ✅ | ✅ | ✅ | -| CONV_TRANSPOSE_2D | ❌ | ✅ | ✅ | ❌ | -| COS | ❌ | ✅ | ✅ | 🟡 | -| COUNT_EQUAL | ❌ | ✅ | ✅ | ❌ | -| CPY | ❌ | 🟡 | 🟡 | 🟡 | -| CROSS_ENTROPY_LOSS | ❌ | ✅ | ✅ | ❌ | -| CROSS_ENTROPY_LOSS_BACK | ❌ | ✅ | ✅ | ❌ | -| DIAG_MASK_INF | ❌ | ✅ | ✅ | 🟡 | -| DIV | ❌ | ✅ | ✅ | 🟡 | -| DUP | ❌ | ✅ | 🟡 | 🟡 | -| ELU | ❌ | ✅ | ❌ | 🟡 | -| EXP | ❌ | ✅ | 🟡 | ❌ | -| FLASH_ATTN_EXT | ❌ | ✅ | 🟡 | 🟡 | -| GATED_LINEAR_ATTN | ❌ | ✅ | ✅ | ❌ | -| GEGLU | ❌ | ✅ | ✅ | 🟡 | -| GEGLU_ERF | ❌ | ✅ | ✅ | 🟡 | -| GEGLU_QUICK | ❌ | ✅ | ✅ | 🟡 | -| GELU | ❌ | ✅ | 🟡 | 🟡 | -| GELU_ERF | ❌ | ✅ | 🟡 | 🟡 | -| GELU_QUICK | ❌ | ✅ | 🟡 | 🟡 | -| GET_ROWS | ❌ | ✅ | 🟡 | ✅ | -| GET_ROWS_BACK | ❌ | 🟡 | 🟡 | ❌ | -| GROUP_NORM | ❌ | ✅ | ✅ | ✅ | -| HARDSIGMOID | ❌ | ✅ | 🟡 | ❌ | -| HARDSWISH | ❌ | ✅ | 🟡 | ❌ | -| IM2COL | ❌ | ✅ | ✅ | 🟡 | -| L2_NORM | ❌ | ✅ | ✅ | ✅ | -| LEAKY_RELU | ❌ | ✅ | ✅ | ✅ | -| LOG | ❌ | ✅ | ✅ | ❌ | -| MEAN | ❌ | ✅ | ✅ | ✅ | -| MUL | ❌ | ✅ | ✅ | 🟡 | -| MUL_MAT | 🟡 | 🟡 | 🟡 | 🟡 | -| MUL_MAT_ID | ❌ | ✅ | ✅ | ✅ | -| NEG | ❌ | ✅ | 🟡 | 🟡 | -| NORM | ❌ | ✅ | ✅ | 🟡 | -| OPT_STEP_ADAMW | ❌ | ✅ | ✅ | ❌ | -| OUT_PROD | 🟡 | 🟡 | 🟡 | ❌ | -| PAD | ❌ | ✅ | ✅ | ✅ | -| PAD_REFLECT_1D | ❌ | ✅ | ❌ | ✅ | -| POOL_2D | ❌ | ✅ | ✅ | ✅ | -| REGLU | ❌ | ✅ | ✅ | 🟡 | -| RELU | ❌ | ✅ | 🟡 | 🟡 | -| REPEAT | ❌ | ✅ | 🟡 | ✅ | -| REPEAT_BACK | ❌ | ✅ | ✅ | ❌ | -| RMS_NORM | ❌ | ✅ | ✅ | 🟡 | -| RMS_NORM_BACK | ❌ | ✅ | ✅ | ❌ | -| RMS_NORM_MUL | ❌ | ✅ | ✅ | ✅ | -| ROPE | ❌ | ✅ | ✅ | ✅ | -| ROPE_BACK | ❌ | ✅ | ✅ | ❌ | -| RWKV_WKV6 | ❌ | ✅ | ✅ | ✅ | -| RWKV_WKV7 | ❌ | ✅ | ✅ | ✅ | -| SCALE | ❌ | ✅ | ✅ | ✅ | -| SET | ❌ | ✅ | ❌ | ✅ | -| SET_ROWS | ❌ | 🟡 | ❌ | 🟡 | -| SGN | ❌ | ✅ | 🟡 | ❌ | -| SIGMOID | ❌ | ✅ | 🟡 | 🟡 | -| SILU | ❌ | ✅ | 🟡 | 🟡 | -| SILU_BACK | ❌ | ✅ | ✅ | ❌ | -| SIN | ❌ | ✅ | ✅ | 🟡 | -| SOFT_MAX | ❌ | ✅ | ✅ | ✅ | -| SOFT_MAX_BACK | ❌ | 🟡 | 🟡 | ❌ | -| SQR | ❌ | ✅ | ✅ | 🟡 | -| SQRT | ❌ | ✅ | ✅ | 🟡 | -| SSM_CONV | ❌ | ✅ | ✅ | ✅ | -| SSM_SCAN | ❌ | ✅ | ✅ | ✅ | -| STEP | ❌ | ✅ | 🟡 | ❌ | -| SUB | ❌ | ✅ | ✅ | 🟡 | -| SUM | ❌ | ✅ | ✅ | ❌ | -| SUM_ROWS | ❌ | ✅ | ✅ | ✅ | -| SWIGLU | ❌ | ✅ | ✅ | 🟡 | -| TANH | ❌ | ✅ | 🟡 | 🟡 | -| TIMESTEP_EMBEDDING | ❌ | ✅ | ✅ | ✅ | -| UPSCALE | ❌ | ✅ | ✅ | 🟡 | +| Operation | BLAS | CANN | CPU | CUDA | Metal | OpenCL | SYCL | Vulkan | +|-----------|------|------|------|------|------|------|------|------| +| ABS | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | +| ACC | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | +| ADD | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | +| ADD1 | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | +| ARANGE | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | +| ARGMAX | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | +| ARGSORT | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| CLAMP | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | +| CONCAT | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | 🟡 | ✅ | +| CONT | ❌ | 🟡 | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | +| CONV_2D | ❌ | ❌ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | +| CONV_2D_DW | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | +| CONV_TRANSPOSE_1D | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | +| CONV_TRANSPOSE_2D | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | +| COS | ❌ | ✅ | ✅ | ✅ | 🟡 | ❌ | ✅ | 🟡 | +| COUNT_EQUAL | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | +| CPY | ❌ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | +| CROSS_ENTROPY_LOSS | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | +| CROSS_ENTROPY_LOSS_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | +| DIAG_MASK_INF | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | +| DIV | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | +| DUP | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | +| ELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | +| EXP | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | +| FLASH_ATTN_EXT | ❌ | 🟡 | ✅ | 🟡 | 🟡 | ❌ | ❌ | 🟡 | +| GATED_LINEAR_ATTN | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | +| GEGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | +| GEGLU_ERF | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | +| GEGLU_QUICK | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | +| GELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | +| GELU_ERF | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | +| GELU_QUICK | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | +| GET_ROWS | ❌ | 🟡 | ✅ | 🟡 | ✅ | 🟡 | 🟡 | 🟡 | +| GET_ROWS_BACK | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | ❌ | ❌ | +| GROUP_NORM | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| HARDSIGMOID | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | +| HARDSWISH | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | +| IM2COL | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | +| L2_NORM | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | +| LEAKY_RELU | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | +| LOG | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | +| MEAN | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | +| MUL | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | +| MUL_MAT | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | +| MUL_MAT_ID | ❌ | 🟡 | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | +| NEG | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | +| NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | +| OPT_STEP_ADAMW | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | +| OUT_PROD | 🟡 | ❌ | 🟡 | 🟡 | ❌ | ❌ | 🟡 | ❌ | +| PAD | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| PAD_REFLECT_1D | ❌ | ✅ | ✅ | ❌ | ✅ | ❌ | ❌ | ❌ | +| POOL_2D | ❌ | 🟡 | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | +| REGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | +| RELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | +| REPEAT | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | 🟡 | +| REPEAT_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | +| RMS_NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | +| RMS_NORM_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | +| RMS_NORM_MUL_ADD | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| ROLL | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | +| ROPE | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| ROPE_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | +| RWKV_WKV6 | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | +| RWKV_WKV7 | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | +| SCALE | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| SET | ❌ | ❌ | ✅ | ❌ | ✅ | ❌ | ❌ | ❌ | +| SET_ROWS | ❌ | ❌ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | +| SGN | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | +| SIGMOID | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | +| SILU | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | +| SILU_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | +| SIN | ❌ | ✅ | ✅ | ✅ | 🟡 | ❌ | ✅ | 🟡 | +| SOFT_MAX | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | 🟡 | ✅ | +| SOFT_MAX_BACK | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | ❌ | ✅ | +| SQR | ❌ | ✅ | ✅ | ✅ | 🟡 | ❌ | ✅ | 🟡 | +| SQRT | ❌ | ✅ | ✅ | ✅ | 🟡 | ❌ | ✅ | ❌ | +| SSM_CONV | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | +| SSM_SCAN | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | +| STEP | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | +| SUB | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | +| SUM | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ✅ | +| SUM_ROWS | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| SWIGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | +| TANH | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | 🟡 | +| TIMESTEP_EMBEDDING | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| UPSCALE | ❌ | 🟡 | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | diff --git a/docs/ops/BLAS.csv b/docs/ops/BLAS.csv index dde13f701d..74c767cf29 100644 --- a/docs/ops/BLAS.csv +++ b/docs/ops/BLAS.csv @@ -1,6534 +1,8133 @@ -"test_time","build_commit","backend_name","op_name","op_params","test_mode","supported","passed","error_message","time_us","flops","bandwidth_gb_s","memory_kb","n_runs","device_description","backend_reg_name" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SILU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SILU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","EXP","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","EXP","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ABS","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ABS","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SGN","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SGN","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","NEG","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","NEG","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","STEP","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","STEP","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","TANH","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","TANH","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SILU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SILU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","EXP","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","EXP","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ABS","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ABS","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SGN","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SGN","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","NEG","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","TANH","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ELU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RELU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SIGMOID","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SIGMOID","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_QUICK","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_QUICK","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SILU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SILU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSWISH","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSWISH","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSIGMOID","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","HARDSIGMOID","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","EXP","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","EXP","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_ERF","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,32],ne_kernel=[3,3,1,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,32],ne_kernel=[3,3,2,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,1024],ne_kernel=[3,3,1,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,1024],ne_kernel=[3,3,2,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2048],ne_kernel=[3,3,1,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2048],ne_kernel=[3,3,2,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2560],ne_kernel=[3,3,1,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2560],ne_kernel=[3,3,2,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[197,32,1,1],ne_kernel=[16,32,32,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,1,2,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_2D","ne_input=[3,2,3,1],ne_kernel=[2,2,1,3],stride=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_2D","ne_input=[10,10,9,1],ne_kernel=[3,3,1,9],stride=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","COUNT_EQUAL","type=f32,ne=[4,500,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","COUNT_EQUAL","type=f32,ne=[4,5000,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[100,10,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[1024,10,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[1024,12,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[2000,10,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[5438,3,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,1],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=i32,ne=[10,5,4,1],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=i16,ne=[10,5,4,1],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=i32,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=i16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f32,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f16,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=i32,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=i16,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f32,ne=[10,10,5,1],permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f16,ne=[10,10,5,1],permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f32,ne=[10,10,5,1],permute=[1,0,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f16,ne=[10,10,5,1],permute=[1,0,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=i16,ne=[10,8,3,1],permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=i16,ne=[10,8,3,1],permute=[1,2,0,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIV","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIV","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIV","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIV","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=1.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","L2_NORM","type=f32,ne=[64,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SSM_CONV","type=f32,ne_a=[4,1536,1,1],ne_b=[4,1536,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SSM_CONV","type=f32,ne_a=[8,1536,1,1],ne_b=[4,1536,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SSM_CONV","type=f32,ne_a=[4,1536,4,1],ne_b=[4,1536,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SSM_SCAN","type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SSM_SCAN","type=f32,d_state=128,head_dim=64,n_head=16,n_group=2,n_seq_tokens=32,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=1,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=128,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=64,n=45,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=45,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=193,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=67,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q3_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q3_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q6_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q6_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq3_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq3_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq1_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq1_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq1_m,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq1_m,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq4_nl,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq4_nl,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq3_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq3_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq4_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq4_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=bf16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=bf16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SQR","type=f16,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SQRT","type=f16,ne=[10,3,3,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","LOG","type=f16,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SIN","type=f16,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","COS","type=f16,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CLAMP","type=f16,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SQR","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SQRT","type=f32,ne=[10,3,3,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","LOG","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SIN","type=f32,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","COS","type=f32,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CLAMP","type=f32,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIAG_MASK_INF","type=f32,ne=[10,10,1,1],n_past=5","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIAG_MASK_INF","type=f32,ne=[10,10,3,1],n_past=5","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIAG_MASK_INF","type=f32,ne=[10,10,3,2],n_past=5","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[8,1,1,1],order=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[16,10,10,10],order=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[60,10,10,10],order=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[8,1,1,1],order=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[16,10,10,10],order=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[60,10,10,10],order=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=257","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUM","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUM_ROWS","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MEAN","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GROUP_NORM","type=f32,ne=[64,64,320,1],num_groups=32,eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GROUP_NORM","type=f32,ne=[9,9,1280,1],num_groups=32,eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ACC","type=f32,ne_a=[256,17,1,1],ne_b=[256,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","PAD","type=f32,ne_a=[512,512,1,1],pad_0=1,pad_1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","PAD_REFLECT_1D","type=f32,ne_a=[512,34,2,1],pad_0=10,pad_1=9","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARANGE","type=f32,start=0.000000,stop=10.000000,step=1.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","TIMESTEP_EMBEDDING","type=f32,ne_a=[2,1,1,1],dim=320,max_period=10000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","LEAKY_RELU","type=f32,ne_a=[10,5,4,3],negative_slope=0.100000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[30000,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OPT_STEP_ADAMW","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" +"backend_name","op_name","op_params","test_mode","supported","error_message","backend_reg_name" +"BLAS","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","BLAS" +"BLAS","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","BLAS" +"BLAS","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","BLAS" +"BLAS","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","BLAS" +"BLAS","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","BLAS" 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b/docs/ops/CANN.csv new file mode 100644 index 0000000000..0ac1078304 --- /dev/null +++ b/docs/ops/CANN.csv @@ -0,0 +1,8133 @@ +"backend_name","op_name","op_params","test_mode","supported","error_message","backend_reg_name" +"CANN0","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" 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+"CANN0","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","0","no","CANN" +"CANN0","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","0","no","CANN" +"CANN0","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","0","no","CANN" +"CANN0","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[30000,1,1,1]","support","0","no","CANN" +"CANN0","OPT_STEP_ADAMW","type=f32,ne=[10,5,4,3]","support","0","no","CANN" diff --git a/docs/ops/CPU.csv b/docs/ops/CPU.csv index ca3222d71e..21e0d1b3c9 100644 --- a/docs/ops/CPU.csv +++ b/docs/ops/CPU.csv @@ -1,6534 +1,7349 @@ -"test_time","build_commit","backend_name","op_name","op_params","test_mode","supported","passed","error_message","time_us","flops","bandwidth_gb_s","memory_kb","n_runs","device_description","backend_reg_name" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,32],ne_kernel=[3,3,1,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,32],ne_kernel=[3,3,2,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,1024],ne_kernel=[3,3,1,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,1024],ne_kernel=[3,3,2,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2048],ne_kernel=[3,3,1,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2048],ne_kernel=[3,3,2,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2560],ne_kernel=[3,3,1,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2560],ne_kernel=[3,3,2,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT","type=i32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT","type=i16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f32,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f16,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=i32,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=i16,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f32,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f16,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f32,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f16,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=i16,ne=[10,8,3,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=i16,ne=[10,8,3,1],permute=[1,2,0,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONT","type=f32,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONT","type=f16,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONT","type=f16,ne=[2,1,3,5]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONT","type=f16,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONT","type=bf16,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","SUB","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DIV","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ADD","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SUB","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ADD","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SUB","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DIV","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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+"CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","yes","CPU" +"CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","yes","CPU" +"CPU","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","1","yes","CPU" +"CPU","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","1","yes","CPU" +"CPU","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","1","yes","CPU" +"CPU","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[30000,1,1,1]","support","1","yes","CPU" +"CPU","OPT_STEP_ADAMW","type=f32,ne=[10,5,4,3]","support","1","yes","CPU" diff --git a/docs/ops/CUDA.csv b/docs/ops/CUDA.csv index e2d7d42ab5..71e47977e3 100644 --- a/docs/ops/CUDA.csv +++ b/docs/ops/CUDA.csv @@ -1,6534 +1,7349 @@ -"test_time","build_commit","backend_name","op_name","op_params","test_mode","supported","passed","error_message","time_us","flops","bandwidth_gb_s","memory_kb","n_runs","device_description","backend_reg_name" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SILU","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SILU","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","EXP","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","EXP","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NEG","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NEG","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","STEP","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","STEP","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","TANH","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","TANH","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SILU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SILU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","EXP","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","EXP","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,32],ne_kernel=[3,3,1,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,32],ne_kernel=[3,3,2,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,1024],ne_kernel=[3,3,1,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,1024],ne_kernel=[3,3,2,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2048],ne_kernel=[3,3,1,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2048],ne_kernel=[3,3,2,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2560],ne_kernel=[3,3,1,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2560],ne_kernel=[3,3,2,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[197,32,1,1],ne_kernel=[16,32,32,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,1,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_2D","ne_input=[3,2,3,1],ne_kernel=[2,2,1,3],stride=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_2D","ne_input=[10,10,9,1],ne_kernel=[3,3,1,9],stride=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","COUNT_EQUAL","type=f32,ne=[4,500,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","COUNT_EQUAL","type=f32,ne=[4,5000,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[100,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[1024,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[1024,12,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[2000,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[5438,3,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,1],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=i32,ne=[10,5,4,1],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=i16,ne=[10,5,4,1],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=i32,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=i16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f32,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f16,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=i32,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=i16,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f32,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f16,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f32,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f16,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=i16,ne=[10,8,3,1],permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=i16,ne=[10,8,3,1],permute=[1,2,0,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f32,ne=[10,10,10,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f32,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f32,ne=[2,1,3,5]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f32,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f16,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f16,ne=[2,1,3,5]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f16,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=bf16,ne=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=bf16,ne=[2,1,3,5]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=bf16,ne=[2,3,5,7]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000100","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=1.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SSM_CONV","type=f32,ne_a=[4,1536,1,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SSM_CONV","type=f32,ne_a=[8,1536,1,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SSM_CONV","type=f32,ne_a=[4,1536,4,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SSM_SCAN","type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SSM_SCAN","type=f32,d_state=128,head_dim=64,n_head=16,n_group=2,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=1,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=128,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=45,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=45,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=193,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=67,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=16,n_used=16,b=0,m=32,n=1024,k=16","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=16,n_used=16,b=1,m=32,n=1024,k=16","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q3_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","LOG","type=f16,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SIN","type=f16,ne=[10,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","COS","type=f16,ne=[10,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CLAMP","type=f16,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SQR","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIAG_MASK_INF","type=f32,ne=[10,10,1,1],n_past=5","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIAG_MASK_INF","type=f32,ne=[10,10,3,1],n_past=5","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIAG_MASK_INF","type=f32,ne=[10,10,3,2],n_past=5","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGSORT","type=f32,ne=[8,1,1,1],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGSORT","type=f32,ne=[16,10,10,10],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGSORT","type=f32,ne=[60,10,10,10],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=257","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUM","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUM_ROWS","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MEAN","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GROUP_NORM","type=f32,ne=[64,64,320,1],num_groups=32,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GROUP_NORM","type=f32,ne=[9,9,1280,1],num_groups=32,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ACC","type=f32,ne_a=[256,17,1,1],ne_b=[256,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","PAD","type=f32,ne_a=[512,512,1,1],pad_0=1,pad_1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","PAD_REFLECT_1D","type=f32,ne_a=[512,34,2,1],pad_0=10,pad_1=9","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARANGE","type=f32,start=0.000000,stop=10.000000,step=1.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","TIMESTEP_EMBEDDING","type=f32,ne_a=[2,1,1,1],dim=320,max_period=10000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","LEAKY_RELU","type=f32,ne_a=[10,5,4,3],negative_slope=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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a/docs/ops/Metal.csv b/docs/ops/Metal.csv index ac45d46b3c..65fa0d6573 100644 --- a/docs/ops/Metal.csv +++ b/docs/ops/Metal.csv @@ -1,6534 +1,8133 @@ -"test_time","build_commit","backend_name","op_name","op_params","test_mode","supported","passed","error_message","time_us","flops","bandwidth_gb_s","memory_kb","n_runs","device_description","backend_reg_name" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f32,n=1,m=8,r=2,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f32,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f32,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f32,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f32,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f16,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f16,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f16,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f16,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=bf16,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=bf16,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=bf16,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=bf16,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_0,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_0,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_0,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_0,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_1,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_1,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_1,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_1,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_0,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_0,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_0,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_0,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_1,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_1,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_1,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_1,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q8_0,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q8_0,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q8_0,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q8_0,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q2_K,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q2_K,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q2_K,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q2_K,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q3_K,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q3_K,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q3_K,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q3_K,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_K,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_K,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_K,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_K,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_K,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_K,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_K,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_K,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q6_K,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q6_K,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q6_K,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q6_K,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xxs,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xxs,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xxs,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xxs,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xs,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xs,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xs,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xs,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_s,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_s,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_s,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_s,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_xxs,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_xxs,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_xxs,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_xxs,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_s,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_s,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_s,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_s,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_m,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_m,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_m,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_m,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_nl,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_nl,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_nl,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_nl,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_s,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_s,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_s,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_s,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_xs,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_xs,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_xs,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_xs,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=i32,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=i32,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=i32,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=i32,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=f32,n=1,m=8,r=2,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=f32,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=f32,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=f16,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=f16,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=bf16,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=bf16,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_0,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_0,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_1,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_1,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_0,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_0,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_1,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_1,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q8_0,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q8_0,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q2_K,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q2_K,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q3_K,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q3_K,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_K,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_K,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_K,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_K,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q6_K,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q6_K,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_xxs,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_xxs,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_xs,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_xs,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_s,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_s,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq3_xxs,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq3_xxs,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq1_s,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq1_s,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq1_m,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq1_m,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq4_nl,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq4_nl,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq3_s,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq3_s,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq4_xs,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq4_xs,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=i32,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=i32,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[1,8,1,3],nr23=[1,1],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[3,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[31,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[33,5,1,1],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[3,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[31,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[33,5,1,1],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[3,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[31,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[33,5,1,7],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[3,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[31,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[33,5,1,7],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[3,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[31,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[33,5,1,1],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[3,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[31,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[33,5,1,1],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[3,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[31,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[33,5,1,7],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[3,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[31,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[33,5,1,7],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[3,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[31,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[33,5,1,1],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[3,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[31,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[33,5,1,1],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[3,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[31,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[33,5,1,7],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[3,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[31,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[33,5,1,7],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,32],ne_kernel=[3,3,1,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,32],ne_kernel=[3,3,2,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,1024],ne_kernel=[3,3,1,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,1024],ne_kernel=[3,3,2,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2048],ne_kernel=[3,3,1,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2048],ne_kernel=[3,3,2,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2560],ne_kernel=[3,3,1,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2560],ne_kernel=[3,3,2,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[197,32,1,1],ne_kernel=[16,32,32,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,1,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_2D","ne_input=[3,2,3,1],ne_kernel=[2,2,1,3],stride=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_2D","ne_input=[10,10,9,1],ne_kernel=[3,3,1,9],stride=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","COUNT_EQUAL","type=f32,ne=[4,500,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","COUNT_EQUAL","type=f32,ne=[4,5000,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[100,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[1024,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[1024,12,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[2000,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[5438,3,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,1],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=i32,ne=[10,5,4,1],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=i16,ne=[10,5,4,1],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=i32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=i16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f32,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f16,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=i32,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=i16,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f32,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f16,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f32,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f16,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=i16,ne=[10,8,3,1],permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=i16,ne=[10,8,3,1],permute=[1,2,0,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f32,ne=[10,10,10,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f32,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f32,ne=[2,1,3,5]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f32,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f16,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f16,ne=[2,1,3,5]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f16,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=bf16,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=bf16,ne=[2,1,3,5]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=bf16,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD1","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU_BACK","type=f32,ne=[64,5,4,3],eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000100","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000100","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000100","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000100","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.000100","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.100000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000100","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=1.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SSM_CONV","type=f32,ne_a=[4,1536,1,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SSM_CONV","type=f32,ne_a=[8,1536,1,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SSM_CONV","type=f32,ne_a=[4,1536,4,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SSM_SCAN","type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SSM_SCAN","type=f32,d_state=128,head_dim=64,n_head=16,n_group=2,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=1,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=128,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=45,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=45,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=193,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=67,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=16,n_used=16,b=0,m=32,n=1024,k=16","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=16,n_used=16,b=1,m=32,n=1024,k=16","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q3_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q3_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q6_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q6_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq3_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq3_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq1_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq1_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq1_m,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq1_m,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq4_nl,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq4_nl,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq3_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq3_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq4_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq4_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=bf16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=bf16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SQR","type=f16,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SQRT","type=f16,ne=[10,3,3,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","LOG","type=f16,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIN","type=f16,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","COS","type=f16,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CLAMP","type=f16,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SQR","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SQRT","type=f32,ne=[10,3,3,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","LOG","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIN","type=f32,ne=[10,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","COS","type=f32,ne=[10,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CLAMP","type=f32,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIAG_MASK_INF","type=f32,ne=[10,10,1,1],n_past=5","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIAG_MASK_INF","type=f32,ne=[10,10,3,1],n_past=5","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIAG_MASK_INF","type=f32,ne=[10,10,3,2],n_past=5","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[8,1,1,1],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[16,10,10,10],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[60,10,10,10],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[8,1,1,1],order=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[16,10,10,10],order=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[60,10,10,10],order=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=257","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUM","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUM_ROWS","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MEAN","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GROUP_NORM","type=f32,ne=[64,64,320,1],num_groups=32,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GROUP_NORM","type=f32,ne=[9,9,1280,1],num_groups=32,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ACC","type=f32,ne_a=[256,17,1,1],ne_b=[256,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","PAD","type=f32,ne_a=[512,512,1,1],pad_0=1,pad_1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","PAD_REFLECT_1D","type=f32,ne_a=[512,34,2,1],pad_0=10,pad_1=9","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARANGE","type=f32,start=0.000000,stop=10.000000,step=1.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TIMESTEP_EMBEDDING","type=f32,ne_a=[2,1,1,1],dim=320,max_period=10000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","LEAKY_RELU","type=f32,ne_a=[10,5,4,3],negative_slope=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[30000,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OPT_STEP_ADAMW","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" +"backend_name","op_name","op_params","test_mode","supported","error_message","backend_reg_name" +"Metal","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","SIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","GELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" 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+"Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","0","no","Metal" +"Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","yes","Metal" +"Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","yes","Metal" +"Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","0","no","Metal" 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+"Metal","SUB","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","SUB","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","SUB","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","SUB","type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","Metal" +"Metal","SUB","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","Metal" +"Metal","SUB","type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=2","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[16,5,4,3],nr=[1,2,1,1],nf=3","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=4","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[16,5,4,3],nr=[1,1,1,2],nf=5","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=6","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=7","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[16,5,4,3],nr=[2,2,2,2],nf=8","support","1","yes","Metal" +"Metal","ADD1","type=f32,ne=[10,5,4,3]","support","0","no","Metal" +"Metal","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000,bias=0.000000","support","1","yes","Metal" +"Metal","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000,bias=1.000000","support","1","yes","Metal" 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+"Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.000001","support","0","no","Metal" +"Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","yes","Metal" +"Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000100","support","1","yes","Metal" +"Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000100","support","1","yes","Metal" +"Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000100","support","0","no","Metal" +"Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000100","support","0","no","Metal" +"Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.000100","support","0","no","Metal" +"Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","yes","Metal" +"Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","yes","Metal" +"Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","yes","Metal" +"Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","0","no","Metal" +"Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","0","no","Metal" +"Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.100000","support","0","no","Metal" +"Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000000,broadcast=0","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000000,broadcast=1","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000001,broadcast=0","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000001,broadcast=1","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000100,broadcast=0","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000100,broadcast=1","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.100000,broadcast=0","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.100000,broadcast=1","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=1.000000,broadcast=0","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=1.000000,broadcast=1","support","1","yes","Metal" +"Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1024,1,1],ne_b=[3,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,1024,1,1],ne_b=[3,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1024,4,1],ne_b=[3,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1536,1,1],ne_b=[3,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,1536,1,1],ne_b=[3,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1536,4,1],ne_b=[3,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,2048,1,1],ne_b=[3,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,2048,1,1],ne_b=[3,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,2048,4,1],ne_b=[3,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1024,1,1],ne_b=[4,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,1024,1,1],ne_b=[4,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1024,4,1],ne_b=[4,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1536,1,1],ne_b=[4,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,1536,1,1],ne_b=[4,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1536,4,1],ne_b=[4,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,2048,1,1],ne_b=[4,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,2048,1,1],ne_b=[4,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,2048,4,1],ne_b=[4,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_SCAN","type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4","support","1","yes","Metal" +"Metal","SSM_SCAN","type=f32,d_state=128,head_dim=64,n_head=16,n_group=2,n_seq_tokens=32,n_seqs=4","support","1","yes","Metal" +"Metal","SSM_SCAN","type=f32,d_state=256,head_dim=64,n_head=8,n_group=2,n_seq_tokens=32,n_seqs=4","support","1","yes","Metal" +"Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","yes","Metal" +"Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","yes","Metal" +"Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","yes","Metal" +"Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","yes","Metal" +"Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","yes","Metal" +"Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","yes","Metal" +"Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","yes","Metal" +"Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","yes","Metal" +"Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","0","no","Metal" +"Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","0","no","Metal" +"Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","0","no","Metal" +"Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","0","no","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" 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+"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=1,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=128,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=45,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=45,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=193,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=67,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" 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+"Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","yes","Metal" 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+"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","yes","Metal" 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a/docs/ops/Vulkan.csv b/docs/ops/Vulkan.csv new file mode 100644 index 0000000000..ea25257728 --- /dev/null +++ b/docs/ops/Vulkan.csv @@ -0,0 +1,8133 @@ +"backend_name","op_name","op_params","test_mode","supported","error_message","backend_reg_name" +"Vulkan0","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Vulkan" +"Vulkan0","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Vulkan" +"Vulkan0","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Vulkan" +"Vulkan0","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Vulkan" +"Vulkan0","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Vulkan" +"Vulkan0","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Vulkan" +"Vulkan0","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Vulkan" +"Vulkan0","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Vulkan" +"Vulkan0","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","Vulkan" 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+"Vulkan0","SSM_SCAN","type=f32,d_state=256,head_dim=64,n_head=8,n_group=2,n_seq_tokens=32,n_seqs=4","support","0","no","Vulkan" +"Vulkan0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","yes","Vulkan" +"Vulkan0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","yes","Vulkan" +"Vulkan0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","yes","Vulkan" +"Vulkan0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","yes","Vulkan" +"Vulkan0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","yes","Vulkan" +"Vulkan0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","yes","Vulkan" +"Vulkan0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","yes","Vulkan" +"Vulkan0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","yes","Vulkan" +"Vulkan0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","0","no","Vulkan" +"Vulkan0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","0","no","Vulkan" +"Vulkan0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","0","no","Vulkan" +"Vulkan0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" 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+"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" 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+"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" 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+"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" 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+"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","no","Vulkan" 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+"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=1,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=128,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=45,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=45,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=193,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=67,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" 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https://github.com/ggml-org/llama.cpp/pull/14771 + + +Example of using Dream architechture: `llama-diffusion-cli -m dream7b.gguf -p "write code to train MNIST in pytorch" -ub 512 --diffusion-eps 0.001 --diffusion-algorithm 3 --diffusion-steps 256 --diffusion-visual` + +Example of using LLaDA architechture: `llama-diffusion-cli -m llada-8b.gguf -p "write code to train MNIST in pytorch" -ub 512 --diffusion-block-length 32 --diffusion-steps 256 --diffusion-visual` + diff --git a/examples/diffusion/diffusion-cli.cpp b/examples/diffusion/diffusion-cli.cpp index 3e11ce1160..8431dcea8f 100644 --- a/examples/diffusion/diffusion-cli.cpp +++ b/examples/diffusion/diffusion-cli.cpp @@ -5,344 +5,128 @@ #include "log.h" #include -#include -#include + #include #include +#include #include #include +#include +#include -typedef bool (*diffusion_step_callback_t)(int32_t step, - int32_t total_steps, - const llama_token * tokens, - int32_t n_tokens, - void * user_data); +enum diffusion_algorithm { ORIGIN = 0, ENTROPY_BASED = 1, MARGIN_BASED = 2, RANDOM = 3, CONFIDENCE_BASED = 4 }; -enum diffusion_alg { - DIFFUSION_ALG_ORIGIN = 0, - DIFFUSION_ALG_MASKGIT_PLUS = 1, - DIFFUSION_ALG_TOPK_MARGIN = 2, - DIFFUSION_ALG_ENTROPY = 3, +// Unified transfer scheduling methods +enum transfer_schedule { + TIMESTEP_BASED = 0, // Dream-style: (1.0 - s/t) * remaining + BLOCK_BASED = 1, // LLaDA-style: process in blocks with get_num_transfer_tokens }; +typedef bool (*diffusion_step_callback_t)(int32_t step, + int32_t total_steps, + const llama_token * tokens, + int32_t n_tokens, + void * user_data); + struct diffusion_params { - int32_t steps; - float eps; - float temperature; - float top_p; - int32_t top_k; - llama_token mask_token_id; - enum diffusion_alg algorithm; - float alg_temp; - diffusion_step_callback_t step_callback; - void * step_callback_user_data; - int32_t seed; + int32_t steps = 0; + float temperature = 0; + llama_token mask_token_id = LLAMA_TOKEN_NULL; + diffusion_step_callback_t step_callback = nullptr; + void * step_callback_user_data = nullptr; + int32_t seed = 0; + bool visual_mode = false; + bool shift_logits = false; // Shift logits by -1 after decode + + float top_p = 0.; + int32_t top_k = 0.; + + diffusion_algorithm algorithm = CONFIDENCE_BASED; + transfer_schedule schedule = TIMESTEP_BASED; + + float cfg_scale = 0.; // Config scale for classifier-free guidance + float eps = 0.; // Timestep scheduling + int32_t block_length = 0; // Block size (for block scheduling) + float alg_temp = 0; // algorithm temperature (0.0 = deterministic) + bool add_gumbel_noise = false; // Add gumbel noise to the logits if temp > 0.0 + + int32_t max_length = 0; // Maximum sequence length }; - -static diffusion_params diffusion_default_params() { - diffusion_params params = {}; - params.steps = 64; - params.eps = 1e-3f; - params.temperature = 0.2f; - params.top_p = 0.95f; - params.top_k = 0; - params.mask_token_id = LLAMA_TOKEN_NULL; - params.algorithm = DIFFUSION_ALG_ORIGIN; - params.alg_temp = 0.0f; - params.step_callback = nullptr; - params.step_callback_user_data = nullptr; - params.seed = 0; - return params; -} - -static void diffusion_generate(llama_context * ctx, - const llama_token * input_tokens, - llama_token * output_tokens, - int32_t n_input, - int32_t max_length, - struct diffusion_params params, - int32_t & n_generated) { - - n_generated = 0; - if (!ctx || !input_tokens || !output_tokens || n_input <= 0 || max_length <= n_input) { - return; - } - - const llama_model * model = llama_get_model(ctx); - - // Initialize with input and pad with mask tokens - std::copy(input_tokens, input_tokens + n_input, output_tokens); - std::fill(output_tokens + n_input, output_tokens + max_length, params.mask_token_id); - - std::mt19937 rng(params.seed); - - std::vector timesteps(params.steps + 1); - for (int32_t i = 0; i <= params.steps; i++) { - timesteps[i] = 1.0f - (float) i / params.steps * (1.0f - params.eps); - } - - llama_set_causal_attn(ctx, false); - - int32_t n_vocab = llama_vocab_n_tokens(llama_model_get_vocab(model)); - - std::vector candidates(n_vocab); - - std::vector conf_candidates; - conf_candidates.reserve(max_length); - - std::vector mask_positions; - mask_positions.reserve(max_length); - - struct llama_sampler * sampler = llama_sampler_chain_init(llama_sampler_chain_default_params()); - if (params.top_k > 0) { - llama_sampler_chain_add(sampler, llama_sampler_init_top_k(params.top_k)); - } - if (params.top_p < 1.0f) { - llama_sampler_chain_add(sampler, llama_sampler_init_top_p(params.top_p, 1)); - } - if (params.temperature > 0.0f) { - llama_sampler_chain_add(sampler, llama_sampler_init_temp(params.temperature)); - } - llama_sampler_chain_add(sampler, llama_sampler_init_dist(params.seed)); - - struct llama_sampler * dist_sampler = llama_sampler_init_dist(params.seed); - - llama_batch batch = llama_batch_init(max_length, 0, 1); - batch.n_tokens = max_length; - - int64_t total_sampling_time = 0; - int64_t total_time = 0; - - int64_t time_start = ggml_time_us(); - for (int32_t step = 0; step < params.steps; step++) { - if (params.step_callback) { - if (!params.step_callback(step, params.steps, output_tokens, max_length, params.step_callback_user_data)) { - break; - } - } - - for (int32_t i = 0; i < max_length; i++) { - batch.token[i] = output_tokens[i]; - batch.pos[i] = i; - batch.n_seq_id[i] = 1; - batch.seq_id[i][0] = 0; - batch.logits[i] = 1; - } - - int ret = llama_decode(ctx, batch); - if (ret != 0) { - LOG_ERR("%s: failed to decode at step %d, ret = %d\n", __func__, step, ret); - break; - } - - float * raw_logits = llama_get_logits(ctx); - if (!raw_logits) { - LOG_ERR("%s: failed to get logits at step %d\n", __func__, step); - break; - } - - auto get_logits_for_pos = [&](int32_t pos) -> const float * { - return pos == 0 ? raw_logits : raw_logits + (pos - 1) * n_vocab; - }; - - int64_t time_start_sampling = ggml_time_us(); - - mask_positions.clear(); - for (int32_t i = 0; i < max_length; i++) { - if (output_tokens[i] == params.mask_token_id) { - mask_positions.push_back(i); - } - } - - if (mask_positions.empty()) { - break; - } - - float t = timesteps[step]; - float s = timesteps[step + 1]; - - if (params.algorithm == DIFFUSION_ALG_ORIGIN) { - float p_transfer = (step < params.steps - 1) ? (1.0f - s / t) : 1.0f; - - for (int32_t pos : mask_positions) { - if (std::uniform_real_distribution(0.0f, 1.0f)(rng) < p_transfer) { - const float * pos_logits = get_logits_for_pos(pos); - for (int32_t token_id = 0; token_id < n_vocab; token_id++) { - candidates[token_id].id = token_id; - candidates[token_id].logit = pos_logits[token_id]; - candidates[token_id].p = 0.0f; - } - - llama_token_data_array cur_p = { - /* .data = */ candidates.data(), - /* .size = */ (size_t) n_vocab, // Reset size to full vocab - /* .selected = */ -1, - /* .sorted = */ false, - }; - - llama_sampler_apply(sampler, &cur_p); - output_tokens[pos] = cur_p.data[cur_p.selected].id; - } - } - } else { - std::vector> confidences; - std::vector sampled_tokens(mask_positions.size()); - - for (size_t i = 0; i < mask_positions.size(); i++) { - int32_t pos = mask_positions[i]; - const float * pos_logits = get_logits_for_pos(pos); - - for (int32_t token_id = 0; token_id < n_vocab; token_id++) { - candidates[token_id].logit = pos_logits[token_id]; - candidates[token_id].p = 0.0f; - candidates[token_id].id = token_id; - } - - llama_token_data_array cur_p = { - /* .data = */ candidates.data(), - /* .size = */ candidates.size(), - /* .selected = */ -1, - /* .sorted = */ false, - }; - - llama_sampler_apply(sampler, &cur_p); - - llama_token sampled_token = cur_p.data[cur_p.selected].id; - - float confidence = 0.0f; - if (params.algorithm == DIFFUSION_ALG_ENTROPY) { - const float epsilon = 1e-10f; - for (size_t j = 0; j < cur_p.size; j++) { - float prob = cur_p.data[j].p; - confidence += prob * logf(prob + epsilon); - } - } else if (params.algorithm == DIFFUSION_ALG_TOPK_MARGIN) { - confidence = cur_p.data[0].p - cur_p.data[1].p; - } else { - confidence = cur_p.data[cur_p.selected].p; - } - - sampled_tokens[i] = sampled_token; - confidences.emplace_back(confidence, i); - } - - int32_t num_transfer = - (step < params.steps - 1) ? (int32_t) (mask_positions.size() * (1.0f - s / t)) : mask_positions.size(); - - if (num_transfer > 0) { - if (params.alg_temp == 0.0f) { - std::partial_sort(confidences.begin(), confidences.begin() + num_transfer, confidences.end(), - [](const std::pair & a, const std::pair & b) { - if (a.first != b.first) { - return a.first > b.first; - } - return a.second < b.second; - }); - } else { - conf_candidates.clear(); - - for (int32_t pos = 0; pos < max_length; pos++) { - float conf_logit = -std::numeric_limits::infinity(); - - auto it = std::find(mask_positions.begin(), mask_positions.end(), pos); - if (it != mask_positions.end()) { - size_t mask_idx = std::distance(mask_positions.begin(), it); - conf_logit = confidences[mask_idx].first / params.alg_temp; // Apply temperature scaling - } - - conf_candidates.emplace_back(llama_token_data{ pos, conf_logit, 0.0f }); - } - - llama_token_data_array conf_array = { - /* .data = */ conf_candidates.data(), - /* .size = */ conf_candidates.size(), - /* .selected = */ -1, - /* .sorted = */ false, - }; - - for (int32_t i = 0; i < num_transfer; i++) { - // Apply distribution sampler to get selected index - llama_sampler_apply(dist_sampler, &conf_array); - int selected_idx = conf_array.selected; - confidences[i].second = conf_candidates[selected_idx].id; - - conf_candidates[selected_idx].p = 0.0f; - conf_array.selected = -1; - } - } - - if (params.alg_temp == 0.0f) { - // Deterministic - use confidence order - for (int32_t i = 0; i < num_transfer; i++) { - int32_t mask_idx = confidences[i].second; - int32_t pos = mask_positions[mask_idx]; - llama_token token = sampled_tokens[mask_idx]; - output_tokens[pos] = token; - } - } else { - for (int32_t i = 0; i < num_transfer; i++) { - int32_t pos = confidences[i].second; - auto it = std::find(mask_positions.begin(), mask_positions.end(), pos); - if (it != mask_positions.end()) { - int32_t mask_idx = std::distance(mask_positions.begin(), it); - output_tokens[pos] = sampled_tokens[mask_idx]; - } - } - } - } - } - int64_t time_end_sampling = ggml_time_us(); - total_sampling_time += time_end_sampling - time_start_sampling; - } - int64_t time_end = ggml_time_us(); - total_time += time_end - time_start; - - LOG_INF("\ntotal time: %0.2fms, time per step: %0.2fms, sampling time per step: %0.2fms\n", - total_time / 1000.0, total_time / 1000.0 / params.steps, total_sampling_time / 1000.0 / params.steps); - - - llama_batch_free(batch); - llama_sampler_free(sampler); - llama_sampler_free(dist_sampler); - - n_generated = max_length; -} - - - - -static std::string format_input_text(const std::string & prompt, bool use_chat_template, llama_model * model) { - if (!use_chat_template) { - return prompt; - } - - auto chat_templates = common_chat_templates_init(model, ""); - - common_chat_templates_inputs inputs; - common_chat_msg user_msg; - user_msg.role = "user"; - user_msg.content = prompt; - inputs.add_generation_prompt = true; - inputs.messages.push_back(user_msg); - - auto result = common_chat_templates_apply(chat_templates.get(), inputs); - - return result.prompt; -} - struct callback_data { - const common_params_diffusion * diff_params; - const llama_vocab * vocab; - int32_t n_input; + diffusion_params * diff_params; + const llama_vocab * vocab; + int32_t n_input; }; -static bool diffusion_step_callback(int32_t step, - int32_t total_steps, +static float calculate_confidence(const llama_token_data_array & cur_p, + diffusion_algorithm algorithm, + std::mt19937 & rng) { + switch (algorithm) { + case CONFIDENCE_BASED: + return cur_p.data[cur_p.selected].p; // Selected token probability + + case ENTROPY_BASED: + { + float entropy = 0.0f; + const float epsilon = 1e-10f; + for (size_t i = 0; i < cur_p.size; i++) { + float prob = cur_p.data[i].p; + entropy += prob * logf(prob + epsilon); + } + return -entropy; // Higher entropy = lower confidence + } + + case MARGIN_BASED: + return (cur_p.size > 1) ? cur_p.data[0].p - cur_p.data[1].p : cur_p.data[0].p; + + case RANDOM: + { + std::uniform_real_distribution uniform(0.0f, 1.0f); + return uniform(rng); // Random confidence + } + + case ORIGIN: + return cur_p.data[cur_p.selected].p; + + default: + return 0.0f; + } +} + +// Unified transfer count calculation function +static int32_t calculate_transfer_count(int32_t step, + int32_t total_steps, + int32_t remaining_masked, + transfer_schedule schedule, + float eps, + const std::vector & num_transfer_tokens = {}) { + switch (schedule) { + case TIMESTEP_BASED: + { + float t = 1.0f - (float) step / total_steps * (1.0f - eps); + float s = 1.0f - (float) (step + 1) / total_steps * (1.0f - eps); + float p_transfer = (step < total_steps - 1) ? (1.0f - s / t) : 1.0f; + return (int32_t) (remaining_masked * p_transfer); + } + + case BLOCK_BASED: + if (!num_transfer_tokens.empty() && step < (int32_t) num_transfer_tokens.size()) { + return num_transfer_tokens[step]; + } + return remaining_masked / (total_steps - step); // Fallback + + default: + return remaining_masked / (total_steps - step); + } +} + +static bool diffusion_step_callback(int32_t step, + int32_t total_steps, const llama_token * tokens, - int32_t n_tokens, - void * user_data) { - (void)user_data; + int32_t n_tokens, + void * user_data) { + (void) user_data; callback_data * data = static_cast(user_data); @@ -350,11 +134,11 @@ static bool diffusion_step_callback(int32_t step, int progress_percent = (step * 100) / total_steps; int progress_bars = (step * 50) / total_steps; LOG_INF("\rdiffusion step: %d/%d [%s%s] %d%%", - step, - total_steps, - std::string(progress_bars, '=').c_str(), - std::string(50 - progress_bars, ' ').c_str(), - progress_percent); + step, + total_steps, + std::string(progress_bars, '=').c_str(), + std::string(50 - progress_bars, ' ').c_str(), + progress_percent); }; if (data->diff_params->visual_mode) { @@ -391,6 +175,360 @@ static bool diffusion_step_callback(int32_t step, return true; } +static void add_gumbel_noise(float * logits, int32_t n_vocab, float temperature, std::mt19937 & rng) { + if (temperature == 0.0f) { + return; + } + + std::uniform_real_distribution uniform(0.0, 1.0); + for (int32_t i = 0; i < n_vocab; i++) { + double noise = uniform(rng); + // Prevent log(0) + noise = std::max(noise, 1e-20); + double gumbel_noise = std::pow(-std::log(noise), temperature); + logits[i] = std::exp(logits[i]) / gumbel_noise; + } +} + +static std::vector get_num_transfer_tokens(int32_t mask_count, int32_t steps) { + std::vector num_transfer_tokens(steps); + + int32_t base = mask_count / steps; + int32_t remainder = mask_count % steps; + + for (int32_t i = 0; i < steps; i++) { + num_transfer_tokens[i] = base + (i < remainder ? 1 : 0); + } + + return num_transfer_tokens; +} + +static void diffusion_generate(llama_context * ctx, + const llama_token * input_tokens, + llama_token * output_tokens, + int32_t n_input, + const diffusion_params & params, + int32_t & n_generated) { + n_generated = 0; + if (!ctx || !input_tokens || !output_tokens || n_input <= 0 || params.max_length <= n_input) { + return; + } + + const llama_model * model = llama_get_model(ctx); + + // Initialize with input and pad with mask tokens + std::copy(input_tokens, input_tokens + n_input, output_tokens); + std::fill(output_tokens + n_input, output_tokens + params.max_length, params.mask_token_id); + + std::mt19937 rng(params.seed); + + llama_set_causal_attn(ctx, false); + + int32_t n_vocab = llama_vocab_n_tokens(llama_model_get_vocab(model)); + + std::vector candidates(n_vocab); + std::vector conf_candidates; + conf_candidates.reserve(params.max_length); + std::vector mask_positions; + mask_positions.reserve(params.max_length); + + // Setup sampler chain + struct llama_sampler * sampler = llama_sampler_chain_init(llama_sampler_chain_default_params()); + if (params.top_k > 0) { + llama_sampler_chain_add(sampler, llama_sampler_init_top_k(params.top_k)); + } + if (params.top_p < 1.0f) { + llama_sampler_chain_add(sampler, llama_sampler_init_top_p(params.top_p, 1)); + } + if (params.temperature > 0.0f) { + llama_sampler_chain_add(sampler, llama_sampler_init_temp(params.temperature)); + } + llama_sampler_chain_add(sampler, llama_sampler_init_dist(params.seed)); + + struct llama_sampler * dist_sampler = llama_sampler_init_dist(params.seed); + + llama_batch batch = llama_batch_init(params.max_length, 0, 1); + batch.n_tokens = params.max_length; + + // Pre-allocate buffers for CFG if needed + int32_t logits_size = n_vocab * params.max_length; + std::vector cond_logits_buffer; + std::vector un_x_buffer; + if (params.cfg_scale > 0.0f) { + cond_logits_buffer.resize(logits_size); + un_x_buffer.resize(params.max_length); + } + + // For block-based processing + std::vector num_transfer_tokens; + int32_t num_blocks = 1; + int32_t steps_per_block = params.steps; + + if (params.schedule == BLOCK_BASED) { + GGML_ASSERT(params.max_length % params.block_length == 0); + num_blocks = params.max_length / params.block_length; + GGML_ASSERT(params.steps % num_blocks == 0); + steps_per_block = params.steps / num_blocks; + } + + std::vector confidence(params.max_length); + + int64_t total_sampling_time = 0; + int64_t total_time = 0; + int64_t time_start = ggml_time_us(); + + for (int block_num = 0; block_num < num_blocks; block_num++) { + int32_t block_start = (params.schedule == BLOCK_BASED) ? n_input + block_num * params.block_length : 0; + int32_t block_end = (params.schedule == BLOCK_BASED) ? + std::min(n_input + (block_num + 1) * params.block_length, params.max_length) : + params.max_length; + + // Count masked tokens in current block for block-based processing + if (params.schedule == BLOCK_BASED) { + int32_t block_mask_count = 0; + for (int i = block_start; i < block_end; i++) { + if (output_tokens[i] == params.mask_token_id) { + block_mask_count++; + } + } + num_transfer_tokens = get_num_transfer_tokens(block_mask_count, steps_per_block); + } + + for (int32_t step = 0; step < steps_per_block; step++) { + int32_t global_step = block_num * steps_per_block + step; + + if (params.step_callback) { + if (!params.step_callback( + global_step, params.steps, output_tokens, params.max_length, params.step_callback_user_data)) { + break; + } + } + + // Setup batch + for (int32_t i = 0; i < params.max_length; i++) { + batch.token[i] = output_tokens[i]; + batch.pos[i] = i; + batch.n_seq_id[i] = 1; + batch.seq_id[i][0] = 0; + batch.logits[i] = 1; + } + + float * logits = nullptr; + + if (params.cfg_scale > 0.0f) { + int ret = llama_decode(ctx, batch); + if (ret != 0) { + LOG_ERR("Failed to generate conditional"); + break; + } + float * cond_logits_ptr = llama_get_logits(ctx); + std::memcpy(cond_logits_buffer.data(), cond_logits_ptr, logits_size * sizeof(float)); + + // Unconditional generation (mask input) + std::copy(output_tokens, output_tokens + params.max_length, un_x_buffer.begin()); + for (int32_t i = 0; i < n_input; i++) { + un_x_buffer[i] = params.mask_token_id; + } + + for (int32_t i = 0; i < params.max_length; i++) { + batch.token[i] = un_x_buffer[i]; + } + ret = llama_decode(ctx, batch); + if (ret != 0) { + LOG_ERR("Failed to generate unconditional"); + break; + } + float * uncond_logits = llama_get_logits(ctx); + + // Apply CFG + for (int32_t i = 0; i < logits_size; i++) { + cond_logits_buffer[i] = + uncond_logits[i] + (params.cfg_scale + 1.0f) * (cond_logits_buffer[i] - uncond_logits[i]); + } + logits = cond_logits_buffer.data(); + } else { + int ret = llama_decode(ctx, batch); + if (ret != 0) { + LOG_ERR("%s: failed to decode at step %d, ret = %d\n", __func__, global_step, ret); + break; + } + logits = llama_get_logits(ctx); + } + + if (!logits) { + LOG_ERR("%s: failed to get logits at step %d\n", __func__, global_step); + break; + } + + auto get_logits_for_pos = [&](int32_t pos) -> const float * { + if (params.shift_logits) { + return pos == 0 ? logits : logits + (pos - 1) * n_vocab; + } + return logits + (pos) *n_vocab; + }; + + int64_t time_start_sampling = ggml_time_us(); + + mask_positions.clear(); + for (int32_t i = 0; i < params.max_length; i++) { + if (output_tokens[i] == params.mask_token_id) { + // For block-based, only consider current block + if (params.schedule != BLOCK_BASED || (i >= block_start && i < block_end)) { + mask_positions.push_back(i); + } + } + } + + if (mask_positions.empty()) { + break; + } + + if (params.add_gumbel_noise && params.temperature > 0.0f) { + add_gumbel_noise(logits, n_vocab, params.temperature, rng); + } + + if (params.algorithm == ORIGIN) { + int32_t transfer_count = calculate_transfer_count( + step, steps_per_block, mask_positions.size(), params.schedule, params.eps, num_transfer_tokens); + float p_transfer = (float) transfer_count / mask_positions.size(); + + for (int32_t pos : mask_positions) { + if (std::uniform_real_distribution(0.0f, 1.0f)(rng) < p_transfer) { + const float * pos_logits = get_logits_for_pos(pos); + for (int32_t token_id = 0; token_id < n_vocab; token_id++) { + candidates[token_id].id = token_id; + candidates[token_id].logit = pos_logits[token_id]; + candidates[token_id].p = 0.0f; + } + + llama_token_data_array cur_p = { + candidates.data(), + (size_t) n_vocab, + -1, + false, + }; + + llama_sampler_apply(sampler, &cur_p); + output_tokens[pos] = cur_p.data[cur_p.selected].id; + } + } + } else { + std::vector> confidences; + std::vector sampled_tokens(mask_positions.size()); + + for (size_t i = 0; i < mask_positions.size(); i++) { + int32_t pos = mask_positions[i]; + const float * pos_logits = get_logits_for_pos(pos); + + for (int32_t token_id = 0; token_id < n_vocab; token_id++) { + candidates[token_id].logit = pos_logits[token_id]; + candidates[token_id].p = 0.0f; + candidates[token_id].id = token_id; + } + + llama_token_data_array cur_p = { + candidates.data(), + candidates.size(), + -1, + false, + }; + + llama_sampler_apply(sampler, &cur_p); + llama_token sampled_token = cur_p.data[cur_p.selected].id; + + float conf = calculate_confidence(cur_p, params.algorithm, rng); + + sampled_tokens[i] = sampled_token; + confidences.emplace_back(conf, i); + } + + int32_t transfer_count = calculate_transfer_count( + step, steps_per_block, mask_positions.size(), params.schedule, params.eps, num_transfer_tokens); + + if (transfer_count > 0) { + if (params.alg_temp == 0.0f) { + std::partial_sort(confidences.begin(), + confidences.begin() + std::min(transfer_count, (int32_t) confidences.size()), + confidences.end(), + [](const std::pair & a, const std::pair & b) { + if (a.first != b.first) { + return a.first > b.first; + } + return a.second < b.second; + }); + + for (int32_t i = 0; i < std::min(transfer_count, (int32_t) confidences.size()); i++) { + int32_t mask_idx = confidences[i].second; + int32_t pos = mask_positions[mask_idx]; + output_tokens[pos] = sampled_tokens[mask_idx]; + } + } else { + conf_candidates.clear(); + for (size_t i = 0; i < confidences.size(); i++) { + float conf_logit = confidences[i].first / params.alg_temp; + conf_candidates.emplace_back(llama_token_data{ (int32_t) i, conf_logit, 0.0f }); + } + + llama_token_data_array conf_array = { + conf_candidates.data(), + conf_candidates.size(), + -1, + false, + }; + + for (int32_t i = 0; i < std::min(transfer_count, (int32_t) confidences.size()); i++) { + llama_sampler_apply(dist_sampler, &conf_array); + int32_t selected_idx = conf_array.selected; + int32_t mask_idx = selected_idx; + int32_t pos = mask_positions[mask_idx]; + output_tokens[pos] = sampled_tokens[mask_idx]; + + conf_candidates[selected_idx].p = 0.0f; + conf_array.selected = -1; + } + } + } + } + + int64_t time_end_sampling = ggml_time_us(); + total_sampling_time += time_end_sampling - time_start_sampling; + } + } + + int64_t time_end = ggml_time_us(); + total_time += time_end - time_start; + + LOG_INF("\ntotal time: %0.2fms, time per step: %0.2fms, sampling time per step: %0.2fms\n", + total_time / 1000.0, + total_time / 1000.0 / params.steps, + total_sampling_time / 1000.0 / params.steps); + + llama_batch_free(batch); + llama_sampler_free(sampler); + llama_sampler_free(dist_sampler); + + n_generated = params.max_length; +} + +static std::string format_input_text(const std::string & prompt, bool use_chat_template, llama_model * model) { + if (!use_chat_template) { + return prompt; + } + + auto chat_templates = common_chat_templates_init(model, ""); + + common_chat_templates_inputs inputs; + common_chat_msg user_msg; + user_msg.role = "user"; + user_msg.content = prompt; + inputs.add_generation_prompt = true; + inputs.messages.push_back(user_msg); + + auto result = common_chat_templates_apply(chat_templates.get(), inputs); + + return result.prompt; +} + int main(int argc, char ** argv) { ggml_time_init(); @@ -400,11 +538,6 @@ int main(int argc, char ** argv) { return 1; } - const char * alg_names[] = { "ORIGIN", "MASKGIT_PLUS", "TOPK_MARGIN", "ENTROPY" }; - const char * alg_name = (params.diffusion.algorithm >= 0 && params.diffusion.algorithm <= 3) ? - alg_names[params.diffusion.algorithm] : - "UNKNOWN"; - common_init(); llama_backend_init(); @@ -421,6 +554,12 @@ int main(int argc, char ** argv) { return 1; } + if (!llama_model_is_diffusion(model)) { + LOG_ERR("error: unsupported model for diffusion"); + llama_model_free(model); + return 1; + } + llama_context_params ctx_params = llama_context_default_params(); ctx_params.n_ctx = params.n_ctx; ctx_params.n_batch = params.n_batch; @@ -442,10 +581,12 @@ int main(int argc, char ** argv) { const llama_vocab * vocab = llama_model_get_vocab(model); std::string formatted_prompt = format_input_text(params.prompt, params.enable_chat_template, model); - std::vector input_tokens = common_tokenize(vocab, formatted_prompt, + std::vector input_tokens = common_tokenize(vocab, + formatted_prompt, /*add special tokens*/ true, /*parse special*/ true); - int n_input = input_tokens.size(); + + int n_input = input_tokens.size(); if (n_input >= params.n_ctx) { LOG_ERR("error: input too long (%d tokens), max context is %d\n", n_input, params.n_ctx); @@ -454,44 +595,79 @@ int main(int argc, char ** argv) { return 1; } - struct diffusion_params ldiff_params = diffusion_default_params(); - ldiff_params.steps = params.diffusion.steps; - ldiff_params.eps = params.diffusion.eps; - ldiff_params.temperature = params.sampling.temp; - ldiff_params.top_p = params.sampling.top_p; - ldiff_params.top_k = params.sampling.top_k; - ldiff_params.algorithm = static_cast(params.diffusion.algorithm); - ldiff_params.alg_temp = params.diffusion.alg_temp; - ldiff_params.seed = params.sampling.seed; - llama_token mask_token_id = llama_vocab_mask(vocab); GGML_ASSERT(mask_token_id != LLAMA_TOKEN_NULL); - LOG_INF("diffusion_params: - %-25s llama_token = %d\n", "mask_token_id", mask_token_id); - LOG_INF("diffusion_params: - %-25s u32 = %d\n", "steps", params.diffusion.steps); - LOG_INF("diffusion_params: - %-25s f32 = %.6f\n", "eps", params.diffusion.eps); - LOG_INF("diffusion_params: - %-25s u32 = %d (%s)\n", "algorithm", params.diffusion.algorithm, - alg_name); - LOG_INF("diffusion_params: - %-25s f32 = %.3f\n", "alg_temp", params.diffusion.alg_temp); - - ldiff_params.mask_token_id = mask_token_id; - - callback_data cb_data = { ¶ms.diffusion, vocab, n_input }; - - ldiff_params.step_callback = diffusion_step_callback; - ldiff_params.step_callback_user_data = &cb_data; - - int32_t n_generated = 0; + bool visual_mode = params.diffusion.visual_mode; + int32_t n_generated = 0; std::vector output_tokens(params.n_ubatch); - diffusion_generate(ctx, input_tokens.data(), output_tokens.data(), n_input, params.n_ubatch, - ldiff_params, n_generated); + + struct diffusion_params diff_params; + + char shift_logits_str[8]; + if (llama_model_meta_val_str(model, "diffusion.shift_logits", shift_logits_str, sizeof(shift_logits_str)) >= 0) { + diff_params.shift_logits = (strcmp(shift_logits_str, "true") == 0); + } else { + diff_params.shift_logits = true; + } + + //Use either eps or block length, but not both + GGML_ASSERT((params.diffusion.eps == 0) ^ (params.diffusion.block_length == 0)); + + if (params.diffusion.eps) { + diff_params.schedule = TIMESTEP_BASED; + diff_params.eps = params.diffusion.eps; + } else if (params.diffusion.block_length) { + diff_params.schedule = BLOCK_BASED; + diff_params.block_length = params.diffusion.block_length; + } + + diff_params.mask_token_id = mask_token_id; + diff_params.seed = params.sampling.seed; + diff_params.temperature = params.sampling.temp; + diff_params.steps = params.diffusion.steps; + diff_params.algorithm = static_cast(params.diffusion.algorithm); + diff_params.max_length = params.n_ubatch; + diff_params.top_p = params.sampling.top_p; + diff_params.top_k = params.sampling.top_k; + diff_params.visual_mode = params.diffusion.visual_mode; + diff_params.add_gumbel_noise = params.diffusion.add_gumbel_noise; + + diff_params.step_callback = diffusion_step_callback; + callback_data cb_data = { &diff_params, vocab, n_input }; + diff_params.step_callback_user_data = &cb_data; + + const char * alg_names[] = { "ORIGIN", "ENTROPY_BASED", "MARGIN_BASED", "RANDOM", "CONFIDENCE_BASED" }; + const char * sched_names[] = { "TIMESTEP_BASED", "BLOCK_BASED" }; + const char * alg_name = + (diff_params.algorithm >= 0 && diff_params.algorithm <= 4) ? alg_names[diff_params.algorithm] : "UNKNOWN"; + const char * sched_name = + (diff_params.schedule >= 0 && diff_params.schedule <= 1) ? sched_names[diff_params.schedule] : "UNKNOWN"; + + LOG_INF("diffusion_params: - %-25s llama_token = %d\n", "mask_token_id", mask_token_id); + LOG_INF("diffusion_params: - %-25s u32 = %d\n", "steps", diff_params.steps); + LOG_INF("diffusion_params: - %-25s u32 = %d\n", "max_length", diff_params.max_length); + LOG_INF("diffusion_params: - %-25s enum = %d (%s)\n", "algorithm", diff_params.algorithm, alg_name); + LOG_INF("diffusion_params: - %-25s enum = %d (%s)\n", "schedule", diff_params.schedule, sched_name); + LOG_INF("diffusion_params: - %-25s f32 = %.3f\n", "temperature", diff_params.temperature); + if (diff_params.schedule == TIMESTEP_BASED) { + LOG_INF("diffusion_params: - %-25s f32 = %.6f\n", "eps", diff_params.eps); + LOG_INF("diffusion_params: - %-25s f32 = %.3f\n", "alg_temp", diff_params.alg_temp); + } + if (diff_params.schedule == BLOCK_BASED) { + LOG_INF("diffusion_params: - %-25s u32 = %d\n", "block_length", diff_params.block_length); + LOG_INF("diffusion_params: - %-25s f32 = %.3f\n", "cfg_scale", diff_params.cfg_scale); + } + + diffusion_generate(ctx, input_tokens.data(), output_tokens.data(), n_input, diff_params, n_generated); if (n_generated > 0) { - if (params.diffusion.visual_mode) { + if (visual_mode) { //clear screen and move cursor to top-left LOG_INF("\033[2J\033[H"); } + output_tokens.erase(output_tokens.begin(), output_tokens.begin() + n_input); std::string output_data = common_detokenize(vocab, output_tokens, false); LOG_INF("\n%s\n", output_data.c_str()); diff --git a/examples/embedding/embedding.cpp b/examples/embedding/embedding.cpp index 40ff648380..9ae7e4dbb0 100644 --- a/examples/embedding/embedding.cpp +++ b/examples/embedding/embedding.cpp @@ -81,6 +81,14 @@ int main(int argc, char ** argv) { params.embedding = true; + // if the number of prompts that would be encoded is known in advance, it's more efficient to specify the + // --parallel argument accordingly. for convenience, if not specified, we fallback to unified KV cache + // in order to support any number of prompts + if (params.n_parallel == 1) { + LOG_INF("%s: n_parallel == 1 -> unified KV cache is enabled\n", __func__); + params.kv_unified = true; + } + // utilize the full context if (params.n_batch < params.n_ctx) { LOG_WRN("%s: setting batch size to %d\n", __func__, params.n_ctx); diff --git a/examples/eval-callback/eval-callback.cpp b/examples/eval-callback/eval-callback.cpp index 4afd80eb45..61eefc7248 100644 --- a/examples/eval-callback/eval-callback.cpp +++ b/examples/eval-callback/eval-callback.cpp @@ -7,6 +7,7 @@ #include #include #include +#include /** * This the arbitrary data which will be passed to each callback. @@ -77,6 +78,12 @@ static void ggml_print_tensor(uint8_t * data, ggml_type type, const int64_t * ne LOG(" ]\n"); LOG(" sum = %f\n", sum); } + + // TODO: make this abort configurable/optional? + if (std::isnan(sum)) { + LOG_ERR("encountered NaN - aborting\n"); + exit(0); + } } /** diff --git a/examples/save-load-state/save-load-state.cpp b/examples/save-load-state/save-load-state.cpp index db79588f1a..1065ec6bb0 100644 --- a/examples/save-load-state/save-load-state.cpp +++ b/examples/save-load-state/save-load-state.cpp @@ -15,6 +15,12 @@ int main(int argc, char ** argv) { return 1; } + if (params.n_parallel == 1) { + // the example uses 2 sequences, so when n_parallel == 1, we need to enable unified kv cache + printf("%s: n_parallel == 1, enabling unified kv cache\n", __func__); + params.kv_unified = true; + } + common_init(); if (params.n_predict < 0) { diff --git a/examples/speculative-simple/speculative-simple.cpp b/examples/speculative-simple/speculative-simple.cpp index 99196c9d04..a8e53f28eb 100644 --- a/examples/speculative-simple/speculative-simple.cpp +++ b/examples/speculative-simple/speculative-simple.cpp @@ -59,13 +59,15 @@ int main(int argc, char ** argv) { } params.cpuparams_batch.n_threads = params.speculative.cpuparams_batch.n_threads; + params.tensor_buft_overrides = params.speculative.tensor_buft_overrides; + common_init_result llama_init_dft = common_init_from_params(params); //model_dft = llama_init_dft.model.get(); ctx_dft = llama_init_dft.context.get(); if (!common_speculative_are_compatible(ctx_tgt, ctx_dft)) { - return 1; + LOG_INF("the draft model '%s' is not compatible with the target model '%s'. tokens will be translated between the draft and target models.\n", params.speculative.model.path.c_str(), params.model.path.c_str()); } // Tokenize the prompt @@ -130,7 +132,10 @@ int main(int argc, char ** argv) { params_spec.n_reuse = llama_n_ctx(ctx_dft) - n_draft; params_spec.p_min = p_min; - struct common_speculative * spec = common_speculative_init(ctx_dft); + struct common_speculative * spec = common_speculative_init(ctx_tgt, ctx_dft); + for (auto &pair : params.speculative.replacements) { + common_speculative_add_replacement_tgt_dft(spec, pair.first.c_str(), pair.second.c_str()); + } llama_batch batch_tgt = llama_batch_init(llama_n_batch(ctx_tgt), 0, 1); diff --git a/examples/speculative/speculative.cpp b/examples/speculative/speculative.cpp index 0adffdb006..8449406a6d 100644 --- a/examples/speculative/speculative.cpp +++ b/examples/speculative/speculative.cpp @@ -85,6 +85,8 @@ int main(int argc, char ** argv) { } params.cpuparams_batch.n_threads = params.speculative.cpuparams_batch.n_threads; + params.tensor_buft_overrides = params.speculative.tensor_buft_overrides; + common_init_result llama_init_dft = common_init_from_params(params); model_dft = llama_init_dft.model.get(); diff --git a/examples/training/finetune.cpp b/examples/training/finetune.cpp index 23bede49b1..416d8d8f6c 100644 --- a/examples/training/finetune.cpp +++ b/examples/training/finetune.cpp @@ -10,20 +10,20 @@ #include #if defined(_MSC_VER) -#pragma warning(disable: 4244 4267) // possible loss of data +#pragma warning(disable: 4244 4267) // possible loss of data #endif int main(int argc, char ** argv) { common_params params; - params.escape = false; - if (!common_params_parse(argc, argv, params, LLAMA_EXAMPLE_PERPLEXITY)) { + if (!common_params_parse(argc, argv, params, LLAMA_EXAMPLE_FINETUNE)) { return 1; } if (params.use_mmap) { - LOG_INF("%s: force disabling memory mapping because it would result in-read-only pointers to the weights\n", __func__); + LOG_INF("%s: force disabling memory mapping because it would result in-read-only pointers to the weights\n", + __func__); params.use_mmap = false; } if (params.cache_type_k != GGML_TYPE_F32) { @@ -38,11 +38,10 @@ int main(int argc, char ** argv) { common_init(); llama_backend_init(); llama_numa_init(params.numa); - // load the model and apply lora adapter, if any - common_init_result llama_init = common_init_from_params(params); - llama_model_ptr & model = llama_init.model; - llama_context_ptr & ctx = llama_init.context; + common_init_result llama_init = common_init_from_params(params); + llama_model_ptr & model = llama_init.model; + llama_context_ptr & ctx = llama_init.context; if (model == NULL) { LOG_ERR("%s: unable to load model\n", __func__); @@ -55,31 +54,32 @@ int main(int argc, char ** argv) { LOG_INF("%s\n", common_params_get_system_info(params).c_str()); } - constexpr float val_split = 0.05f; + std::vector tokens = common_tokenize(ctx.get(), params.prompt, true); + ggml_opt_dataset_t dataset = common_opt_dataset_init(ctx.get(), tokens, llama_n_ctx(ctx.get()) / 2); - std::vector tokens = common_tokenize(ctx.get(), params.prompt, true); - ggml_opt_dataset_t dataset = common_opt_dataset_init(ctx.get(), tokens, llama_n_ctx(ctx.get())/2); + struct lr_opt & lr = params.lr; + LOG_INF("-optimizer %s -lr0 %.2g -wd %.2g -lr-min %.2g -min-epochs %.2g -epochs %d -period %.2g -val %.2g\n", + ggml_opt_optimizer_name(params.optimizer), (double) lr.lr0, (double) lr.wd, (double) lr.lr_min, (double) lr.decay_epochs, + (unsigned) lr.epochs, (double) params.n_batch / params.n_ubatch, (double) params.val_split); - struct ggml_opt_optimizer_params optimizer_params = ggml_opt_get_default_optimizer_params(nullptr); - optimizer_params.adamw.alpha = 1e-7f; // learning rate - - struct llama_opt_params lopt_params { - /*n_ctx_train =*/ 0, - /*param_filter =*/ llama_opt_param_filter_all, - /*param_filter_ud =*/ nullptr, - /*get_opt_pars =*/ ggml_opt_get_constant_optimizer_params, - /*get_opt_pars_ud =*/ &optimizer_params, + struct llama_opt_params lopt_params{ + /*n_ctx_train =*/0, + /*param_filter =*/llama_opt_param_filter_all, + /*param_filter_ud =*/nullptr, + /*get_opt_pars =*/common_opt_lr_pars, + /*get_opt_pars_ud =*/¶ms.lr, + /*optimizer_type =*/params.optimizer, }; llama_opt_init(ctx.get(), model.get(), lopt_params); - const int64_t idata_split = ggml_opt_dataset_ndata(dataset) * (1.0f - val_split); + const int64_t idata_split = ggml_opt_dataset_ndata(dataset) * (1.0f - params.val_split); ggml_opt_result_t result_train = ggml_opt_result_init(); ggml_opt_result_t result_eval = ggml_opt_result_init(); - for (int epoch = 0; epoch < 2; ++epoch) { + for (lr.epoch = 0; lr.epoch < lr.epochs; ++lr.epoch) { llama_opt_epoch(ctx.get(), dataset, result_train, result_eval, idata_split, - ggml_opt_epoch_callback_progress_bar, ggml_opt_epoch_callback_progress_bar); + ggml_opt_epoch_callback_progress_bar, ggml_opt_epoch_callback_progress_bar); fprintf(stderr, "\n"); ggml_opt_result_reset(result_train); @@ -88,7 +88,7 @@ int main(int argc, char ** argv) { ggml_opt_result_free(result_train); ggml_opt_result_free(result_eval); - llama_model_save_to_file(model.get(), "finetuned-model.gguf"); + llama_model_save_to_file(model.get(), params.out_file.c_str()); llama_backend_free(); diff --git a/flake.nix b/flake.nix index 0b5edf911f..bb02c8e52f 100644 --- a/flake.nix +++ b/flake.nix @@ -36,9 +36,6 @@ # ``` # nixConfig = { # extra-substituters = [ - # # Populated by the CI in ggml-org/llama.cpp - # "https://llama-cpp.cachix.org" - # # # A development cache for nixpkgs imported with `config.cudaSupport = true`. # # Populated by https://hercules-ci.com/github/SomeoneSerge/nixpkgs-cuda-ci. # # This lets one skip building e.g. the CUDA-enabled openmpi. @@ -47,10 +44,8 @@ # ]; # # # Verify these are the same keys as published on - # # - https://app.cachix.org/cache/llama-cpp # # - https://app.cachix.org/cache/cuda-maintainers # extra-trusted-public-keys = [ - # "llama-cpp.cachix.org-1:H75X+w83wUKTIPSO1KWy9ADUrzThyGs8P5tmAbkWhQc=" # "cuda-maintainers.cachix.org-1:0dq3bujKpuEPMCX6U4WylrUDZ9JyUG0VpVZa7CNfq5E=" # ]; # }; diff --git a/ggml/CMakeLists.txt b/ggml/CMakeLists.txt index de6d789c98..1fb7abeaf0 100644 --- a/ggml/CMakeLists.txt +++ b/ggml/CMakeLists.txt @@ -39,8 +39,9 @@ if (WIN32) set(CMAKE_SHARED_MODULE_PREFIX "") endif() -option(BUILD_SHARED_LIBS "ggml: build shared libraries" ${BUILD_SHARED_LIBS_DEFAULT}) -option(GGML_BACKEND_DL "ggml: build backends as dynamic libraries (requires BUILD_SHARED_LIBS)" OFF) +option(BUILD_SHARED_LIBS "ggml: build shared libraries" ${BUILD_SHARED_LIBS_DEFAULT}) +option(GGML_BACKEND_DL "ggml: build backends as dynamic libraries (requires BUILD_SHARED_LIBS)" OFF) +set(GGML_BACKEND_DIR "" CACHE PATH "ggml: directory to load dynamic backends from (requires GGML_BACKEND_DL") # # option list @@ -131,7 +132,7 @@ option(GGML_RVV "ggml: enable rvv" ON) option(GGML_RV_ZFH "ggml: enable riscv zfh" OFF) option(GGML_XTHEADVECTOR "ggml: enable xtheadvector" OFF) option(GGML_VXE "ggml: enable vxe" ON) -option(GGML_NNPA "ggml: enable nnpa" ON) +option(GGML_NNPA "ggml: enable nnpa" OFF) # temp disabled by default, see: https://github.com/ggml-org/llama.cpp/issues/14877 option(GGML_CPU_ALL_VARIANTS "ggml: build all variants of the CPU backend (requires GGML_BACKEND_DL)" OFF) set(GGML_CPU_ARM_ARCH "" CACHE STRING "ggml: CPU architecture for ARM") @@ -174,6 +175,10 @@ option(GGML_HIP_GRAPHS "ggml: use HIP graph, experimental, option(GGML_HIP_NO_VMM "ggml: do not try to use HIP VMM" ON) option(GGML_HIP_ROCWMMA_FATTN "ggml: enable rocWMMA for FlashAttention" OFF) option(GGML_HIP_FORCE_ROCWMMA_FATTN_GFX12 "ggml: enable rocWMMA FlashAttention on GFX12" OFF) +option(GGML_HIP_MMQ_MFMA "ggml: enable MFMA MMA for CDNA in MMQ" ON) +option(GGML_HIP_EXPORT_METRICS "ggml: enable kernel perf metrics output" OFF) +option(GGML_MUSA_GRAPHS "ggml: use MUSA graph, experimental, unstable" OFF) +option(GGML_MUSA_MUDNN_COPY "ggml: enable muDNN for accelerated copy" OFF) option(GGML_VULKAN "ggml: use Vulkan" OFF) option(GGML_VULKAN_CHECK_RESULTS "ggml: run Vulkan op checks" OFF) option(GGML_VULKAN_DEBUG "ggml: enable Vulkan debug output" OFF) diff --git a/ggml/cmake/ggml-config.cmake.in b/ggml/cmake/ggml-config.cmake.in index 8c2dc31c6d..91c9d5cd34 100644 --- a/ggml/cmake/ggml-config.cmake.in +++ b/ggml/cmake/ggml-config.cmake.in @@ -1,152 +1,191 @@ +@PACKAGE_INIT@ @GGML_VARIABLES_EXPANDED@ -@PACKAGE_INIT@ - -set_and_check(GGML_INCLUDE_DIR "@PACKAGE_GGML_INCLUDE_INSTALL_DIR@") -set_and_check(GGML_LIB_DIR "@PACKAGE_GGML_LIB_INSTALL_DIR@") -#set_and_check(GGML_BIN_DIR "@PACKAGE_GGML_BIN_INSTALL_DIR@") - -find_package(Threads REQUIRED) - -find_library(GGML_LIBRARY ggml - REQUIRED - HINTS ${GGML_LIB_DIR} - NO_CMAKE_FIND_ROOT_PATH) - -add_library(ggml::ggml UNKNOWN IMPORTED) -set_target_properties(ggml::ggml - PROPERTIES - IMPORTED_LOCATION "${GGML_LIBRARY}") - -find_library(GGML_BASE_LIBRARY ggml-base - REQUIRED - HINTS ${GGML_LIB_DIR} - NO_CMAKE_FIND_ROOT_PATH) - -add_library(ggml::ggml-base UNKNOWN IMPORTED) -set_target_properties(ggml::ggml-base - PROPERTIES - IMPORTED_LOCATION "${GGML_BASE_LIBRARY}") - +# Find all dependencies before creating any target. +include(CMakeFindDependencyMacro) +find_dependency(Threads) if (NOT GGML_SHARED_LIB) + set(GGML_CPU_INTERFACE_LINK_LIBRARIES "") + set(GGML_CPU_INTERFACE_LINK_OPTIONS "") + if (APPLE AND GGML_ACCELERATE) - find_library(ACCELERATE_FRAMEWORK Accelerate REQUIRED) + find_library(ACCELERATE_FRAMEWORK Accelerate) + if(NOT ACCELERATE_FRAMEWORK) + set(${CMAKE_FIND_PACKAGE_NAME}_FOUND 0) + return() + endif() list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES ${ACCELERATE_FRAMEWORK}) endif() - if (GGML_OPENMP) - find_package(OpenMP REQUIRED) + if (GGML_OPENMP_ENABLED) + find_dependency(OpenMP) list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES OpenMP::OpenMP_C OpenMP::OpenMP_CXX) endif() if (GGML_CPU_HBM) - find_library(memkind memkind REQUIRED) + find_library(memkind memkind) + if(NOT memkind) + set(${CMAKE_FIND_PACKAGE_NAME}_FOUND 0) + return() + endif() list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES memkind) endif() if (GGML_BLAS) - find_package(BLAS REQUIRED) - list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES ${BLAS_LIBRARIES}) - list(APPEND GGML_CPU_INTERFACE_LINK_OPTIONS ${BLAS_LINKER_FLAGS}) + find_dependency(BLAS) + list(APPEND GGML_BLAS_INTERFACE_LINK_LIBRARIES ${BLAS_LIBRARIES}) + list(APPEND GGML_BLAS_INTERFACE_LINK_OPTIONS ${BLAS_LINKER_FLAGS}) endif() if (GGML_CUDA) - find_package(CUDAToolkit REQUIRED) + set(GGML_CUDA_INTERFACE_LINK_LIBRARIES "") + find_dependency(CUDAToolkit) + if (GGML_STATIC) + list(APPEND GGML_CUDA_INTERFACE_LINK_LIBRARIES $) + if (WIN32) + list(APPEND GGML_CUDA_INTERFACE_LINK_LIBRARIES $ $) + else() + list(APPEND GGML_CUDA_INTERFACE_LINK_LIBRARIES $ $) + endif() + endif() + if (NOT GGML_CUDA_NO_VMM) + list(APPEND GGML_CUDA_INTERFACE_LINK_LIBRARIES $) + endif() endif() if (GGML_METAL) - find_library(FOUNDATION_LIBRARY Foundation REQUIRED) - find_library(METAL_FRAMEWORK Metal REQUIRED) - find_library(METALKIT_FRAMEWORK MetalKit REQUIRED) + find_library(FOUNDATION_LIBRARY Foundation) + find_library(METAL_FRAMEWORK Metal) + find_library(METALKIT_FRAMEWORK MetalKit) + if(NOT FOUNDATION_LIBRARY OR NOT METAL_FRAMEWORK OR NOT METALKIT_FRAMEWORK) + set(${CMAKE_FIND_PACKAGE_NAME}_FOUND 0) + return() + endif() + set(GGML_METAL_INTERFACE_LINK_LIBRARIES + ${FOUNDATION_LIBRARY} ${METAL_FRAMEWORK} ${METALKIT_FRAMEWORK}) + endif() - list(APPEND GGML_METAL_INTERFACE_LINK_LIBRARIES - ${FOUNDATION_LIBRARY} ${METAL_FRAMEWORK} ${METALKIT_FRAMEWORK}) + if (GGML_OPENCL) + find_dependency(OpenCL) + set(GGML_OPENCL_INTERFACE_LINK_LIBRARIES $) endif() if (GGML_VULKAN) - find_package(Vulkan REQUIRED) - list(APPEND GGML_VULKAN_INTERFACE_LINK_LIBRARIES Vulkan::Vulkan) + find_dependency(Vulkan) + set(GGML_VULKAN_INTERFACE_LINK_LIBRARIES $) endif() if (GGML_HIP) - find_package(hip REQUIRED) - find_package(hipblas REQUIRED) - find_package(rocblas REQUIRED) - list(APPEND GGML_HIP_INTERFACE_LINK_LIBRARIES hip::host roc::rocblas roc::hipblas) + find_dependency(hip) + find_dependency(hipblas) + find_dependency(rocblas) + set(GGML_HIP_INTERFACE_LINK_LIBRARIES hip::host roc::rocblas roc::hipblas) endif() if (GGML_SYCL) + set(GGML_SYCL_INTERFACE_LINK_LIBRARIES "") find_package(DNNL) if (${DNNL_FOUND} AND GGML_SYCL_TARGET STREQUAL "INTEL") list(APPEND GGML_SYCL_INTERFACE_LINK_LIBRARIES DNNL::dnnl) endif() if (WIN32) - find_package(IntelSYCL REQUIRED) - find_package(MKL REQUIRED) + find_dependency(IntelSYCL) + find_dependency(MKL) list(APPEND GGML_SYCL_INTERFACE_LINK_LIBRARIES IntelSYCL::SYCL_CXX MKL::MKL MKL::MKL_SYCL) endif() endif() endif() -set(_ggml_all_targets "") -foreach(_ggml_backend ${GGML_AVAILABLE_BACKENDS}) - string(REPLACE "-" "_" _ggml_backend_pfx "${_ggml_backend}") - string(TOUPPER "${_ggml_backend_pfx}" _ggml_backend_pfx) +set_and_check(GGML_INCLUDE_DIR "@PACKAGE_GGML_INCLUDE_INSTALL_DIR@") +set_and_check(GGML_LIB_DIR "@PACKAGE_GGML_LIB_INSTALL_DIR@") +#set_and_check(GGML_BIN_DIR "@PACKAGE_GGML_BIN_INSTALL_DIR@") - find_library(${_ggml_backend_pfx}_LIBRARY ${_ggml_backend} +if(NOT TARGET ggml::ggml) + find_package(Threads REQUIRED) + + find_library(GGML_LIBRARY ggml REQUIRED HINTS ${GGML_LIB_DIR} NO_CMAKE_FIND_ROOT_PATH) - message(STATUS "Found ${${_ggml_backend_pfx}_LIBRARY}") - - add_library(ggml::${_ggml_backend} UNKNOWN IMPORTED) - set_target_properties(ggml::${_ggml_backend} + add_library(ggml::ggml UNKNOWN IMPORTED) + set_target_properties(ggml::ggml PROPERTIES - INTERFACE_INCLUDE_DIRECTORIES "${GGML_INCLUDE_DIR}" - IMPORTED_LINK_INTERFACE_LANGUAGES "CXX" - IMPORTED_LOCATION "${${_ggml_backend_pfx}_LIBRARY}" - INTERFACE_COMPILE_FEATURES c_std_90 - POSITION_INDEPENDENT_CODE ON) + IMPORTED_LOCATION "${GGML_LIBRARY}") - string(REGEX MATCH "^ggml-cpu" is_cpu_variant "${_ggml_backend}") - if(is_cpu_variant) - list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES "ggml::ggml-base") - set_target_properties(ggml::${_ggml_backend} - PROPERTIES - INTERFACE_LINK_LIBRARIES "${GGML_CPU_INTERFACE_LINK_LIBRARIES}") + find_library(GGML_BASE_LIBRARY ggml-base + REQUIRED + HINTS ${GGML_LIB_DIR} + NO_CMAKE_FIND_ROOT_PATH) - if(GGML_CPU_INTERFACE_LINK_OPTIONS) + add_library(ggml::ggml-base UNKNOWN IMPORTED) + set_target_properties(ggml::ggml-base + PROPERTIES + IMPORTED_LOCATION "${GGML_BASE_LIBRARY}") + + set(_ggml_all_targets "") + if (NOT GGML_BACKEND_DL) + foreach(_ggml_backend ${GGML_AVAILABLE_BACKENDS}) + string(REPLACE "-" "_" _ggml_backend_pfx "${_ggml_backend}") + string(TOUPPER "${_ggml_backend_pfx}" _ggml_backend_pfx) + + find_library(${_ggml_backend_pfx}_LIBRARY ${_ggml_backend} + REQUIRED + HINTS ${GGML_LIB_DIR} + NO_CMAKE_FIND_ROOT_PATH) + + message(STATUS "Found ${${_ggml_backend_pfx}_LIBRARY}") + + add_library(ggml::${_ggml_backend} UNKNOWN IMPORTED) set_target_properties(ggml::${_ggml_backend} PROPERTIES - INTERFACE_LINK_OPTIONS "${GGML_CPU_INTERFACE_LINK_OPTIONS}") - endif() + INTERFACE_INCLUDE_DIRECTORIES "${GGML_INCLUDE_DIR}" + IMPORTED_LINK_INTERFACE_LANGUAGES "CXX" + IMPORTED_LOCATION "${${_ggml_backend_pfx}_LIBRARY}" + INTERFACE_COMPILE_FEATURES c_std_90 + POSITION_INDEPENDENT_CODE ON) - else() - list(APPEND ${_ggml_backend_pfx}_INTERFACE_LINK_LIBRARIES "ggml::ggml-base") - set_target_properties(ggml::${_ggml_backend} - PROPERTIES - INTERFACE_LINK_LIBRARIES "${${_ggml_backend_pfx}_INTERFACE_LINK_LIBRARIES}") - - if(${_ggml_backend_pfx}_INTERFACE_LINK_OPTIONS) - set_target_properties(ggml::${_ggml_backend} + string(REGEX MATCH "^ggml-cpu" is_cpu_variant "${_ggml_backend}") + if(is_cpu_variant) + list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES "ggml::ggml-base") + set_target_properties(ggml::${_ggml_backend} PROPERTIES - INTERFACE_LINK_OPTIONS "${${_ggml_backend_pfx}_INTERFACE_LINK_OPTIONS}") - endif() + INTERFACE_LINK_LIBRARIES "${GGML_CPU_INTERFACE_LINK_LIBRARIES}") + + if(GGML_CPU_INTERFACE_LINK_OPTIONS) + set_target_properties(ggml::${_ggml_backend} + PROPERTIES + INTERFACE_LINK_OPTIONS "${GGML_CPU_INTERFACE_LINK_OPTIONS}") + endif() + + else() + list(APPEND ${_ggml_backend_pfx}_INTERFACE_LINK_LIBRARIES "ggml::ggml-base") + set_target_properties(ggml::${_ggml_backend} + PROPERTIES + INTERFACE_LINK_LIBRARIES "${${_ggml_backend_pfx}_INTERFACE_LINK_LIBRARIES}") + + if(${_ggml_backend_pfx}_INTERFACE_LINK_OPTIONS) + set_target_properties(ggml::${_ggml_backend} + PROPERTIES + INTERFACE_LINK_OPTIONS "${${_ggml_backend_pfx}_INTERFACE_LINK_OPTIONS}") + endif() + endif() + + list(APPEND _ggml_all_targets ggml::${_ggml_backend}) + endforeach() endif() - list(APPEND _ggml_all_targets ggml::${_ggml_backend}) -endforeach() + list(APPEND GGML_INTERFACE_LINK_LIBRARIES ggml::ggml-base "${_ggml_all_targets}") + set_target_properties(ggml::ggml + PROPERTIES + INTERFACE_LINK_LIBRARIES "${GGML_INTERFACE_LINK_LIBRARIES}") -list(APPEND GGML_INTERFACE_LINK_LIBRARIES ggml::ggml-base "${_ggml_all_targets}") -set_target_properties(ggml::ggml - PROPERTIES - INTERFACE_LINK_LIBRARIES "${GGML_INTERFACE_LINK_LIBRARIES}") + add_library(ggml::all INTERFACE IMPORTED) + set_target_properties(ggml::all + PROPERTIES + INTERFACE_LINK_LIBRARIES "${_ggml_all_targets}") -add_library(ggml::all INTERFACE IMPORTED) -set_target_properties(ggml::all - PROPERTIES - INTERFACE_LINK_LIBRARIES "${_ggml_all_targets}") +endif() check_required_components(ggml) diff --git a/ggml/include/ggml-opt.h b/ggml/include/ggml-opt.h index 74ec080a05..4703a05afe 100644 --- a/ggml/include/ggml-opt.h +++ b/ggml/include/ggml-opt.h @@ -74,16 +74,26 @@ extern "C" { GGML_OPT_BUILD_TYPE_OPT = 30, }; + enum ggml_opt_optimizer_type { + GGML_OPT_OPTIMIZER_TYPE_ADAMW, + GGML_OPT_OPTIMIZER_TYPE_SGD, + + GGML_OPT_OPTIMIZER_TYPE_COUNT + }; + // parameters that control which optimizer is used and how said optimizer tries to find the minimal loss struct ggml_opt_optimizer_params { - // AdamW optimizer parameters struct { float alpha; // learning rate - float beta1; - float beta2; + float beta1; // first AdamW momentum + float beta2; // second AdamW momentum float eps; // epsilon for numerical stability - float wd; // weight decay for AdamW, use 0.0f to disable + float wd; // weight decay - 0.0f to disable } adamw; + struct { + float alpha; // learning rate + float wd; // weight decay + } sgd; }; // callback to calculate optimizer parameters prior to a backward pass @@ -112,8 +122,11 @@ extern "C" { int32_t opt_period; // after how many gradient accumulation steps an optimizer step should be done - ggml_opt_get_optimizer_params get_opt_pars; // callback for calculating optimizer parameters - void * get_opt_pars_ud; // userdata for calculating optimizer parameters + ggml_opt_get_optimizer_params get_opt_pars; // callback for calculating optimizer parameters + void * get_opt_pars_ud; // userdata for calculating optimizer parameters + + // only GGML_OPT_OPTIMIZER_TYPE_ADAMW needs m, v momenta per parameter tensor + enum ggml_opt_optimizer_type optimizer; }; // get parameters for an optimization context with defaults set where possible @@ -142,6 +155,10 @@ extern "C" { // get the gradient accumulator for a node from the forward graph GGML_API struct ggml_tensor * ggml_opt_grad_acc(ggml_opt_context_t opt_ctx, struct ggml_tensor * node); + GGML_API enum ggml_opt_optimizer_type ggml_opt_context_optimizer_type(ggml_opt_context_t); //TODO consistent naming scheme + + GGML_API const char * ggml_opt_optimizer_name(enum ggml_opt_optimizer_type); + // ====== Optimization Result ====== GGML_API ggml_opt_result_t ggml_opt_result_init(void); @@ -226,12 +243,14 @@ extern "C" { struct ggml_tensor * outputs, // output tensor, must have shape [ne_label, ndata_batch] if labels are used ggml_opt_dataset_t dataset, // dataset with data and optionally also labels enum ggml_opt_loss_type loss_type, // loss to minimize + enum ggml_opt_optimizer_type optimizer, // sgd or adamw ggml_opt_get_optimizer_params get_opt_pars, // callback to get optimizer params, userdata is pointer to epoch (of type int64_t) int64_t nepoch, // how many times the dataset should be iterated over int64_t nbatch_logical, // datapoints optimizer step, must be a multiple of ndata_batch in inputs/outputs float val_split, // fraction of the dataset to use for validation, must be in [0.0f, 1.0f) bool silent); // whether or not info prints to stderr should be suppressed + #ifdef __cplusplus } #endif diff --git a/ggml/include/ggml.h b/ggml/include/ggml.h index 8a8775be36..da8813fd27 100644 --- a/ggml/include/ggml.h +++ b/ggml/include/ggml.h @@ -241,6 +241,8 @@ #define GGML_ROPE_TYPE_MROPE 8 #define GGML_ROPE_TYPE_VISION 24 +#define GGML_MROPE_SECTIONS 4 + #define GGML_UNUSED(x) (void)(x) #define GGML_PAD(x, n) (((x) + (n) - 1) & ~((n) - 1)) @@ -304,6 +306,16 @@ GGML_TENSOR_LOCALS(int64_t, ne, dst, ne) \ GGML_TENSOR_LOCALS(size_t, nb, dst, nb) +#define GGML_TENSOR_TERNARY_OP_LOCALS \ + GGML_TENSOR_LOCALS(int64_t, ne0, src0, ne) \ + GGML_TENSOR_LOCALS(size_t, nb0, src0, nb) \ + GGML_TENSOR_LOCALS(int64_t, ne1, src1, ne) \ + GGML_TENSOR_LOCALS(size_t, nb1, src1, nb) \ + GGML_TENSOR_LOCALS(int64_t, ne2, src2, ne) \ + GGML_TENSOR_LOCALS(size_t, nb2, src2, nb) \ + GGML_TENSOR_LOCALS(int64_t, ne, dst, ne) \ + GGML_TENSOR_LOCALS(size_t, nb, dst, nb) + #define GGML_TENSOR_BINARY_OP_LOCALS01 \ GGML_TENSOR_LOCALS(int64_t, ne0, src0, ne) \ GGML_TENSOR_LOCALS(size_t, nb0, src0, nb) \ @@ -395,7 +407,8 @@ extern "C" { // GGML_TYPE_IQ4_NL_4_4 = 36, // GGML_TYPE_IQ4_NL_4_8 = 37, // GGML_TYPE_IQ4_NL_8_8 = 38, - GGML_TYPE_COUNT = 39, + GGML_TYPE_MXFP4 = 39, // MXFP4 (1 block) + GGML_TYPE_COUNT = 40, }; // precision @@ -430,6 +443,7 @@ extern "C" { GGML_FTYPE_MOSTLY_IQ4_XS = 22, // except 1d tensors GGML_FTYPE_MOSTLY_IQ1_M = 23, // except 1d tensors GGML_FTYPE_MOSTLY_BF16 = 24, // except 1d tensors + GGML_FTYPE_MOSTLY_MXFP4 = 25, // except 1d tensors }; // available tensor operations: @@ -438,6 +452,7 @@ extern "C" { GGML_OP_DUP, GGML_OP_ADD, + GGML_OP_ADD_ID, GGML_OP_ADD1, GGML_OP_ACC, GGML_OP_SUB, @@ -527,6 +542,7 @@ extern "C" { GGML_OP_CROSS_ENTROPY_LOSS, GGML_OP_CROSS_ENTROPY_LOSS_BACK, GGML_OP_OPT_STEP_ADAMW, + GGML_OP_OPT_STEP_SGD, GGML_OP_GLU, @@ -557,6 +573,7 @@ extern "C" { GGML_GLU_OP_REGLU, GGML_GLU_OP_GEGLU, GGML_GLU_OP_SWIGLU, + GGML_GLU_OP_SWIGLU_OAI, GGML_GLU_OP_GEGLU_ERF, GGML_GLU_OP_GEGLU_QUICK, @@ -831,6 +848,13 @@ extern "C" { struct ggml_tensor * b, enum ggml_type type); + // dst[i0, i1, i2] = a[i0, i1, i2] + b[i0, ids[i1, i2]] + GGML_API struct ggml_tensor * ggml_add_id( + struct ggml_context * ctx, + struct ggml_tensor * a, + struct ggml_tensor * b, + struct ggml_tensor * ids); + GGML_API struct ggml_tensor * ggml_add1( struct ggml_context * ctx, struct ggml_tensor * a, @@ -1198,6 +1222,13 @@ extern "C" { struct ggml_tensor * a, struct ggml_tensor * b); + GGML_API struct ggml_tensor * ggml_swiglu_oai( + struct ggml_context * ctx, + struct ggml_tensor * a, + struct ggml_tensor * b, + float alpha, + float limit); + // normalize along rows GGML_API struct ggml_tensor * ggml_norm( struct ggml_context * ctx, @@ -1570,6 +1601,10 @@ extern "C" { float scale, float max_bias); + GGML_API void ggml_soft_max_add_sinks( + struct ggml_tensor * a, + struct ggml_tensor * sinks); + GGML_API struct ggml_tensor * ggml_soft_max_ext_back( struct ggml_context * ctx, struct ggml_tensor * a, @@ -1628,7 +1663,7 @@ extern "C" { struct ggml_tensor * b, struct ggml_tensor * c, int n_dims, - int sections[4], + int sections[GGML_MROPE_SECTIONS], int mode, int n_ctx_orig, float freq_base, @@ -1654,6 +1689,22 @@ extern "C" { float beta_fast, float beta_slow); + GGML_API struct ggml_tensor * ggml_rope_multi_inplace( + struct ggml_context * ctx, + struct ggml_tensor * a, + struct ggml_tensor * b, + struct ggml_tensor * c, + int n_dims, + int sections[GGML_MROPE_SECTIONS], + int mode, + int n_ctx_orig, + float freq_base, + float freq_scale, + float ext_factor, + float attn_factor, + float beta_fast, + float beta_slow); + GGML_DEPRECATED(GGML_API struct ggml_tensor * ggml_rope_custom( struct ggml_context * ctx, struct ggml_tensor * a, @@ -2052,6 +2103,10 @@ extern "C" { GGML_API enum ggml_prec ggml_flash_attn_ext_get_prec( const struct ggml_tensor * a); + GGML_API void ggml_flash_attn_ext_add_sinks( + struct ggml_tensor * a, + struct ggml_tensor * sinks); + // TODO: needs to be adapted to ggml_flash_attn_ext GGML_API struct ggml_tensor * ggml_flash_attn_back( struct ggml_context * ctx, @@ -2257,7 +2312,14 @@ extern "C" { struct ggml_tensor * grad, struct ggml_tensor * m, struct ggml_tensor * v, - struct ggml_tensor * adamw_params); // parameters such a the learning rate + struct ggml_tensor * adamw_params); // parameters such as the learning rate + + // stochastic gradient descent step (with weight decay) + GGML_API struct ggml_tensor * ggml_opt_step_sgd( + struct ggml_context * ctx, + struct ggml_tensor * a, + struct ggml_tensor * grad, + struct ggml_tensor * sgd_params); // alpha, weight decay // // automatic differentiation diff --git a/ggml/src/CMakeLists.txt b/ggml/src/CMakeLists.txt index 0425fd60a9..177fb28213 100644 --- a/ggml/src/CMakeLists.txt +++ b/ggml/src/CMakeLists.txt @@ -214,6 +214,13 @@ add_library(ggml ggml-backend-reg.cpp) add_library(ggml::ggml ALIAS ggml) +if (GGML_BACKEND_DIR) + if (NOT GGML_BACKEND_DL) + message(FATAL_ERROR "GGML_BACKEND_DIR requires GGML_BACKEND_DL") + endif() + target_compile_definitions(ggml PUBLIC GGML_BACKEND_DIR="${GGML_BACKEND_DIR}") +endif() + target_link_libraries(ggml PUBLIC ggml-base) if (CMAKE_SYSTEM_NAME MATCHES "Linux") @@ -227,7 +234,11 @@ function(ggml_add_backend_library backend) set_target_properties(${backend} PROPERTIES LIBRARY_OUTPUT_DIRECTORY ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}) target_compile_definitions(${backend} PRIVATE GGML_BACKEND_DL) add_dependencies(ggml ${backend}) - install(TARGETS ${backend} LIBRARY DESTINATION ${CMAKE_INSTALL_BINDIR}) + if (GGML_BACKEND_DIR) + install(TARGETS ${backend} LIBRARY DESTINATION ${GGML_BACKEND_DIR}) + else() + install(TARGETS ${backend} LIBRARY DESTINATION ${CMAKE_INSTALL_BINDIR}) + endif() else() add_library(${backend} ${ARGN}) target_link_libraries(ggml PUBLIC ${backend}) diff --git a/ggml/src/ggml-alloc.c b/ggml/src/ggml-alloc.c index fcc552da51..8b6e602836 100644 --- a/ggml/src/ggml-alloc.c +++ b/ggml/src/ggml-alloc.c @@ -29,6 +29,7 @@ static bool ggml_op_can_inplace(enum ggml_op op) { case GGML_OP_DIAG_MASK_ZERO: case GGML_OP_DIAG_MASK_INF: case GGML_OP_ADD: + case GGML_OP_ADD_ID: case GGML_OP_ADD1: case GGML_OP_SUB: case GGML_OP_MUL: diff --git a/ggml/src/ggml-backend-reg.cpp b/ggml/src/ggml-backend-reg.cpp index f0cdac31ea..6c31513750 100644 --- a/ggml/src/ggml-backend-reg.cpp +++ b/ggml/src/ggml-backend-reg.cpp @@ -498,6 +498,9 @@ static ggml_backend_reg_t ggml_backend_load_best(const char * name, bool silent, std::vector search_paths; if (user_search_path == nullptr) { +#ifdef GGML_BACKEND_DIR + search_paths.push_back(fs::u8path(GGML_BACKEND_DIR)); +#endif // default search paths: executable directory, current directory search_paths.push_back(get_executable_path()); search_paths.push_back(fs::current_path()); diff --git a/ggml/src/ggml-backend.cpp b/ggml/src/ggml-backend.cpp index b7498b8d40..1b9d29e911 100644 --- a/ggml/src/ggml-backend.cpp +++ b/ggml/src/ggml-backend.cpp @@ -647,6 +647,7 @@ struct ggml_backend_sched { // pipeline parallelism support int n_copies; int cur_copy; + int next_copy; ggml_backend_event_t events[GGML_SCHED_MAX_BACKENDS][GGML_SCHED_MAX_COPIES]; struct ggml_tensor * graph_inputs[GGML_SCHED_MAX_SPLIT_INPUTS]; int n_graph_inputs; @@ -1070,6 +1071,11 @@ static void ggml_backend_sched_split_graph(ggml_backend_sched_t sched, struct gg } } } + // if the node is still unassigned, assign it to the first backend that supports it + for (int b = 0; b < sched->n_backends && *cur_backend_id == -1; b++) { + ggml_backend_sched_set_if_supported(sched, node, b, cur_backend_id); + } + GGML_ASSERT(*cur_backend_id != -1); } // pass 5: split graph, find tensors that need to be copied @@ -1097,7 +1103,7 @@ static void ggml_backend_sched_split_graph(ggml_backend_sched_t sched, struct gg const int node_backend_id = tensor_backend_id(node); - assert(node_backend_id != -1); // all nodes should be assigned by now, this can happen if there is no CPU fallback + GGML_ASSERT(node_backend_id != -1); // all nodes should be assigned by now, this can happen if there is no CPU fallback // check if we should start a new split based on the sources of the current node bool need_new_split = false; @@ -1155,7 +1161,7 @@ static void ggml_backend_sched_split_graph(ggml_backend_sched_t sched, struct gg size_t src_id = hash_id(src); const int src_backend_id = sched->hv_tensor_backend_ids[src_id]; - assert(src_backend_id != -1); // all inputs should be assigned by now + GGML_ASSERT(src_backend_id != -1); // all inputs should be assigned by now if (src->flags & GGML_TENSOR_FLAG_INPUT && sched->n_copies > 1) { if (tensor_id_copy(src_id, src_backend_id, 0) == NULL) { @@ -1433,8 +1439,6 @@ static enum ggml_status ggml_backend_sched_compute_splits(ggml_backend_sched_t s } } - sched->cur_copy = (sched->cur_copy + 1) % sched->n_copies; - return GGML_STATUS_SUCCESS; } @@ -1535,10 +1539,10 @@ void ggml_backend_sched_reset(ggml_backend_sched_t sched) { bool ggml_backend_sched_reserve(ggml_backend_sched_t sched, struct ggml_cgraph * measure_graph) { GGML_ASSERT((int)sched->hash_set.size >= measure_graph->n_nodes + measure_graph->n_leafs); - ggml_backend_sched_split_graph(sched, measure_graph); - ggml_backend_sched_synchronize(sched); + ggml_backend_sched_split_graph(sched, measure_graph); + if (!ggml_gallocr_reserve_n(sched->galloc, &sched->graph, sched->node_backend_ids, sched->leaf_backend_ids)) { return false; } @@ -1550,6 +1554,10 @@ bool ggml_backend_sched_reserve(ggml_backend_sched_t sched, struct ggml_cgraph * bool ggml_backend_sched_alloc_graph(ggml_backend_sched_t sched, struct ggml_cgraph * graph) { GGML_ASSERT((int)sched->hash_set.size >= graph->n_nodes + graph->n_leafs); + GGML_ASSERT(!sched->is_alloc); + + sched->cur_copy = sched->next_copy; + sched->next_copy = (sched->next_copy + 1) % sched->n_copies; ggml_backend_sched_split_graph(sched, graph); @@ -1590,7 +1598,7 @@ void ggml_backend_sched_synchronize(ggml_backend_sched_t sched) { // if the graph is not already allocated, always use copy 0 after a synchronization // this ensures that during generation the same copy is used every time, // which avoids changes in the graph that could cause CUDA or other graphs to be disabled - sched->cur_copy = 0; + sched->next_copy = 0; } } diff --git a/ggml/src/ggml-blas/ggml-blas.cpp b/ggml/src/ggml-blas/ggml-blas.cpp index ec158dfac6..aeac2e5744 100644 --- a/ggml/src/ggml-blas/ggml-blas.cpp +++ b/ggml/src/ggml-blas/ggml-blas.cpp @@ -281,10 +281,10 @@ ggml_backend_t ggml_backend_blas_init(void) { ggml_backend_blas_context * ctx = new ggml_backend_blas_context; ggml_backend_t backend = new ggml_backend { - /* .guid = */ ggml_backend_blas_guid(), - /* .interface = */ blas_backend_i, - /* .device = */ ggml_backend_reg_dev_get(ggml_backend_blas_reg(), 0), - /* .context = */ ctx, + /* .guid = */ ggml_backend_blas_guid(), + /* .iface = */ blas_backend_i, + /* .device = */ ggml_backend_reg_dev_get(ggml_backend_blas_reg(), 0), + /* .context = */ ctx, }; #if defined(OPENBLAS_VERSION) && defined(GGML_USE_OPENMP) diff --git a/ggml/src/ggml-cann/CMakeLists.txt b/ggml/src/ggml-cann/CMakeLists.txt index 7742b39153..aee5e7b06e 100755 --- a/ggml/src/ggml-cann/CMakeLists.txt +++ b/ggml/src/ggml-cann/CMakeLists.txt @@ -31,6 +31,13 @@ string(REGEX MATCH "[0-9]+[a-zA-Z]" SOC_TYPE_MAJOR_SN "${SOC_VERSION}") set(SOC_TYPE_COMPILE_OPTION "ASCEND_${SOC_TYPE_MAJOR_SN}") string(TOUPPER ${SOC_TYPE_COMPILE_OPTION} SOC_TYPE_COMPILE_OPTION) message(STATUS "CANN: SOC_VERSION = ${SOC_VERSION}") +option(USE_ACL_GRAPH "Enable CANN graph execution (ACL graph mode)" OFF) + +if(USE_ACL_GRAPH AND (SOC_TYPE_MAJOR_SN STREQUAL "310P" OR SOC_TYPE_COMPILE_OPTION STREQUAL "ASCEND_310P")) + message(FATAL_ERROR + "CANN Graph (ACL graph mode) is not supported on 310P devices. " + "Please build with -DUSE_ACL_GRAPH=OFF or use a supported SOC.") +endif() if (CANN_INSTALL_DIR) # Only Support Linux. @@ -68,6 +75,13 @@ if (CANN_INSTALL_DIR) target_compile_definitions(ggml-cann PRIVATE "-D${SOC_TYPE_COMPILE_OPTION}") + if (USE_ACL_GRAPH) + target_compile_definitions(ggml-cann PRIVATE USE_ACL_GRAPH) + message(STATUS "CANN: USE_ACL_GRAPH is enabled.") + else() + message(STATUS "CANN: USE_ACL_GRAPH is disabled.") + endif() + message(STATUS "CANN: CANN_INCLUDE_DIRS = ${CANN_INCLUDE_DIRS}") message(STATUS "CANN: CANN_LIBRARIES = ${CANN_LIBRARIES}") else() diff --git a/ggml/src/ggml-cann/acl_tensor.cpp b/ggml/src/ggml-cann/acl_tensor.cpp index f311864d48..8ffac31dd6 100755 --- a/ggml/src/ggml-cann/acl_tensor.cpp +++ b/ggml/src/ggml-cann/acl_tensor.cpp @@ -77,6 +77,8 @@ aclTensor* ggml_cann_create_tensor(const ggml_tensor* tensor, int64_t* ne, for (int i = 0; i < final_dims; i++) { acl_storage_len += (acl_ne[i] - 1) * acl_stride[i]; } + size_t elem_offset = offset / ggml_element_size(tensor); + acl_storage_len += elem_offset; // Reverse ne and stride. std::reverse(acl_ne, acl_ne + final_dims); @@ -84,7 +86,7 @@ aclTensor* ggml_cann_create_tensor(const ggml_tensor* tensor, int64_t* ne, aclTensor* acl_tensor = aclCreateTensor( acl_ne, final_dims, ggml_cann_type_mapping(tensor->type), acl_stride, - offset / ggml_element_size(tensor), format, &acl_storage_len, 1, + elem_offset, format, &acl_storage_len, 1, tensor->data); return acl_tensor; diff --git a/ggml/src/ggml-cann/aclnn_ops.cpp b/ggml/src/ggml-cann/aclnn_ops.cpp index 4d5c2c1825..259a2928b1 100755 --- a/ggml/src/ggml-cann/aclnn_ops.cpp +++ b/ggml/src/ggml-cann/aclnn_ops.cpp @@ -68,6 +68,8 @@ #include #include #include +#include +#include #include #include @@ -99,7 +101,7 @@ void bcast_shape(ggml_tensor * src0, ggml_tensor * src1, ggml_tensor * dst, aclT } } -void ggml_cann_unary_op( +void ggml_cann_op_unary( std::function unary_op, ggml_backend_cann_context& ctx, ggml_tensor* dst) { ggml_tensor* src = dst->src[0]; @@ -111,6 +113,42 @@ void ggml_cann_unary_op( ggml_cann_release_resources(ctx, acl_src, acl_dst); } +void ggml_cann_op_unary_gated( + std::function unary_op, + ggml_backend_cann_context& ctx, ggml_tensor* dst) { + ggml_tensor* src0 = dst->src[0]; + ggml_tensor* src1 = dst->src[1]; + + GGML_ASSERT(ggml_is_contiguous_1(src0)); + GGML_ASSERT(ggml_is_contiguous_1(dst)); + const int32_t swapped = ggml_get_op_params_i32(dst, 1); + + aclTensor* acl_dst = ggml_cann_create_tensor(dst); + aclTensor *acl_src0 = nullptr, *acl_src1 = nullptr; + if(src1) { + GGML_ASSERT(ggml_is_contiguous_1(src1)); + GGML_ASSERT(src0->type == src1->type); + + acl_src0 = ggml_cann_create_tensor(src0); + acl_src1 = ggml_cann_create_tensor(src1); + } else { + int64_t ne[] = {src0->ne[0] / 2, src0->ne[1], src0->ne[2], src0->ne[3]}; + size_t nb[] = {src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3]}; + acl_src0 = ggml_cann_create_tensor(src0, ne, nb, GGML_MAX_DIMS, ACL_FORMAT_ND, 0); + acl_src1 = ggml_cann_create_tensor(src0, ne, nb, GGML_MAX_DIMS, ACL_FORMAT_ND, ne[0] * ggml_element_size(src0)); + if (swapped) { + std::swap(acl_src0, acl_src1); + } + } + + unary_op(ctx, acl_src0, acl_dst); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceMul, acl_dst, acl_src1); + + ggml_cann_release_resources(ctx, acl_src0, acl_dst); + if(src1) + ggml_cann_release_resources(ctx, acl_src1); +} + /** * @brief Repeats elements of a tensor along each dimension according to the * specified repeat array. @@ -715,69 +753,55 @@ static void cann_copy(ggml_backend_cann_context& ctx, aclTensor* acl_src, void ggml_cann_dup(ggml_backend_cann_context& ctx, ggml_tensor* dst) { ggml_tensor* src0 = dst->src[0]; - aclTensor* acl_src = ggml_cann_create_tensor(src0); - aclTensor* acl_dst = ggml_cann_create_tensor(dst); if (ggml_are_same_shape(src0, dst)) { + aclTensor* acl_src = ggml_cann_create_tensor(src0); + aclTensor* acl_dst = ggml_cann_create_tensor(dst); if (dst->type == src0->type) { cann_copy(ctx, acl_src, acl_dst); } else { aclnn_cast(ctx, acl_src, acl_dst, ggml_cann_type_mapping(dst->type)); } + ggml_cann_release_resources(ctx, acl_src, acl_dst); } else { - if (ggml_is_contiguous(src0) && ggml_is_contiguous(dst)) { - if (dst->type == src0->type) { - size_t cpy_size = ggml_nbytes(dst); - ggml_cann_async_memcpy(ctx, dst->data, src0->data, cpy_size, - ACL_MEMCPY_DEVICE_TO_DEVICE); - return; - } else { - ggml_cann_pool_alloc src_buffer_allocator( - ctx.pool(), - ggml_nelements(dst) * ggml_type_size(dst->type)); - void* src_trans_buffer = src_buffer_allocator.get(); - size_t src_trans_nb[GGML_MAX_DIMS]; - src_trans_nb[0] = ggml_type_size(dst->type); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - src_trans_nb[i] = src_trans_nb[i - 1] * src0->ne[i - 1]; - } - aclTensor* src_trans_tensor = ggml_cann_create_tensor( - src_trans_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), src0->ne, src_trans_nb, - GGML_MAX_DIMS); - - aclnn_cast(ctx, acl_src, src_trans_tensor, ggml_cann_type_mapping(dst->type)); - size_t cpy_size = ggml_nbytes(dst); - ggml_cann_async_memcpy(ctx, dst->data, src_trans_buffer, cpy_size, - ACL_MEMCPY_DEVICE_TO_DEVICE); - ggml_cann_release_resources(ctx, src_trans_tensor); - return; - } - } else if (ggml_is_contiguous(dst)) { - ggml_cann_pool_alloc src_buffer_allocator( - ctx.pool(), ggml_nelements(dst) * ggml_type_size(dst->type)); - void* src_trans_buffer = src_buffer_allocator.get(); + void* src_trans_buffer = src0->data; + ggml_cann_pool_alloc src_buffer_allocator; + if (!ggml_is_contiguous(src0)) { + aclTensor* acl_src = ggml_cann_create_tensor(src0); + src_buffer_allocator.alloc(ctx.pool(), + ggml_nelements(src0) * ggml_type_size(src0->type)); + src_trans_buffer = src_buffer_allocator.get(); size_t src_trans_nb[GGML_MAX_DIMS]; - src_trans_nb[0] = ggml_type_size(dst->type); + src_trans_nb[0] = ggml_type_size(src0->type); for (int i = 1; i < GGML_MAX_DIMS; i++) { src_trans_nb[i] = src_trans_nb[i - 1] * src0->ne[i - 1]; } aclTensor* src_trans_tensor = ggml_cann_create_tensor( - src_trans_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), src0->ne, src_trans_nb, + src_trans_buffer, ggml_cann_type_mapping(src0->type), + ggml_type_size(src0->type), src0->ne, src_trans_nb, GGML_MAX_DIMS); - - aclnn_cast(ctx, acl_src, src_trans_tensor, ggml_cann_type_mapping(dst->type)); - - size_t cpy_size = ggml_nbytes(dst); - ggml_cann_async_memcpy(ctx, dst->data, src_trans_buffer, cpy_size, - ACL_MEMCPY_DEVICE_TO_DEVICE); - ggml_cann_release_resources(ctx, src_trans_tensor); - return; - } else { - GGML_ABORT("Unsupport dst is not tontiguous."); + cann_copy(ctx, acl_src, src_trans_tensor); + ggml_cann_release_resources(ctx, acl_src, src_trans_tensor); } + + size_t src_reshape_nb[GGML_MAX_DIMS]; + src_reshape_nb[0] = ggml_type_size(src0->type); + for (int i = 1; i < GGML_MAX_DIMS; i++) { + src_reshape_nb[i] = src_reshape_nb[i - 1] * dst->ne[i - 1]; + } + + aclTensor* trans_acl_src = ggml_cann_create_tensor(src_trans_buffer, + ggml_cann_type_mapping(src0->type),ggml_type_size(src0->type), + dst->ne, src_reshape_nb, GGML_MAX_DIMS, ACL_FORMAT_ND); + aclTensor* acl_dst = ggml_cann_create_tensor(dst); + + if (dst->type == src0->type) { + cann_copy(ctx, trans_acl_src, acl_dst); + } else { + aclnn_cast(ctx, trans_acl_src, acl_dst, ggml_cann_type_mapping(dst->type)); + } + ggml_cann_release_resources(ctx, trans_acl_src, acl_dst); } - ggml_cann_release_resources(ctx, acl_src, acl_dst); + return; } /** @@ -1292,160 +1316,196 @@ static void aclnn_pow_tensor_tensor(ggml_backend_cann_context& ctx, } /** - * @brief Applies the Alibi (Attention with Linear Biases) mechanism to the - * @details This function implements the Alibi mechanism, which introduces - * learnable biases into the attention scores to simulate relative - * position encoding without the need for explicit positional - * embeddings. + * @brief Generate a range of values and apply a scalar base exponentiation. * - * @param ctx The backend CANN context for executing operations. - * @param acl_src The source tensor representing the query or key. - * @param acl_position The position tensor containing relative positions. - * @param acl_dst The destination tensor where the result will be stored. - * @param n_head The number of attention heads. - * @param src_ne The dimensions of the source tensor. - * @param src_nb0 The byte size of the first dimension of the source - tensor. - * @param max_bias The maximum bias value used in the Alibi mechanism. - * @param dst The destination tensor object for additional metadata. + * This function creates an evenly spaced sequence from `start` to `stop` (exclusive), + * with step size `step`, stores it in a temporary buffer, and then computes: * - * The function performs the following steps: - * 1. Calculates the logarithm floor of the number of heads to determine the - base for bias calculation. - * 2. Initializes arrays with arithmetic sequences and fills them with bias - values. - * 3. Computes the bias tensor based on the calculated biases and arithmetic - sequences. - * 4. Reshapes the bias tensor to match the dimensions of the input tensors. - * 5. Multiplies the position tensor by the bias tensor. - * 6. Adds the result of the multiplication to the source tensor to produce the - final output. + * @f[ + * slope[i] = m^{\left( start + i \cdot step \right)}, \quad 0 \le i < size + * @f] + * + * The results are written to the provided @p slope_buffer. + * + * @param ctx CANN backend context for memory allocation and operator execution. + * @param slope_buffer Pointer to the output buffer (float array) for the computed slope values. + * @param m Scalar base for the exponentiation. + * @param size Number of elements in the generated sequence. + * @param start Starting exponent offset. + * @param stop Stopping exponent offset (exclusive). + * @param step Step size for the exponent increment. */ -static void aclnn_alibi(ggml_backend_cann_context& ctx, aclTensor* acl_src, - aclTensor* acl_position, aclTensor* acl_dst, - const int n_head, int64_t* src_ne, const size_t src_nb0, - float max_bias, ggml_tensor* dst) { - const int64_t ne2_ne3 = src_ne[2] * src_ne[3]; - GGML_ASSERT(src_nb0 == sizeof(float)); - GGML_ASSERT(n_head == src_ne[2]); +static void aclnn_get_slope_inner(ggml_backend_cann_context& ctx, void* slope_buffer, + float m, int64_t size, float start, float stop, float step){ + int64_t ne[] = {size}; + size_t nb[] = {sizeof(float)}; - const int n_heads_log2_floor = 1u << (uint32_t)floor(log2(n_head)); + ggml_cann_pool_alloc arange_allocator(ctx.pool(), size * sizeof(float)); + void* arange_buffer = arange_allocator.get(); - float m0 = powf(2.0f, -(max_bias) / n_heads_log2_floor); - float m1 = powf(2.0f, -(max_bias / 2.0f) / n_heads_log2_floor); + aclTensor* arange_tensor = ggml_cann_create_tensor( + arange_buffer, ACL_FLOAT, sizeof(float), ne, nb, 1); + aclnn_arange(ctx, arange_tensor, start, stop, step, size); - // init arange - ggml_cann_pool_alloc arange_allocator(ctx.pool(), - ne2_ne3 * ggml_type_size(dst->type)); - void* tmp_arange_buffer = arange_allocator.get(); + aclTensor* slope_tensor = ggml_cann_create_tensor( + slope_buffer, ACL_FLOAT, sizeof(float), ne, nb, 1); - // arange1: [1, ..., n_heads_log2_floor+1) - float start = 1; - float stop = n_heads_log2_floor + 1; - float step = 1; - int64_t n_elements_arange = n_heads_log2_floor; + aclScalar* sc = aclCreateScalar(&m, aclDataType::ACL_FLOAT); - int64_t tmp_arange1_ne[] = {n_heads_log2_floor}; - size_t tmp_arange1_nb[] = {sizeof(dst->type)}; - aclTensor* tmp_arange1_tensor = ggml_cann_create_tensor( - tmp_arange_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_arange1_ne, tmp_arange1_nb, - GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - - aclnn_arange(ctx, tmp_arange1_tensor, start, stop, step, n_elements_arange); - - aclTensor* tmp_arange2_tensor = nullptr; - if (n_heads_log2_floor < ne2_ne3) { - // arange2: [1, ..., 2 * (k - n_heads_log2_floor) + 1) - start = 1; - stop = 2 * (ne2_ne3 - n_heads_log2_floor) + 1; - step = 2; - n_elements_arange = ne2_ne3 - n_heads_log2_floor; - int64_t tmp_arange2_ne[] = {ne2_ne3 - n_heads_log2_floor}; - size_t tmp_arange2_nb[] = {sizeof(dst->type)}; - - aclTensor* tmp_arange2_tensor = ggml_cann_create_tensor( - (char*)tmp_arange_buffer + - n_heads_log2_floor * ggml_type_size(dst->type), - ggml_cann_type_mapping(dst->type), ggml_type_size(dst->type), - tmp_arange2_ne, tmp_arange2_nb, GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - aclnn_arange(ctx, tmp_arange2_tensor, start, stop, step, - n_elements_arange); - } - - // init mk_base - ggml_cann_pool_alloc mk_base_allocator(ctx.pool(), - ne2_ne3 * ggml_type_size(dst->type)); - void* tmp_mk_base_buffer = mk_base_allocator.get(); - int64_t tmp_mk_base1_ne[] = {n_heads_log2_floor}; - size_t tmp_mk_base1_nb[] = {sizeof(dst->type)}; - aclTensor* tmp_mk_base1_tensor = ggml_cann_create_tensor( - tmp_mk_base_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_mk_base1_ne, tmp_mk_base1_nb, - GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - - aclnn_fill_scalar(ctx, m0, tmp_mk_base1_tensor); - - aclTensor* tmp_mk_base2_tensor = nullptr; - if (n_heads_log2_floor < ne2_ne3) { - int64_t tmp_mk_base2_ne[] = {ne2_ne3 - n_heads_log2_floor}; - size_t tmp_mk_base2_nb[] = {sizeof(dst->type)}; - aclTensor* tmp_mk_base2_tensor = ggml_cann_create_tensor( - (char*)tmp_mk_base_buffer + - n_heads_log2_floor * ggml_type_size(dst->type), - ggml_cann_type_mapping(dst->type), ggml_type_size(dst->type), - tmp_mk_base2_ne, tmp_mk_base2_nb, GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - aclnn_fill_scalar(ctx, m1, tmp_mk_base2_tensor); - } - - // init mk - int64_t tmp_mk_base_ne[] = {ne2_ne3}; - size_t tmp_mk_base_nb[] = {sizeof(dst->type)}; - aclTensor* tmp_mk_base_tensor = ggml_cann_create_tensor( - tmp_mk_base_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_mk_base_ne, tmp_mk_base_nb, - GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - aclTensor* tmp_arange_tensor = ggml_cann_create_tensor( - tmp_arange_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_mk_base_ne, tmp_mk_base_nb, - GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - aclnn_pow_tensor_tensor(ctx, tmp_mk_base_tensor, tmp_arange_tensor); - - // reshape mk - int64_t tmp_mk_ne[] = {1, 1, src_ne[2], src_ne[3]}; - size_t tmp_mk_nb[GGML_MAX_DIMS]; - tmp_mk_nb[0] = ggml_type_size(dst->type); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - tmp_mk_nb[i] = tmp_mk_nb[i - 1] * tmp_mk_ne[i - 1]; - } - aclTensor* tmp_mk_tensor = ggml_cann_create_tensor( - tmp_mk_base_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_mk_ne, tmp_mk_nb, GGML_MAX_DIMS, - ACL_FORMAT_ND); - - // acl_position * mk - int64_t tmp_output_ne[] = {src_ne[0], src_ne[1], src_ne[2], src_ne[3]}; - size_t tmp_output_nb[GGML_MAX_DIMS]; - tmp_output_nb[0] = ggml_type_size(dst->type); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - tmp_output_nb[i] = tmp_output_nb[i - 1] * tmp_output_ne[i - 1]; - } - ggml_cann_pool_alloc output_allocator(ctx.pool(), ggml_nbytes(dst)); - void* tmp_output_buffer = output_allocator.get(); - aclTensor* tmp_output_tensor = ggml_cann_create_tensor( - tmp_output_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_output_ne, tmp_output_nb, GGML_MAX_DIMS, - ACL_FORMAT_ND); - aclnn_mul(ctx, acl_position, tmp_mk_tensor, tmp_output_tensor); - - // add - aclnn_add(ctx, tmp_output_tensor, acl_src, acl_dst); - ggml_cann_release_resources(ctx, tmp_arange1_tensor, tmp_arange2_tensor, - tmp_mk_base1_tensor, tmp_mk_base2_tensor, tmp_mk_base_tensor, - tmp_arange_tensor, tmp_mk_tensor, tmp_output_tensor); + GGML_CANN_CALL_ACLNN_OP(ctx, PowScalarTensor, sc, arange_tensor, slope_tensor); + ggml_cann_release_resources(ctx, sc, arange_tensor, slope_tensor); } -void ggml_cann_cpy(ggml_backend_cann_context& ctx, ggml_tensor* dst) { +/** + * @brief Compute slope values for multiple attention heads based on ALiBi bias parameters. + * + * This function generates slope values for each attention head according to the ALiBi + * (Attention with Linear Biases) method. It splits the computation into two ranges depending + * on whether the head index is less than @p n_head_log2 or not, and uses different base values + * (`m0` and `m1`) for the exponentiation. + * + * @f[ + * slope[h] = + * \begin{cases} + * m_0^{(h + 1)}, & h < n\_head\_log2 \\ + * m_1^{\left( 2 \cdot (h - n\_head\_log2) + 1 \right)}, & h \geq n\_head\_log2 + * \end{cases} + * \quad , \quad \text{if } max\_bias > 0 + * @f] + * + * If @p max_bias <= 0, all slope values are set to 1.0. + * + * @param ctx CANN backend context for memory allocation and operator execution. + * @param n_head Total number of attention heads. + * @param slope_buffer Pointer to the output buffer (float array) for storing slopes. + * @param max_bias Maximum bias value for slope computation. + * +*/ +static void aclnn_get_slope(ggml_backend_cann_context & ctx, int64_t n_head, + void* slope_buffer, float max_bias) { + const int n_head_log2 = 1u << (uint32_t) floor(log2(n_head)); + + float m0 = powf(2.0f, -(max_bias) / n_head_log2); + float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2); + + // const float slope = (max_bias > 0.0f) ? + // h < n_head_log2 ? + // powf(m0, h + 1) : + // powf(m1, 2*(h - n_head_log2) + 1) : + // 1.0f; + // arange1 + float start = 0 + 1; + float end = (n_head_log2 - 1) + 1; + float step = 1; + float count = n_head_log2; + // end needs to be +1 because aclnn uses a left-closed, right-open interval. + aclnn_get_slope_inner(ctx, slope_buffer, m0, count, start, end + 1, step); + if (n_head_log2 < n_head) { + // arange2 + start = 2 * (n_head_log2 - n_head_log2) + 1; + end = 2 * ((n_head - 1) - n_head_log2) + 1; + step = 2; + count = n_head - n_head_log2; + aclnn_get_slope_inner( + ctx, (char *) slope_buffer + n_head_log2 * sizeof(float), + m1, count, start, end + 1, step); + } +} + +/** + * @brief Add ALiBi (Attention with Linear Biases) positional biases to the attention mask. + * + * This function computes the ALiBi slopes for each attention head (if max_bias > 0), + * multiplies them with the attention mask to produce bias tensors, and adds these biases + * to the destination tensor (@p dst). + * + * The function performs necessary broadcasting of the mask and slope tensors to match + * the shape of the destination tensor, then applies element-wise multiplication and addition + * using CANN operators. + * + * @param ctx CANN backend context for memory management and operator execution. + * @param mask Input attention mask tensor, assumed to be contiguous. + * @param dst Destination tensor to which ALiBi biases will be added. + * @param dst_ptr Pointer to the memory of the destination tensor. + * @param max_bias Maximum bias value controlling the slope scaling. + * + * @note + * - Write data into dst_ptr using only the shape information of the dst tensor. + * - `GGML_MAX_DIMS + 2` is used to extend tensor dimensions for broadcasting. + */ +static void aclnn_add_alibi(ggml_backend_cann_context& ctx, ggml_tensor* mask, + ggml_tensor* dst, void* dst_ptr, float max_bias) { + void* slope_buffer = nullptr; + void* bias_buffer = nullptr; + + if (max_bias > 0.0f) { + int64_t n_heads = dst->ne[2]; + ggml_cann_pool_alloc slope_allocator(ctx.pool(), n_heads * sizeof(float)); + slope_buffer = slope_allocator.get(); + ggml_cann_pool_alloc bias_allocator( + ctx.pool(), ggml_nelements(dst) * ggml_element_size(dst)); + bias_buffer = bias_allocator.get(); + aclnn_get_slope(ctx, n_heads, slope_buffer, max_bias); + } + + // broadcast for mask, slop and dst; + int64_t nr2 = dst->ne[2] / mask->ne[2]; + int64_t nr3 = dst->ne[3] / mask->ne[3]; + + // broadcast the mask across rows + int64_t mask_ne[] = { mask->ne[0], dst->ne[1], mask->ne[2], 1, mask->ne[3], 1 }; + size_t mask_nb[] = { + mask_nb[0] = mask->nb[0], mask_nb[1] = mask->nb[1], mask_nb[2] = mask->nb[2], + mask_nb[3] = mask->nb[2], mask_nb[4] = mask->nb[3], mask_nb[5] = mask->nb[3] + }; + + int64_t dst_ne[] = { dst->ne[0], dst->ne[1], mask->ne[2], nr2, mask->ne[3], nr3 }; + size_t dst_nb[] = { + dst_nb[0] = dst->nb[0], dst_nb[1] = dst->nb[1], dst_nb[2] = dst->nb[2], + dst_nb[3] = dst->nb[2], dst_nb[4] = dst->nb[3], dst_nb[5] = dst->nb[3] + }; + + // slope is a 1 dim tensor, slope.ne2 == dst.ne2 + int64_t slope_ne[] = { 1, 1, mask->ne[2], nr2, 1, 1 }; + size_t slope_nb[GGML_MAX_DIMS + 2]; + slope_nb[0] = sizeof(float); + for (int i = 1; i < GGML_MAX_DIMS + 2; i++) { + slope_nb[i] = slope_nb[i - 1] * slope_ne[i - 1]; + } + + aclTensor* acl_slope = ggml_cann_create_tensor( + slope_buffer, ACL_FLOAT, sizeof(float), + slope_ne, slope_nb, GGML_MAX_DIMS + 2); + aclTensor* acl_mask = ggml_cann_create_tensor( + mask, mask_ne, mask_nb, GGML_MAX_DIMS + 2); + + // write data into dst_ptr using only the shape information of the dst tensor. + aclTensor* acl_dst = ggml_cann_create_tensor( + dst_ptr, ggml_cann_type_mapping(dst->type), + ggml_type_size(dst->type), dst_ne, dst_nb, + GGML_MAX_DIMS + 2); + + if (max_bias > 0.0f) { + int64_t bias_ne[] = { mask->ne[0], dst->ne[1], mask->ne[2], nr2, mask->ne[3], 1 }; + size_t bias_nb[GGML_MAX_DIMS + 2]; + bias_nb[0] = sizeof(float); + for (int i = 1; i < GGML_MAX_DIMS + 2; i++) { + bias_nb[i] = bias_nb[i - 1] * bias_ne[i - 1]; + } + aclTensor* bias_tensor = ggml_cann_create_tensor( + bias_buffer, ACL_FLOAT, sizeof(float), + bias_ne, bias_nb, GGML_MAX_DIMS + 2); + + aclnn_mul(ctx, acl_slope, acl_mask, bias_tensor); + aclnn_add(ctx, acl_dst, bias_tensor); + ggml_cann_release_resources(ctx, bias_tensor); + } else { + aclnn_add(ctx, acl_dst, acl_mask); + } + ggml_cann_release_resources(ctx, acl_slope, acl_mask, acl_dst); +} + +void ggml_cann_cpy(ggml_backend_cann_context & ctx, ggml_tensor * dst) { ggml_cann_dup(ctx, dst); } @@ -1463,165 +1523,135 @@ void ggml_cann_cpy(ggml_backend_cann_context& ctx, ggml_tensor* dst) { * @param acl_dst The destination tensor where the softmax results will be * stored. */ -static void aclnn_softmax(ggml_backend_cann_context& ctx, aclTensor* acl_src, - int64_t dim, aclTensor* acl_dst) { +static void aclnn_softmax(ggml_backend_cann_context & ctx, + aclTensor* acl_src, int64_t dim, aclTensor * acl_dst) { GGML_CANN_CALL_ACLNN_OP(ctx, Softmax, acl_src, dim, acl_dst); } -void ggml_cann_softmax(ggml_backend_cann_context& ctx, ggml_tensor* dst) { +void ggml_cann_softmax(ggml_backend_cann_context & ctx, ggml_tensor * dst) { ggml_tensor* src0 = dst->src[0]; ggml_tensor* src1 = dst->src[1]; // mask aclTensor* acl_src0 = ggml_cann_create_tensor(src0); - aclTensor* acl_dst = ggml_cann_create_tensor(dst); + aclTensor* acl_dst = ggml_cann_create_tensor(dst); - float scale = 1.0f; + float scale = 1.0f; float max_bias = 0.0f; - memcpy(&scale, (float*)dst->op_params + 0, sizeof(float)); - memcpy(&max_bias, (float*)dst->op_params + 1, sizeof(float)); + memcpy(&scale, (float *) dst->op_params + 0, sizeof(float)); + memcpy(&max_bias, (float *) dst->op_params + 1, sizeof(float)); // input mul scale aclScalar* acl_scale = aclCreateScalar(&scale, aclDataType::ACL_FLOAT); + ggml_cann_pool_alloc src_tensor_allocator(ctx.pool(), ggml_nbytes(src0)); + void* src_tensor_buffer = src_tensor_allocator.get(); + aclTensor* softmax_tensor = ggml_cann_create_tensor( + src_tensor_buffer, ggml_cann_type_mapping(src0->type), + ggml_element_size(src0), src0->ne, src0->nb,GGML_MAX_DIMS); - size_t n_bytes = ggml_nbytes(src0); - ggml_cann_pool_alloc mul_scale_allocator(ctx.pool(), n_bytes); - void* input_mul_scale_buffer = mul_scale_allocator.get(); - aclTensor* acl_input_mul_scale_tensor = ggml_cann_create_tensor( - input_mul_scale_buffer, ACL_FLOAT, ggml_type_size(src0->type), src0->ne, - src0->nb, GGML_MAX_DIMS); - - bool inplace = false; - aclnn_muls(ctx, acl_src0, scale, acl_input_mul_scale_tensor, inplace); + aclnn_muls(ctx, acl_src0, scale, softmax_tensor, false); // mask - aclTensor* acl_src1_fp32_tensor = nullptr; - aclTensor* tmp_mask_tensor = nullptr; - ggml_cann_pool_alloc src1_fp32_allocator(ctx.pool()); if (src1) { - const bool use_f16 = src1->type == GGML_TYPE_F16; - if (use_f16) { - // cast to fp32 - size_t n_bytes = ggml_nelements(src1) * sizeof(float_t); - size_t src1_fp32_nb[GGML_MAX_DIMS]; - src1_fp32_nb[0] = sizeof(float_t); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - src1_fp32_nb[i] = src1_fp32_nb[i - 1] * src1->ne[i - 1]; - } - src1_fp32_allocator.alloc(n_bytes); - void* src1_fp32_buffer = src1_fp32_allocator.get(); - acl_src1_fp32_tensor = ggml_cann_create_tensor( - src1_fp32_buffer, ACL_FLOAT, sizeof(float), src1->ne, - src1_fp32_nb, GGML_MAX_DIMS); - aclTensor* acl_src1 = ggml_cann_create_tensor(src1); - aclnn_cast(ctx, acl_src1, acl_src1_fp32_tensor, ACL_FLOAT); - ggml_cann_release_resources(ctx, acl_src1); - } else { - acl_src1_fp32_tensor = ggml_cann_create_tensor(src1); - } - - // broadcast the mask across rows, only use ne11 of ne01 in mask - if (src1->ne[1] != src0->ne[1]) { - // mask shape: [1,1,ne11,ne10] - int64_t tmp_mask_ne[] = {src0->ne[0], src0->ne[1], 1, 1}; - size_t tmp_mask_nb[GGML_MAX_DIMS]; - tmp_mask_nb[0] = sizeof(float_t); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - tmp_mask_nb[i] = tmp_mask_nb[i - 1] * tmp_mask_ne[i - 1]; - } - tmp_mask_tensor = ggml_cann_create_tensor( - src1->data, ACL_FLOAT, sizeof(float), tmp_mask_ne, tmp_mask_nb, - GGML_MAX_DIMS, ACL_FORMAT_ND); - } - - // alibi - const int n_head = src0->ne[2]; - const size_t src_nb0 = src0->nb[0]; - - n_bytes = ggml_nbytes(dst); - ggml_cann_pool_alloc output_allocator(ctx.pool(), n_bytes); - void* output_buffer = output_allocator.get(); - aclTensor* alibi_output_tensor = ggml_cann_create_tensor( - output_buffer, ACL_FLOAT, ggml_type_size(dst->type), dst->ne, - dst->nb, GGML_MAX_DIMS); - if (max_bias <= 0.0f) { - // slope = 1.0 - if (tmp_mask_tensor) { - aclnn_add(ctx, tmp_mask_tensor, acl_input_mul_scale_tensor, - alibi_output_tensor); - } else { - aclnn_add(ctx, acl_src1_fp32_tensor, acl_input_mul_scale_tensor, - alibi_output_tensor); - } - } else { - // slope != 1.0 - if (tmp_mask_tensor) { - aclnn_alibi(ctx, acl_input_mul_scale_tensor, tmp_mask_tensor, - alibi_output_tensor, n_head, src0->ne, src_nb0, - max_bias, dst); - } else { - aclnn_alibi(ctx, acl_input_mul_scale_tensor, - acl_src1_fp32_tensor, alibi_output_tensor, n_head, - src0->ne, src_nb0, max_bias, dst); - } - } - - // softmax - aclnn_softmax(ctx, alibi_output_tensor, 3, acl_dst); - ggml_cann_release_resources(ctx, alibi_output_tensor); - } else { - aclnn_softmax(ctx, acl_input_mul_scale_tensor, 3, acl_dst); + aclnn_add_alibi(ctx, src1, src0, src_tensor_buffer, max_bias); } - - ggml_cann_release_resources(ctx, acl_src0, acl_src1_fp32_tensor, acl_dst, - acl_scale, acl_input_mul_scale_tensor, tmp_mask_tensor); + // softmax + aclnn_softmax(ctx, softmax_tensor, 3, acl_dst); + ggml_cann_release_resources(ctx, acl_src0, acl_dst, acl_scale, softmax_tensor); } /** - * @brief Performs embedding operation on a 4D tensor using the CANN backend. + * @brief Performs index select operation on a 4D tensor using the CANN backend. * - * This function extracts slices from the source tensor (`src_buffer`), - * index tensor (`index`), and destination tensor (`dst`), and performs an - * embedding operation on them. The embedding operation is applied by iterating - * over the last two dimensions of the source tensor, creating the necessary - * tensors for the source, index, and output, and executing the embedding operation. + * This function applies the `IndexSelect` operation along a specific dimension + * of the source tensor (`src_buffer`) using the indices from the index tensor (`index`). + * It iterates over the last two dimensions of the source tensor, creates the corresponding + * CANN tensors for the source, index, and output slices, and executes the `IndexSelect` + * operation for each slice. * * @param ctx The context for CANN backend operations. - * @param src_buffer The source buffer holding the data for the source tensor. + * @param src_buffer The source buffer containing the 4D input tensor data. * @param src_ne The dimensions of the source tensor. * @param src_nb The strides (byte offsets) of the source tensor. - * @param index The index tensor used in the embedding operation. - * @param dst The destination tensor where the result will be stored. + * @param dst_buffer The destination buffer where the output tensor data will be written. + * @param dst_ne The dimensions of the destination tensor. + * @param dst_nb The strides (byte offsets) of the destination tensor. + * @param index The index tensor specifying the indices to select from the source tensor. + * @param type The data type of the source and destination tensors. */ -static void aclnn_embedding_4d(ggml_backend_cann_context& ctx, void* src_buffer, - int64_t* src_ne, size_t* src_nb, ggml_tensor* index, - ggml_tensor* dst) { +static void aclnn_index_select_4d(ggml_backend_cann_context& ctx, + void* src_buffer,int64_t* src_ne, size_t* src_nb, + void* dst_buffer, int64_t* dst_ne, size_t* dst_nb, + ggml_tensor* index, ggml_type type) { for (int64_t i = 0; i < src_ne[3]; i++) { for (int64_t j = 0; j < src_ne[2]; j++) { // src - int64_t acl_src_ne[2] = {src_ne[0], src_ne[1]}; - size_t acl_src_nb[2] = {src_nb[0], src_nb[1]}; aclTensor* acl_src_tensor = ggml_cann_create_tensor( (char*)src_buffer + i * src_nb[3] + j * src_nb[2], - ggml_cann_type_mapping(dst->type), ggml_element_size(dst), - acl_src_ne, acl_src_nb, 2); + ggml_cann_type_mapping(type), ggml_type_size(type), + src_ne, src_nb, 2); // index - int64_t acl_index_ne[1] = {index->ne[0]}; - size_t acl_index_nb[1] = {index->nb[0]}; aclTensor* acl_index = ggml_cann_create_tensor( - (char*)index->data + i * index->nb[2] + j * index->nb[1], + (char*)index->data + (i % index->ne[2]) * index->nb[2] + (j % index->ne[1]) * index->nb[1], ggml_cann_type_mapping(index->type), ggml_element_size(index), - acl_index_ne, acl_index_nb, 1); + index->ne, index->nb, 1); // out - int64_t acl_out_ne[2] = {dst->ne[0], dst->ne[1]}; - size_t acl_out_nb[2] = {dst->nb[0], dst->nb[1]}; aclTensor* acl_out = ggml_cann_create_tensor( - (char*)dst->data + i * dst->nb[3] + j * dst->nb[2], - ggml_cann_type_mapping(dst->type), ggml_element_size(dst), - acl_out_ne, acl_out_nb, 2); - GGML_CANN_CALL_ACLNN_OP(ctx, Embedding, acl_src_tensor, acl_index, acl_out); + (char*)dst_buffer + i * dst_nb[3] + j * dst_nb[2], + ggml_cann_type_mapping(type), ggml_type_size(type), + dst_ne, dst_nb, 2); + GGML_CANN_CALL_ACLNN_OP(ctx, IndexSelect, acl_src_tensor, 0, acl_index, acl_out); + ggml_cann_release_resources(ctx, acl_src_tensor, acl_index, acl_out); + } + } +} + +/** + * @brief Performs inplace index copy operation on a 4D tensor using the CANN backend. + * + * This function applies the `IndexCopy` operation along a specific dimension of the + * destination tensor (`dst_buffer`) by copying elements from the source tensor (`src_buffer`) + * to positions specified by the index tensor (`index`). + * It iterates over the last two dimensions of the tensors, creates the corresponding + * CANN tensors for source, index, and destination slices, and performs the index copy + * operation for each slice. + * + * @param ctx The context for CANN backend operations. + * @param src_buffer The source buffer containing the 4D input tensor data to be copied. + * @param src_ne The dimensions of the source tensor. + * @param src_nb The strides (byte offsets) of the source tensor. + * @param dst_buffer The destination buffer where values will be copied to. + * @param dst_ne The dimensions of the destination tensor. + * @param dst_nb The strides (byte offsets) of the destination tensor. + * @param index The index tensor specifying target positions in the destination tensor. + * @param type The data type of the source and destination tensors. + */ +static void aclnn_index_copy_4d(ggml_backend_cann_context& ctx, + void* src_buffer,int64_t* src_ne, size_t* src_nb, + void* dst_buffer, int64_t* dst_ne, size_t* dst_nb, + ggml_tensor* index, ggml_type type) { + for (int64_t i = 0; i < src_ne[3]; i++) { + for (int64_t j = 0; j < src_ne[2]; j++) { + // src + aclTensor* acl_src_tensor = ggml_cann_create_tensor( + (char*)src_buffer + i * src_nb[3] + j * src_nb[2], + ggml_cann_type_mapping(type), ggml_type_size(type), + src_ne, src_nb, 2); + + // index + aclTensor* acl_index = ggml_cann_create_tensor( + (char*)index->data + (i % index->ne[2]) * index->nb[2] + (j % index->ne[1]) * index->nb[1], + ggml_cann_type_mapping(index->type), ggml_element_size(index), + index->ne, index->nb, 1); + + // out + aclTensor* acl_out = ggml_cann_create_tensor( + (char*)dst_buffer + i * dst_nb[3] + j * dst_nb[2], + ggml_cann_type_mapping(type), ggml_type_size(type), + dst_ne, dst_nb, 2); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceIndexCopy, acl_out, 0, acl_index, acl_src_tensor); ggml_cann_release_resources(ctx, acl_src_tensor, acl_index, acl_out); } } @@ -1633,8 +1663,9 @@ void ggml_cann_get_rows(ggml_backend_cann_context& ctx, ggml_tensor* dst) { switch (src0->type) { case GGML_TYPE_F32: { - aclnn_embedding_4d(ctx, src0->data, src0->ne, src0->nb, src1, - dst); + aclnn_index_select_4d(ctx, src0->data, src0->ne, src0->nb, + dst->data, dst->ne, dst->nb, + src1, dst->type); break; } case GGML_TYPE_F16: { @@ -1651,8 +1682,9 @@ void ggml_cann_get_rows(ggml_backend_cann_context& ctx, ggml_tensor* dst) { src_trans_buffer, ACL_FLOAT, ggml_type_size(dst->type), src0->ne, src_trans_nb, GGML_MAX_DIMS); aclnn_cast(ctx, acl_src0, src_trans_tensor, ggml_cann_type_mapping(dst->type)); - aclnn_embedding_4d(ctx, src_trans_buffer, src0->ne, - src_trans_nb, src1, dst); + aclnn_index_select_4d(ctx, src_trans_buffer, src0->ne, src_trans_nb, + dst->data, dst->ne, dst->nb, + src1, dst->type); ggml_cann_release_resources(ctx, acl_src0, src_trans_tensor); break; } @@ -1712,8 +1744,10 @@ void ggml_cann_get_rows(ggml_backend_cann_context& ctx, ggml_tensor* dst) { dequant_nb[i] = dequant_nb[i - 1] * src0->ne[i - 1]; } - aclnn_embedding_4d(ctx, dequant_buffer_allocator.get(), - dequant_ne, dequant_nb, src1, dst); + aclnn_index_select_4d(ctx, dequant_buffer_allocator.get(), + dequant_ne, dequant_nb, + dst->data, dst->ne, dst->nb, + src1, dst->type); ggml_cann_release_resources(ctx, dequant_tensor); break; @@ -1724,6 +1758,43 @@ void ggml_cann_get_rows(ggml_backend_cann_context& ctx, ggml_tensor* dst) { } } +void ggml_cann_set_rows(ggml_backend_cann_context& ctx, ggml_tensor* dst) { + ggml_tensor* src0 = dst->src[0]; // src + ggml_tensor* src1 = dst->src[1]; // index + + switch (dst->type) { + case GGML_TYPE_F32: { + aclnn_index_copy_4d(ctx, src0->data, src0->ne, src0->nb, + dst->data, dst->ne, dst->nb, + src1, dst->type); + break; + } + case GGML_TYPE_F16: { + aclTensor* acl_src0 = ggml_cann_create_tensor(src0); + ggml_cann_pool_alloc src_buffer_allocator( + ctx.pool(), ggml_nelements(src0) * sizeof(uint16_t)); + void* src_trans_buffer = src_buffer_allocator.get(); + size_t src_trans_nb[GGML_MAX_DIMS]; + src_trans_nb[0] = sizeof(uint16_t); + for (int i = 1; i < GGML_MAX_DIMS; i++) { + src_trans_nb[i] = src_trans_nb[i - 1] * src0->ne[i - 1]; + } + aclTensor* src_trans_tensor = ggml_cann_create_tensor( + src_trans_buffer, ACL_FLOAT16, ggml_type_size(dst->type), + src0->ne, src_trans_nb, GGML_MAX_DIMS); + aclnn_cast(ctx, acl_src0, src_trans_tensor, ggml_cann_type_mapping(dst->type)); + aclnn_index_copy_4d(ctx, src_trans_buffer, src0->ne, src_trans_nb, + dst->data, dst->ne, dst->nb, + src1, dst->type); + ggml_cann_release_resources(ctx, acl_src0, src_trans_tensor); + break; + } + default: + GGML_ABORT("Unsupported tensor type for GGML_OP_SET_ROWS"); + break; + } +} + /** * @brief Repeats elements of a tensor along a specified dimension. * @@ -1785,8 +1856,25 @@ static void ggml_cann_mat_mul_fp(ggml_backend_cann_context& ctx, size_t transpose_nb[] = {bcast_weight_nb[1], bcast_weight_nb[0], bcast_weight_nb[2], bcast_weight_nb[3], bcast_weight_nb[4], bcast_weight_nb[5]}; - aclTensor* acl_weight_tensor = - ggml_cann_create_tensor(weight, transpose_ne, transpose_nb, n_dims); + aclTensor* acl_weight_tensor; + + // Only check env once. + static bool weight_to_nz = parse_bool(get_env("GGML_CANN_WEIGHT_NZ").value_or("")); + if (weight_to_nz && is_matmul_weight(weight)) { + int64_t acl_stride[2] = {1, transpose_ne[1]}; + + // Reverse ne. + std::reverse(transpose_ne, transpose_ne + n_dims); + + std::vector storageDims = {transpose_ne[0], transpose_ne[1]}; + + acl_weight_tensor = aclCreateTensor( + transpose_ne, n_dims, ggml_cann_type_mapping(weight->type), acl_stride, + 0, ACL_FORMAT_FRACTAL_NZ, storageDims.data(), 2, weight->data); + } else { + acl_weight_tensor = + ggml_cann_create_tensor(weight, transpose_ne, transpose_nb, n_dims, ACL_FORMAT_ND); + } aclTensor* acl_dst = ggml_cann_create_tensor(dst, bcast_dst_ne, bcast_dst_nb, n_dims); @@ -3065,104 +3153,24 @@ void ggml_cann_flash_attn_ext(ggml_backend_cann_context& ctx, ggml_tensor* dst){ // Compute the slope if needed. Derived from ggml_cann_softmax(). if(maxBias != 0.0f){ // alibi - const int64_t ne2_ne3 = src0->ne[2] * src0->ne[3]; - const int64_t n_head = src0->ne[2]; - const int n_heads_log2_floor = 1u << (uint32_t)floor(log2(n_head)); - float m0 = powf(2.0f, -(maxBias) / n_heads_log2_floor); - float m1 = powf(2.0f, -(maxBias / 2.0f) / n_heads_log2_floor); - // init arange - ggml_cann_pool_alloc arange_allocator(ctx.pool(), - ne2_ne3 * faElemSize); - void* tmp_arange_buffer = arange_allocator.get(); + const int64_t n_heads = src0->ne[2]; + ggml_cann_pool_alloc slope_allocator(ctx.pool(), n_heads * sizeof(float)); + void* slope_buffer = slope_allocator.get(); + aclnn_get_slope(ctx, n_heads, slope_buffer, maxBias); - // arange1: [1, ..., n_heads_log2_floor+1) - float start = 1; - float stop = n_heads_log2_floor + 1; - float step = 1; - int64_t n_elements_arange = n_heads_log2_floor; - - int64_t tmp_arange1_ne[] = {n_heads_log2_floor}; - size_t tmp_arange1_nb[] = {faElemSize}; - aclTensor* tmp_arange1_tensor = ggml_cann_create_tensor( - tmp_arange_buffer, faDataType, faElemSize, - tmp_arange1_ne, tmp_arange1_nb, - GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - - aclnn_arange(ctx, tmp_arange1_tensor, start, stop, step, n_elements_arange); - - aclTensor* tmp_arange2_tensor = nullptr; - if (n_heads_log2_floor < ne2_ne3) { - // arange2: [1, ..., 2 * (k - n_heads_log2_floor) + 1) - start = 1; - stop = 2 * (ne2_ne3 - n_heads_log2_floor) + 1; - step = 2; - n_elements_arange = ne2_ne3 - n_heads_log2_floor; - int64_t tmp_arange2_ne[] = {ne2_ne3 - n_heads_log2_floor}; - size_t tmp_arange2_nb[] = {faElemSize}; - - aclTensor* tmp_arange2_tensor = ggml_cann_create_tensor( - (char*)tmp_arange_buffer + - n_heads_log2_floor * faElemSize, - faDataType, faElemSize, - tmp_arange2_ne, tmp_arange2_nb, GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - aclnn_arange(ctx, tmp_arange2_tensor, start, stop, step, - n_elements_arange); + int64_t slope_ne[] = {1, 1, n_heads, 1}; + size_t slope_nb[GGML_MAX_DIMS]; + slope_nb[0] = sizeof(float); + for(int i = 1;ine[2], src0->ne[3]}; - size_t tmp_mk_nb[GGML_MAX_DIMS]; - tmp_mk_nb[0] = faElemSize; - for (int i = 1; i < GGML_MAX_DIMS; i++) { - tmp_mk_nb[i] = tmp_mk_nb[i - 1] * tmp_mk_ne[i - 1]; - } - aclTensor* tmp_mk_tensor = ggml_cann_create_tensor( - tmp_mk_base_buffer, faDataType, faElemSize, - tmp_mk_ne, tmp_mk_nb, GGML_MAX_DIMS, - ACL_FORMAT_ND); - GGML_CANN_CALL_ACLNN_OP(ctx, InplaceMul, bcast_pse_tensor, tmp_mk_tensor); - - ggml_cann_release_resources(ctx, tmp_arange1_tensor, tmp_arange2_tensor, - tmp_mk_base1_tensor, tmp_mk_base2_tensor, tmp_mk_base_tensor, - tmp_arange_tensor, tmp_mk_tensor); + ggml_cann_release_resources(ctx, slope_tensor); } } diff --git a/ggml/src/ggml-cann/aclnn_ops.h b/ggml/src/ggml-cann/aclnn_ops.h index 80ce80baea..5c510cc993 100755 --- a/ggml/src/ggml-cann/aclnn_ops.h +++ b/ggml/src/ggml-cann/aclnn_ops.h @@ -23,6 +23,7 @@ #ifndef CANN_ACLNN_OPS #define CANN_ACLNN_OPS +#include #include #include #include @@ -423,15 +424,25 @@ void ggml_cann_softmax(ggml_backend_cann_context& ctx, ggml_tensor* dst); * * @details This function retrieves rows from a source tensor src0 according to * the indices provided in another tensor src1 and stores the result in - * a destination tensor (\p dst). It supports different data types - * including F32, F16, Q4_0, and Q8_0. + * a destination tensor (\p dst). * * @param ctx The backend CANN context for executing operations. * @param dst The destination tensor where the extracted rows will be stored. - * dst->op is `GGML_OP_GET_ROWS`. */ void ggml_cann_get_rows(ggml_backend_cann_context& ctx, ggml_tensor* dst); +/** + * @brief Writes specific rows into a tensor at positions specified by indices. + * + * @details This function copies rows from a source tensor into a destination + * tensor (\p dst) at the positions indicated by the indices in another + * tensor. + * + * @param ctx The backend CANN context for executing operations. + * @param dst The destination tensor where the specified rows will be updated. + */ +void ggml_cann_set_rows(ggml_backend_cann_context& ctx, ggml_tensor* dst); + /** * @brief Executes matrix multiplication for the given tensor. * @@ -1020,6 +1031,37 @@ inline void ggml_cann_async_memset(ggml_backend_cann_context & ctx, void * buffe */ void ggml_cann_mul_mat_id(ggml_backend_cann_context& ctx, ggml_tensor* dst); +/** + * @brief Check whether a tensor is a weight tensor for matrix multiplication. + * + * @details Checks whether the given tensor serves as weight parameters in matrix multiplication operations, + * typically within neural network layers. The function maintains a static set of canonical weight + * naming suffixes from Transformer-based architectures. Uses substring matching to identify weight + * tensors even with hierarchical naming patterns. + * + * @param tensor Pointer to the target ggml_tensor object (const-qualified). + */ +static bool is_matmul_weight(const ggml_tensor* tensor) { + std::string name = ggml_get_name(tensor); + static const std::unordered_set weight_suffixes{ + "output.weight", + "attn_q.weight", + "attn_k.weight", + "attn_v.weight", + "attn_output.weight", + "ffn_gate.weight", + "ffn_up.weight", + "ffn_down.weight" + }; + + for (const auto& suffix : weight_suffixes) { + if (name.find(suffix) != std::string::npos) { + return true; + } + } + return false; +} + /** * @brief Applies a element-wise operation to two input tensors using the CANN * backend. @@ -1066,7 +1108,7 @@ void ggml_cann_binary_op(ggml_backend_cann_context& ctx, ggml_tensor* dst) { * @param dst The destination tensor. Its src[0] is treated as the input tensor. */ template - void ggml_cann_unary_op(ggml_backend_cann_context& ctx, ggml_tensor* dst) { + void ggml_cann_op_unary(ggml_backend_cann_context& ctx, ggml_tensor* dst) { ggml_tensor* src = dst->src[0]; aclTensor* acl_src = ggml_cann_create_tensor(src); @@ -1077,49 +1119,125 @@ template } /** - * @brief Applies a unary operation to a ggml tensor using the CANN backend. + * @brief Applies a unary operation to a ggml tensor using the CANN backend. * - * @details This function performs a unary operation on the input tensor using - * a user-provided lambda or callable object `unary_op`, which accepts the CANN - * context and two ACL tensors (source and destination). Internally, this function - * creates ACL representations of the ggml tensors and invokes the unary operation. - * The result is stored in the destination tensor `dst`. This utility abstracts the - * common boilerplate of tensor conversion and cleanup when implementing unary ops. + * @details This function applies a unary operation to the input tensor using + * a user-provided lambda or callable `unary_op`. The lambda receives the + * CANN backend context and two ACL tensors: the source and the destination. * - * @param unary_op A callable that performs the unary operation using CANN APIs. - * @param ctx The CANN context used for operations. - * @param dst The destination tensor where the result will be stored. - * The source tensor is retrieved from `dst->src[0]`. + * Internally, this function handles the conversion from GGML tensors to ACL tensors, + * calls the provided unary op, and manages resource cleanup. The input is assumed + * to be `dst->src[0]`, and the result is written to `dst`. + * + * This utility simplifies writing unary op wrappers by abstracting tensor preparation. + * + * @param unary_op A callable that performs the unary operation using CANN ACL APIs. + * @param ctx The CANN context for operation execution. + * @param dst The destination ggml_tensor where the result will be stored. + * The input tensor is assumed to be `dst->src[0]`. + * + * @see GGML_CANN_CALL_OP_UNARY */ -void ggml_cann_unary_op( +void ggml_cann_op_unary( std::function unary_op, ggml_backend_cann_context& ctx, ggml_tensor* dst); /** - * @brief Helper macro to invoke a unary ACL operation using ggml_cann_unary_op. + * @brief Applies a gated (GLU-style) unary operation using the CANN backend. * - * This macro defines an inline lambda wrapping a specific ACL operation name, - * and passes it to the templated ggml_cann_unary_op function. It simplifies - * calling unary ops by hiding the lambda boilerplate. + * @details This function performs a gated activation such as GEGLU or ReGLU. + * It supports two input modes: + * + * 1. **Dual input mode**: `dst->src[0]` and `dst->src[1]` are both valid tensors. + * These are used directly as the value and gate tensors. + * + * 2. **Packed input mode**: Only `dst->src[0]` is valid, and it is assumed to + * contain a concatenation of value and gate along the first dimension. This tensor + * will be split into two equal halves to form the value and gate inputs. + * + * The function applies a user-provided unary operation (e.g., GELU) to the value tensor, + * then multiplies the result in-place with the gate tensor: * - * Internally, the lambda will call: * @code - * GGML_CANN_CALL_ACLNN_OP(ctx, OP_NAME, acl_src, acl_dst); + * dst = unary_op(value) * gate; * @endcode * + * The `swapped` parameter (from `dst->op_params[1]`) allows flipping the + * order of value/gate in the packed input case. + * + * @param unary_op A callable that performs the unary operation using CANN ACL APIs. + * It receives (ctx, acl_value_tensor, acl_output_tensor). + * @param ctx The CANN context used for execution. + * @param dst The destination ggml_tensor. Source tensors are in `dst->src[0]` and optionally `src[1]`. + * + * @see GGML_CANN_CALL_OP_UNARY_GATED + */ +void ggml_cann_op_unary_gated( + std::function unary_op, + ggml_backend_cann_context& ctx, ggml_tensor* dst); + +/** + * @brief Helper macro to call a unary ACL operator via ggml_cann_op_unary. + * + * This macro wraps the specified ACLNN unary operator name into a lambda expression, + * and passes it to `ggml_cann_op_unary`, which handles the common logic for executing + * unary ops in the CANN backend. + * + * Internally, this macro expands to a lambda like: + * @code + * [](ggml_backend_cann_context& ctx, aclTensor* acl_src, aclTensor* acl_dst) { + * GGML_CANN_CALL_ACLNN_OP(ctx, OP_NAME, acl_src, acl_dst); + * }; + * @endcode + * + * This lambda is then passed to `ggml_cann_op_unary`, which applies the operation. + * * @param OP_NAME The name of the ACL unary operator to invoke via GGML_CANN_CALL_ACLNN_OP. * - * @see ggml_cann_unary_op + * @see ggml_cann_op_unary * @see GGML_CANN_CALL_ACLNN_OP */ -#define GGML_CANN_CALL_UNARY_OP(OP_NAME) \ +#define GGML_CANN_CALL_OP_UNARY(OP_NAME) \ do { \ auto lambda = [](ggml_backend_cann_context& ctx, \ aclTensor* acl_src, \ aclTensor* acl_dst) { \ GGML_CANN_CALL_ACLNN_OP(ctx, OP_NAME, acl_src, acl_dst); \ }; \ - ggml_cann_unary_op(lambda, ctx, dst); \ + ggml_cann_op_unary(lambda, ctx, dst); \ } \ while (0) + +/** + * @brief Helper macro to call a gated unary ACL operator via ggml_cann_op_unary_gated. + * + * This macro wraps the specified ACLNN unary operator name into a lambda expression, + * and passes it to `ggml_cann_op_unary_gated`, which handles the common logic for + * executing gated unary ops in the CANN backend. + * + * Internally, this macro expands to a lambda like: + * @code + * [](ggml_backend_cann_context& ctx, aclTensor* acl_src, aclTensor* acl_dst) { + * GGML_CANN_CALL_ACLNN_OP(ctx, OP_NAME, acl_src, acl_dst); + * }; + * @endcode + * + * This lambda is then passed to `ggml_cann_op_unary_gated`, which applies the operation. + * + * @param OP_NAME The name of the ACL unary operator to invoke via GGML_CANN_CALL_ACLNN_OP. + * + * @see ggml_cann_op_unary_gated + * @see GGML_CANN_CALL_ACLNN_OP + */ +#define GGML_CANN_CALL_OP_UNARY_GATED(OP_NAME) \ + do { \ + auto lambda = [](ggml_backend_cann_context& ctx, \ + aclTensor* acl_src, \ + aclTensor* acl_dst) { \ + GGML_CANN_CALL_ACLNN_OP(ctx, OP_NAME, acl_src, acl_dst); \ + }; \ + ggml_cann_op_unary_gated(lambda, ctx, dst); \ + } \ + while (0) + #endif // CANN_ACLNN_OPS diff --git a/ggml/src/ggml-cann/common.h b/ggml/src/ggml-cann/common.h index 8dfe3b061c..9d294f72b6 100755 --- a/ggml/src/ggml-cann/common.h +++ b/ggml/src/ggml-cann/common.h @@ -337,6 +337,29 @@ private: int32_t device_; }; +#ifdef USE_ACL_GRAPH +struct ggml_graph_node_properties { + void * node_address; + ggml_op node_op; + int64_t ne[GGML_MAX_DIMS]; + size_t nb[GGML_MAX_DIMS]; + void * src_address[GGML_MAX_SRC]; + int32_t op_params[GGML_MAX_OP_PARAMS / sizeof(int32_t)]; +}; + +struct ggml_cann_graph { + ~ggml_cann_graph() { + if (graph != nullptr) { + aclmdlRIDestroy(graph); + } + } + + aclmdlRI graph = nullptr; + + std::vector ggml_graph_properties; +}; +#endif // USE_ACL_GRAPH + /** * @brief Context for managing CANN backend operations. */ @@ -345,8 +368,13 @@ struct ggml_backend_cann_context { std::string name; /**< Name of the device. */ std::string description; /**< Description of the device. */ aclrtEvent copy_event = nullptr; /**< Event for managing copy operations. */ +#ifdef USE_ACL_GRAPH + /// Cached CANN ACL graph used for executing the current ggml computation graph. + std::unique_ptr cann_graph; +#endif cann_task_queue task_queue; bool async_mode; + bool support_set_rows; aclrtStream streams[GGML_CANN_MAX_STREAMS] = {nullptr}; /**< Array of streams for the device. */ @@ -362,6 +390,14 @@ struct ggml_backend_cann_context { async_mode = parse_bool(get_env("GGML_CANN_ASYNC_MODE").value_or("")); GGML_LOG_INFO("%s: device %d async operator submission is %s\n", __func__, device, async_mode ? "ON" : "OFF"); + + support_set_rows = parse_bool(get_env("LLAMA_SET_ROWS").value_or("")); + GGML_LOG_INFO("%s: LLAMA_SET_ROWS is %s\n", __func__, support_set_rows ? "ON" : "OFF"); + + if (!support_set_rows) { + GGML_LOG_INFO("%s: CANN Graph currently only supports execution when LLAMA_SET_ROWS is ON. " + "Falling back to eager mode.\n", __func__); + } } /** diff --git a/ggml/src/ggml-cann/ggml-cann.cpp b/ggml/src/ggml-cann/ggml-cann.cpp index e5e11d4cdc..cb8af42ebf 100755 --- a/ggml/src/ggml-cann/ggml-cann.cpp +++ b/ggml/src/ggml-cann/ggml-cann.cpp @@ -24,6 +24,7 @@ #include #include +#include #include #include @@ -1115,6 +1116,61 @@ static enum ggml_status ggml_backend_cann_buffer_init_tensor( return GGML_STATUS_SUCCESS; } +// ND to NZ Workspace Cache Management. Thread-safety: Not guaranteed +namespace { + void* g_nz_workspace = nullptr; + size_t g_nz_workspace_allocated = 0; + + void release_nz_workspace() { + if (g_nz_workspace) { + aclrtFree(g_nz_workspace); + g_nz_workspace = nullptr; + g_nz_workspace_allocated = 0; + } + } + + void relloc_nz_workspace(size_t new_size) { + if (new_size > g_nz_workspace_allocated) { + if (g_nz_workspace) { + aclrtFree(g_nz_workspace); + g_nz_workspace = nullptr; + } + ACL_CHECK(aclrtMalloc(&g_nz_workspace, new_size, ACL_MEM_MALLOC_HUGE_FIRST)); + g_nz_workspace_allocated = new_size; + } + } +} + +/** + * @brief Convert tensor weights to NZ format using Ascend CANN API. + * + * This function creates a transposed tensor descriptor and performs the + * TransMatmulWeight operation. Converting tensor formats can significantly + * improve performance on certain hardware. + * + * @param tensor Pointer to the input ggml_tensor containing the weights. + * @param data Pointer to the raw data buffer for the tensor weights. + * @param offset Byte offset within the tensor data buffer where weights start. + * + * @note The workspace buffer used in this function is managed globally and reused + * across calls. This reduces overhead from repeated memory allocation and deallocation. + */ +static void weight_format_to_nz(ggml_tensor *tensor, const void *data, size_t offset) { + aclTensor* weightTransposed = ggml_cann_create_tensor(tensor, tensor->ne, + tensor->nb, 2, ACL_FORMAT_ND, offset); + uint64_t workspaceSize = 0; + aclOpExecutor *executor; + + // TransMatmulWeight + ACL_CHECK(aclnnTransMatmulWeightGetWorkspaceSize(weightTransposed, + &workspaceSize, &executor)); + // Avoid frequent malloc/free of the workspace. + relloc_nz_workspace(workspaceSize); + + ACL_CHECK(aclnnTransMatmulWeight(g_nz_workspace, workspaceSize, executor, nullptr)); + ACL_CHECK(aclDestroyTensor(weightTransposed)); +} + // TODO: need handle tensor which has paddings. /** * @brief Set tensor data in a CANN buffer. @@ -1139,9 +1195,16 @@ static void ggml_backend_cann_buffer_set_tensor( // For acl, synchronous functions use this default stream. // Why aclrtSynchronizeDevice? + // Only check env once. + static bool weight_to_nz = parse_bool(get_env("GGML_CANN_WEIGHT_NZ").value_or("")); if (!need_transform(tensor->type)) { ACL_CHECK(aclrtMemcpy((char *)tensor->data + offset, size, data, size, ACL_MEMCPY_HOST_TO_DEVICE)); + if (weight_to_nz && is_matmul_weight((const ggml_tensor*)tensor)) { + GGML_ASSERT(tensor->ne[2] == 1); + GGML_ASSERT(tensor->ne[3] == 1); + weight_format_to_nz(tensor, data, offset); + } } else { void *transform_buffer = malloc(size); ggml_backend_cann_transform(tensor, data, transform_buffer); @@ -1375,20 +1438,32 @@ static size_t ggml_backend_cann_buffer_type_get_alloc_size( size_t size = ggml_nbytes(tensor); int64_t ne0 = tensor->ne[0]; + // Only check env once. + static bool weight_to_nz = parse_bool(get_env("GGML_CANN_WEIGHT_NZ").value_or("")); + // last line must bigger than 32, because every single op deal at // least 32 bytes. // TODO: quantized type? // int64_t line_size = ne0 * ggml_element_size(tensor); // int64_t line_size_align_32 = (line_size + 31) & ~31; // size += (line_size_align_32 - line_size); - - // TODO: not support quantized yet. - // TODO: consider un-continue tensor. if (ggml_is_quantized(tensor->type)) { if (ne0 % MATRIX_ROW_PADDING != 0) { size += ggml_row_size( tensor->type, MATRIX_ROW_PADDING - ne0 % MATRIX_ROW_PADDING); } + } else if (weight_to_nz && is_matmul_weight((const ggml_tensor*)tensor)) { + // NZ format weight are not support quantized yet. + // If ND tensor transform to NZ, size may changed. + int64_t shape[] = {tensor->ne[1], tensor->ne[0]}; + GGML_ASSERT(tensor->ne[2] == 1); + GGML_ASSERT(tensor->ne[3] == 1); + const aclIntArray *acl_shape = aclCreateIntArray(shape, 2); + size_t new_size; + ACL_CHECK(aclnnCalculateMatmulWeightSizeV2(acl_shape, + ggml_cann_type_mapping(tensor->type), &new_size)); + ACL_CHECK(aclDestroyIntArray(acl_shape)); + size = std::max(size, new_size); } return size; @@ -1594,6 +1669,9 @@ static bool ggml_cann_compute_forward(ggml_backend_cann_context& ctx, case GGML_OP_GET_ROWS: ggml_cann_get_rows(ctx, dst); break; + case GGML_OP_SET_ROWS: + ggml_cann_set_rows(ctx, dst); + break; case GGML_OP_DUP: ggml_cann_dup(ctx, dst); break; @@ -1616,16 +1694,18 @@ static bool ggml_cann_compute_forward(ggml_backend_cann_context& ctx, case GGML_OP_UNARY: switch (ggml_get_unary_op(dst)) { case GGML_UNARY_OP_ABS: - GGML_CANN_CALL_UNARY_OP(Abs); + GGML_CANN_CALL_OP_UNARY(Abs); break; case GGML_UNARY_OP_NEG: - GGML_CANN_CALL_UNARY_OP(Neg); + GGML_CANN_CALL_OP_UNARY(Neg); break; case GGML_UNARY_OP_GELU: - GGML_CANN_CALL_UNARY_OP(Gelu); + case GGML_UNARY_OP_GELU_ERF: + // aclnnGelu internally uses the erf-based approximation. + GGML_CANN_CALL_OP_UNARY(Gelu); break; case GGML_UNARY_OP_SILU: - GGML_CANN_CALL_UNARY_OP(Silu); + GGML_CANN_CALL_OP_UNARY(Silu); break; case GGML_UNARY_OP_GELU_QUICK: { auto lambda = [](ggml_backend_cann_context& ctx, @@ -1633,31 +1713,31 @@ static bool ggml_cann_compute_forward(ggml_backend_cann_context& ctx, aclTensor* acl_dst) { GGML_CANN_CALL_ACLNN_OP(ctx, GeluV2, acl_src, 0, acl_dst); }; - ggml_cann_unary_op(lambda, ctx, dst); + ggml_cann_op_unary(lambda, ctx, dst); } break; case GGML_UNARY_OP_TANH: - GGML_CANN_CALL_UNARY_OP(Tanh); + GGML_CANN_CALL_OP_UNARY(Tanh); break; case GGML_UNARY_OP_RELU: - GGML_CANN_CALL_UNARY_OP(Relu); + GGML_CANN_CALL_OP_UNARY(Relu); break; case GGML_UNARY_OP_SIGMOID: - GGML_CANN_CALL_UNARY_OP(Sigmoid); + GGML_CANN_CALL_OP_UNARY(Sigmoid); break; case GGML_UNARY_OP_HARDSIGMOID: - GGML_CANN_CALL_UNARY_OP(Hardsigmoid); + GGML_CANN_CALL_OP_UNARY(Hardsigmoid); break; case GGML_UNARY_OP_HARDSWISH: - GGML_CANN_CALL_UNARY_OP(Hardswish); + GGML_CANN_CALL_OP_UNARY(Hardswish); break; case GGML_UNARY_OP_EXP: - GGML_CANN_CALL_UNARY_OP(Exp); + GGML_CANN_CALL_OP_UNARY(Exp); break; case GGML_UNARY_OP_ELU: ggml_cann_elu(ctx, dst); break; case GGML_UNARY_OP_SGN: - GGML_CANN_CALL_UNARY_OP(Sign); + GGML_CANN_CALL_OP_UNARY(Sign); break; case GGML_UNARY_OP_STEP: ggml_cann_step(ctx, dst); @@ -1666,6 +1746,31 @@ static bool ggml_cann_compute_forward(ggml_backend_cann_context& ctx, return false; } break; + case GGML_OP_GLU: + switch (ggml_get_glu_op(dst)) { + case GGML_GLU_OP_REGLU: + GGML_CANN_CALL_OP_UNARY_GATED(Relu); + break; + case GGML_GLU_OP_GEGLU: + case GGML_GLU_OP_GEGLU_ERF: + // aclnnGelu internally uses the erf-based approximation. + GGML_CANN_CALL_OP_UNARY_GATED(Gelu); + break; + case GGML_GLU_OP_SWIGLU: + GGML_CANN_CALL_OP_UNARY_GATED(Silu); + break; + case GGML_GLU_OP_GEGLU_QUICK: { + auto lambda = [](ggml_backend_cann_context& ctx, + aclTensor* acl_src, + aclTensor* acl_dst) { + GGML_CANN_CALL_ACLNN_OP(ctx, GeluV2, acl_src, 0, acl_dst); + }; + ggml_cann_op_unary_gated(lambda, ctx, dst); + } break; + default: + return false; + } + break; case GGML_OP_NORM: ggml_cann_norm(ctx, dst); break; @@ -1708,7 +1813,7 @@ static bool ggml_cann_compute_forward(ggml_backend_cann_context& ctx, ggml_cann_binary_op(ctx, dst); break; case GGML_OP_SQRT: - GGML_CANN_CALL_UNARY_OP(Sqrt); + GGML_CANN_CALL_OP_UNARY(Sqrt); break; case GGML_OP_CLAMP: ggml_cann_clamp(ctx, dst); @@ -1753,16 +1858,16 @@ static bool ggml_cann_compute_forward(ggml_backend_cann_context& ctx, ggml_cann_argmax(ctx, dst); break; case GGML_OP_COS: - ggml_cann_unary_op(ctx, dst); + ggml_cann_op_unary(ctx, dst); break; case GGML_OP_SIN: - ggml_cann_unary_op(ctx, dst); + ggml_cann_op_unary(ctx, dst); break; case GGML_OP_CONV_TRANSPOSE_1D: ggml_cann_conv_transpose_1d(ctx, dst); break; case GGML_OP_LOG: - GGML_CANN_CALL_UNARY_OP(Log); + GGML_CANN_CALL_OP_UNARY(Log); break; case GGML_OP_MEAN: ggml_cann_mean(ctx, dst); @@ -1911,6 +2016,9 @@ static bool ggml_backend_cann_cpy_tensor_async( (ggml_backend_cann_context*)backend_dst->context; size_t copy_size = ggml_nbytes(dst); + if (copy_size == 0) { + return true; + } if (backend_src != backend_dst) { ggml_backend_cann_buffer_context* buf_ctx_src = (ggml_backend_cann_buffer_context*)buf_src->context; @@ -1967,6 +2075,160 @@ static void ggml_backend_cann_synchronize(ggml_backend_t backend) { ACL_CHECK(aclrtSynchronizeStream(cann_ctx->stream())); } +#ifdef USE_ACL_GRAPH +/** + * @brief Populate the internal CANN graph node properties from the ggml computation graph. + * + * This function copies all node attributes (operation type, dimensions, strides, input sources, + * and operation parameters) into the cached CANN graph structure for later reuse or comparison. + * + * @param cann_ctx The CANN backend context. + * @param cgraph The ggml computational graph. + */ +static void set_ggml_graph_node_properties(ggml_backend_cann_context * cann_ctx, ggml_cgraph * cgraph) { + for (int node_idx = 0; node_idx < cgraph->n_nodes; node_idx++) { + ggml_tensor * node = cgraph->nodes[node_idx]; + cann_ctx->cann_graph->ggml_graph_properties[node_idx].node_address = node->data; + cann_ctx->cann_graph->ggml_graph_properties[node_idx].node_op = node->op; + + for (int dim = 0; dim < GGML_MAX_DIMS; dim++) { + cann_ctx->cann_graph->ggml_graph_properties[node_idx].ne[dim] = node->ne[dim]; + cann_ctx->cann_graph->ggml_graph_properties[node_idx].nb[dim] = node->nb[dim]; + } + for (int src = 0; src < GGML_MAX_SRC; src++) { + cann_ctx->cann_graph->ggml_graph_properties[node_idx].src_address[src] = + node->src[src] ? node->src[src]->data : nullptr; + } + memcpy(cann_ctx->cann_graph->ggml_graph_properties[node_idx].op_params, node->op_params, GGML_MAX_OP_PARAMS); + } +} + +/** + * @brief Check if a ggml tensor node matches a previously captured CANN graph node. + * + * This function compares all relevant fields (address, op type, shape, source inputs, op params) + * to determine whether the current node matches a previously recorded version. + * + * @param node The current ggml tensor node. + * @param graph_node_properties The stored properties of a CANN graph node. + * @return true if all fields match (excluding GGML_OP_VIEW); false otherwise. + */ +static bool ggml_graph_node_has_matching_properties(ggml_tensor * node, ggml_graph_node_properties * graph_node_properties) { + if (node->data != graph_node_properties->node_address && + node->op != GGML_OP_VIEW) { + return false; + } + if (node->op != graph_node_properties->node_op) { + return false; + } + for (int i = 0; i < GGML_MAX_DIMS; i++) { + if (node->ne[i] != graph_node_properties->ne[i]) { + return false; + } + if (node->nb[i] != graph_node_properties->nb[i]) { + return false; + } + } + for (int i = 0; i < GGML_MAX_SRC; i++) { + if (node->src[i] && + node->src[i]->data != graph_node_properties->src_address[i] && + node->op != GGML_OP_VIEW + ) { + return false; + } + } + if (node->op == GGML_OP_SCALE && + memcmp(graph_node_properties->op_params, node->op_params, GGML_MAX_OP_PARAMS) != 0) { + return false; + } + return true; +} + +/** + * @brief Determine if the CANN graph needs to be rebuilt due to graph changes. + * + * This checks whether the number or properties of ggml graph nodes have changed + * compared to the last captured CANN graph. If so, the CANN graph must be re-captured. + * + * @param cann_ctx The CANN backend context. + * @param cgraph The current ggml computation graph. + * @return true if an update is required; false otherwise. + */ +static bool is_cann_graph_update_required(ggml_backend_cann_context * cann_ctx, ggml_cgraph * cgraph) { + // The number of nodes is different, so the graph needs to be reconstructed. + if (cann_ctx->cann_graph->ggml_graph_properties.size() != (size_t)cgraph->n_nodes) { + cann_ctx->cann_graph->ggml_graph_properties.resize(cgraph->n_nodes); + return true; + } + + // The number of nodes is the same; iterate over each node to check whether they match. + for (int i = 0; i < cgraph->n_nodes; i++) { + bool has_matching_properties = ggml_graph_node_has_matching_properties( + cgraph->nodes[i], &cann_ctx->cann_graph->ggml_graph_properties[i]); + if(!has_matching_properties) { + return true; + } + } + return false; +} +#endif // USE_ACL_GRAPH + +/** + * @brief Evaluate the computation graph and optionally capture or execute it using CANN graph API. + * + * If CANN graph execution is enabled and graph capture is required, this function begins + * graph capture, runs the graph, ends capture, and stores the captured graph. + * + * Otherwise, it falls back to op-by-op execution using the CANN compute kernel dispatcher. + * + * @param cann_ctx The CANN backend context. + * @param cgraph The ggml computation graph. + * @param use_cann_graph Whether to use CANN graph execution. + * @param cann_graph_update_required Whether graph capture is needed due to graph changes. + */ +static void evaluate_and_capture_cann_graph(ggml_backend_cann_context * cann_ctx, ggml_cgraph * cgraph, + bool & use_cann_graph, bool & cann_graph_update_required) { +#ifdef USE_ACL_GRAPH + if (use_cann_graph && cann_graph_update_required) { + if (cann_ctx->cann_graph->graph != nullptr) { + ACL_CHECK(aclmdlRIDestroy(cann_ctx->cann_graph->graph)); + cann_ctx->cann_graph->graph = nullptr; + } + ACL_CHECK(aclmdlRICaptureBegin(cann_ctx->stream(), ACL_MODEL_RI_CAPTURE_MODE_GLOBAL)); + } +#endif // USE_ACL_GRAPH + + // Only perform the graph execution if CANN graphs are not enabled, or we are capturing the graph. + // With the use of CANN graphs, the execution will be performed by the graph launch. + if (!use_cann_graph || cann_graph_update_required) { + for (int i = 0; i < cgraph->n_nodes; i++) { + ggml_tensor * node = cgraph->nodes[i]; + + if (ggml_is_empty(node) || node->op == GGML_OP_RESHAPE || node->op == GGML_OP_TRANSPOSE || node->op == GGML_OP_VIEW || node->op == GGML_OP_PERMUTE || node->op == GGML_OP_NONE) { + continue; + } + + bool ok = ggml_cann_compute_forward(*cann_ctx, node); + if (!ok) { + GGML_LOG_ERROR("%s: op not supported %s (%s)\n", __func__, node->name, ggml_op_name(node->op)); + } + GGML_ASSERT(ok); + } + } + +#ifdef USE_ACL_GRAPH + if (use_cann_graph && cann_graph_update_required) { // End CANN graph capture + ACL_CHECK(aclmdlRICaptureEnd(cann_ctx->stream(), &cann_ctx->cann_graph->graph)); + } + + if (use_cann_graph) { + // Execute graph + ACL_CHECK(aclmdlRIExecuteAsync(cann_ctx->cann_graph->graph, cann_ctx->stream())); + } +#endif // USE_ACL_GRAPH +} + + /** * @brief Computes a computational graph using a CANN backend. * @@ -1983,25 +2245,38 @@ static enum ggml_status ggml_backend_cann_graph_compute( ggml_backend_t backend, ggml_cgraph* cgraph) { ggml_backend_cann_context* cann_ctx = (ggml_backend_cann_context*)backend->context; - ggml_cann_set_device(cann_ctx->device); + release_nz_workspace(); +#ifdef USE_ACL_GRAPH + bool use_cann_graph = true; + bool cann_graph_update_required = false; - for (int i = 0; i < cgraph->n_nodes; i++) { - ggml_tensor* node = cgraph->nodes[i]; - - if (ggml_is_empty(node) || node->op == GGML_OP_NONE) { - continue; - } - - bool ok = ggml_cann_compute_forward(*cann_ctx, node); - - if (!ok) { - GGML_LOG_ERROR("%s: error: op not supported %s (%s)\n", __func__, - node->name, ggml_op_name(node->op)); - } - GGML_ASSERT(ok); + // check environment LLAMA_SET_ROWS + if (!cann_ctx->support_set_rows) { + use_cann_graph = false; } + if (use_cann_graph) { + if (cann_ctx->cann_graph == nullptr) { + cann_ctx->cann_graph.reset(new ggml_cann_graph()); + cann_graph_update_required = true; + } + + cann_graph_update_required = is_cann_graph_update_required(cann_ctx, cgraph); + set_ggml_graph_node_properties(cann_ctx, cgraph); + } +#else + bool use_cann_graph = false; + bool cann_graph_update_required = false; +#endif // USE_ACL_GRAPH + + evaluate_and_capture_cann_graph( + cann_ctx, + cgraph, + use_cann_graph, + cann_graph_update_required + ); + return GGML_STATUS_SUCCESS; } @@ -2036,10 +2311,23 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, case GGML_UNARY_OP_ELU: case GGML_UNARY_OP_SGN: case GGML_UNARY_OP_STEP: + case GGML_UNARY_OP_GELU_ERF: return true; default: return false; } + case GGML_OP_GLU: + switch (ggml_get_glu_op(op)) { + case GGML_GLU_OP_REGLU: + case GGML_GLU_OP_GEGLU: + case GGML_GLU_OP_SWIGLU: + case GGML_GLU_OP_GEGLU_ERF: + case GGML_GLU_OP_GEGLU_QUICK: + return true; + default: + return false; + } + break; case GGML_OP_MUL_MAT: { switch (op->src[0]->type) { case GGML_TYPE_F16: @@ -2086,13 +2374,15 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, return false; } } break; - case GGML_OP_SET_ROWS: - { - // TODO: add support - // ref: https://github.com/ggml-org/llama.cpp/pull/14274 -#pragma message("TODO: implement F32, F16, BF16, Q4_0, Q4_1, Q5_0, Q5_1, Q8_0, IQ4_NL support (https://github.com/ggml-org/llama.cpp/pull/14661)") - return false; - } break; + case GGML_OP_SET_ROWS: { + switch (op->type) { + case GGML_TYPE_F32: + case GGML_TYPE_F16: + return true; + default: + return false; + } + } break; case GGML_OP_CPY: { ggml_tensor *src = op->src[0]; if ((op->type != GGML_TYPE_F32 && op->type != GGML_TYPE_F16) || @@ -2101,12 +2391,6 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, // only support F32 and F16. return false; } - - if (!ggml_are_same_shape(op, src) && !ggml_is_contiguous(op)) { - // unsupport dst is not contiguous. - return false; - } - return true; } break; case GGML_OP_CONT: { @@ -2172,8 +2456,8 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, // value of paddingW should be at most half of kernelW return (p0 <= (k0 / 2)) && (p1 <= (k1 / 2)); } - case GGML_OP_SUM: case GGML_OP_DUP: + case GGML_OP_SUM: case GGML_OP_IM2COL: case GGML_OP_CONCAT: case GGML_OP_REPEAT: @@ -2215,9 +2499,11 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, memcpy(&bias, (float*)op->op_params + 1, sizeof(float)); return bias == 0.0f; // TODO: support bias != 0.0f case GGML_OP_SOFT_MAX: - // TODO: support broadcast - // ref: https://github.com/ggml-org/llama.cpp/pull/14435 - return !op->src[1] || (op->src[1]->ne[2] == 1 && op->src[1]->ne[3] == 1); + // TODO: support attention sinks [TAG_ATTN_SINKS] + if (op->src[2]) { + return false; + } + return true; case GGML_OP_FLASH_ATTN_EXT:{ // derived from [ggml-cuda.cu] if(op->src[1]->type != GGML_TYPE_F16 || op->src[2]->type != GGML_TYPE_F16){ @@ -2229,6 +2515,10 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, if(op->type != GGML_TYPE_F16 && op->type != GGML_TYPE_F32 && op->type != GGML_TYPE_BF16){ return false; } + // TODO: support attention sinks [TAG_ATTN_SINKS] + if (op->src[4]) { + return false; + } if (op->src[1]->ne[0] != op->src[2]->ne[0]) { // different head sizes of K and V are not supported yet return false; @@ -2240,11 +2530,6 @@ static bool ggml_backend_cann_supports_op(ggml_backend_dev_t dev, // DeepSeek MLA return false; } - // TODO: support broadcast - // ref: https://github.com/ggml-org/llama.cpp/pull/14435 - if (op->src[0]->ne[3] != 1) { - return false; - } float logitSoftcap = 0.0f; memcpy(&logitSoftcap, (float*)op->op_params + 2, sizeof(float)); if(logitSoftcap != 0.0f) { diff --git a/ggml/src/ggml-common.h b/ggml/src/ggml-common.h index fbb04426ab..93ab7ea446 100644 --- a/ggml/src/ggml-common.h +++ b/ggml/src/ggml-common.h @@ -99,6 +99,9 @@ typedef sycl::half2 ggml_half2; #define QI4_1 (QK4_1 / (4 * QR4_1)) #define QR4_1 2 +#define QI_MXFP4 (QK_MXFP4 / (4 * QR_MXFP4)) +#define QR_MXFP4 2 + #define QI5_0 (QK5_0 / (4 * QR5_0)) #define QR5_0 2 @@ -184,6 +187,13 @@ typedef struct { } block_q4_1; static_assert(sizeof(block_q4_1) == 2 * sizeof(ggml_half) + QK4_1 / 2, "wrong q4_1 block size/padding"); +#define QK_MXFP4 32 +typedef struct { + uint8_t e; // E8M0 + uint8_t qs[QK_MXFP4/2]; +} block_mxfp4; +static_assert(sizeof(block_mxfp4) == sizeof(uint8_t) + QK_MXFP4/2, "wrong mxfp4 block size/padding"); + #define QK5_0 32 typedef struct { ggml_half d; // delta @@ -1074,10 +1084,17 @@ GGML_TABLE_BEGIN(uint32_t, iq3s_grid, 512) 0x0f090307, 0x0f090501, 0x0f090b01, 0x0f0b0505, 0x0f0b0905, 0x0f0d0105, 0x0f0d0703, 0x0f0f0101, GGML_TABLE_END() +// TODO: fix name to kvalues_iq4_nl GGML_TABLE_BEGIN(int8_t, kvalues_iq4nl, 16) -127, -104, -83, -65, -49, -35, -22, -10, 1, 13, 25, 38, 53, 69, 89, 113, GGML_TABLE_END() +// e2m1 values (doubled) +// ref: https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf +GGML_TABLE_BEGIN(int8_t, kvalues_mxfp4, 16) + 0, 1, 2, 3, 4, 6, 8, 12, 0, -1, -2, -3, -4, -6, -8, -12, +GGML_TABLE_END() + #define NGRID_IQ1S 2048 #define IQ1S_DELTA 0.125f #define IQ1M_DELTA 0.125f diff --git a/ggml/src/ggml-cpu/CMakeLists.txt b/ggml/src/ggml-cpu/CMakeLists.txt index 66a5ad8d2e..f188d1638d 100644 --- a/ggml/src/ggml-cpu/CMakeLists.txt +++ b/ggml/src/ggml-cpu/CMakeLists.txt @@ -70,10 +70,12 @@ function(ggml_add_cpu_backend_variant_impl tag_name) if (GGML_OPENMP) find_package(OpenMP) if (OpenMP_FOUND) + set(GGML_OPENMP_ENABLED "ON" CACHE INTERNAL "") target_compile_definitions(${GGML_CPU_NAME} PRIVATE GGML_USE_OPENMP) target_link_libraries(${GGML_CPU_NAME} PRIVATE OpenMP::OpenMP_C OpenMP::OpenMP_CXX) else() + set(GGML_OPENMP_ENABLED "OFF" CACHE INTERNAL "") message(WARNING "OpenMP not found") endif() endif() @@ -456,6 +458,7 @@ function(ggml_add_cpu_backend_variant_impl tag_name) list(APPEND ARCH_FLAGS -march=z16) elseif (${S390X_M} MATCHES "9175|9176") # NOTE: Only available from GCC 15.1.0 onwards. Any z17 machine with compile issues must first verify their GCC version. + # binutils must also be updated to the latest for the -march=z17 flag to work. Otherwise, use -march=arch15. message(STATUS "z17 target") list(APPEND ARCH_FLAGS -march=z17) else() @@ -494,9 +497,9 @@ function(ggml_add_cpu_backend_variant_impl tag_name) # Fetch KleidiAI sources: include(FetchContent) - set(KLEIDIAI_COMMIT_TAG "v1.9.0") + set(KLEIDIAI_COMMIT_TAG "v1.11.0") set(KLEIDIAI_DOWNLOAD_URL "https://github.com/ARM-software/kleidiai/archive/refs/tags/${KLEIDIAI_COMMIT_TAG}.tar.gz") - set(KLEIDIAI_ARCHIVE_MD5 "2a8e1bb55d201557553545536489a017") + set(KLEIDIAI_ARCHIVE_MD5 "3fe9e5ab964c375c53839296eb71eaa2") if (POLICY CMP0135) cmake_policy(SET CMP0135 NEW) diff --git a/ggml/src/ggml-cpu/arch-fallback.h b/ggml/src/ggml-cpu/arch-fallback.h index 10e5342516..f476127995 100644 --- a/ggml/src/ggml-cpu/arch-fallback.h +++ b/ggml/src/ggml-cpu/arch-fallback.h @@ -13,6 +13,7 @@ #define ggml_vec_dot_q5_0_q8_0_generic ggml_vec_dot_q5_0_q8_0 #define ggml_vec_dot_q5_1_q8_1_generic ggml_vec_dot_q5_1_q8_1 #define ggml_vec_dot_q8_0_q8_0_generic ggml_vec_dot_q8_0_q8_0 +#define ggml_vec_dot_mxfp4_q8_0_generic ggml_vec_dot_mxfp4_q8_0 #define ggml_vec_dot_tq1_0_q8_K_generic ggml_vec_dot_tq1_0_q8_K #define ggml_vec_dot_tq2_0_q8_K_generic ggml_vec_dot_tq2_0_q8_K #define ggml_vec_dot_q2_K_q8_K_generic ggml_vec_dot_q2_K_q8_K @@ -37,17 +38,25 @@ #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_0_8x8_q8_0_generic ggml_gemv_q4_0_8x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_0_8x8_q8_0_generic ggml_gemm_q4_0_8x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #elif defined(__aarch64__) || defined(__arm__) || defined(_M_ARM) || defined(_M_ARM64) // repack.cpp #define ggml_quantize_mat_q8_K_4x8_generic ggml_quantize_mat_q8_K_4x8 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #elif defined(__x86_64__) || defined(__i386__) || defined(_M_IX86) || defined(_M_X64) // repack.cpp #define ggml_quantize_mat_q8_0_4x4_generic ggml_quantize_mat_q8_0_4x4 @@ -64,6 +73,7 @@ #define ggml_vec_dot_tq1_0_q8_K_generic ggml_vec_dot_tq1_0_q8_K #define ggml_vec_dot_tq2_0_q8_K_generic ggml_vec_dot_tq2_0_q8_K #define ggml_vec_dot_iq1_m_q8_K_generic ggml_vec_dot_iq1_m_q8_K +#define ggml_vec_dot_mxfp4_q8_0_generic ggml_vec_dot_mxfp4_q8_0 // repack.cpp #define ggml_quantize_mat_q8_0_4x4_generic ggml_quantize_mat_q8_0_4x4 #define ggml_quantize_mat_q8_0_4x8_generic ggml_quantize_mat_q8_0_4x8 @@ -72,18 +82,23 @@ #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_0_8x8_q8_0_generic ggml_gemv_q4_0_8x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_0_8x8_q8_0_generic ggml_gemm_q4_0_8x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #elif defined(__loongarch64) // quants.c #define quantize_row_q8_K_generic quantize_row_q8_K #define ggml_vec_dot_tq1_0_q8_K_generic ggml_vec_dot_tq1_0_q8_K #define ggml_vec_dot_tq2_0_q8_K_generic ggml_vec_dot_tq2_0_q8_K #define ggml_vec_dot_iq1_m_q8_K_generic ggml_vec_dot_iq1_m_q8_K +#define ggml_vec_dot_mxfp4_q8_0_generic ggml_vec_dot_mxfp4_q8_0 // repack.cpp #define ggml_quantize_mat_q8_0_4x4_generic ggml_quantize_mat_q8_0_4x4 #define ggml_quantize_mat_q8_0_4x8_generic ggml_quantize_mat_q8_0_4x8 @@ -92,12 +107,16 @@ #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_0_8x8_q8_0_generic ggml_gemv_q4_0_8x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_0_8x8_q8_0_generic ggml_gemm_q4_0_8x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #elif defined(__riscv) // quants.c #define quantize_row_q8_K_generic quantize_row_q8_K @@ -112,6 +131,7 @@ #define ggml_vec_dot_iq1_m_q8_K_generic ggml_vec_dot_iq1_m_q8_K #define ggml_vec_dot_iq4_nl_q8_0_generic ggml_vec_dot_iq4_nl_q8_0 #define ggml_vec_dot_iq4_xs_q8_K_generic ggml_vec_dot_iq4_xs_q8_K +#define ggml_vec_dot_mxfp4_q8_0_generic ggml_vec_dot_mxfp4_q8_0 // repack.cpp #define ggml_quantize_mat_q8_0_4x4_generic ggml_quantize_mat_q8_0_4x4 #define ggml_quantize_mat_q8_0_4x8_generic ggml_quantize_mat_q8_0_4x8 @@ -119,11 +139,15 @@ #define ggml_gemv_q4_0_4x4_q8_0_generic ggml_gemv_q4_0_4x4_q8_0 #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #elif defined(__s390x__) // quants.c #define quantize_row_q8_K_generic quantize_row_q8_K @@ -139,6 +163,7 @@ #define ggml_vec_dot_iq3_s_q8_K_generic ggml_vec_dot_iq3_s_q8_K #define ggml_vec_dot_iq1_s_q8_K_generic ggml_vec_dot_iq1_s_q8_K #define ggml_vec_dot_iq1_m_q8_K_generic ggml_vec_dot_iq1_m_q8_K +#define ggml_vec_dot_mxfp4_q8_0_generic ggml_vec_dot_mxfp4_q8_0 // repack.cpp #define ggml_quantize_mat_q8_0_4x4_generic ggml_quantize_mat_q8_0_4x4 #define ggml_quantize_mat_q8_0_4x8_generic ggml_quantize_mat_q8_0_4x8 @@ -147,12 +172,16 @@ #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_0_8x8_q8_0_generic ggml_gemv_q4_0_8x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_0_8x8_q8_0_generic ggml_gemm_q4_0_8x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #elif defined(__wasm__) // quants.c #define ggml_vec_dot_q4_1_q8_1_generic ggml_vec_dot_q4_1_q8_1 @@ -167,6 +196,7 @@ #define ggml_vec_dot_iq1_m_q8_K_generic ggml_vec_dot_iq1_m_q8_K #define ggml_vec_dot_iq4_nl_q8_0_generic ggml_vec_dot_iq4_nl_q8_0 #define ggml_vec_dot_iq4_xs_q8_K_generic ggml_vec_dot_iq4_xs_q8_K +#define ggml_vec_dot_mxfp4_q8_0_generic ggml_vec_dot_mxfp4_q8_0 // repack.cpp #define ggml_quantize_mat_q8_0_4x4_generic ggml_quantize_mat_q8_0_4x4 #define ggml_quantize_mat_q8_0_4x8_generic ggml_quantize_mat_q8_0_4x8 @@ -175,10 +205,14 @@ #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_0_8x8_q8_0_generic ggml_gemv_q4_0_8x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_0_8x8_q8_0_generic ggml_gemm_q4_0_8x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #endif diff --git a/ggml/src/ggml-cpu/arch/arm/quants.c b/ggml/src/ggml-cpu/arch/arm/quants.c index 3e2d3d03d6..aadbb487ec 100644 --- a/ggml/src/ggml-cpu/arch/arm/quants.c +++ b/ggml/src/ggml-cpu/arch/arm/quants.c @@ -589,6 +589,67 @@ void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sumf; } +void ggml_vec_dot_mxfp4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { + assert(nrc == 1); + UNUSED(nrc); + UNUSED(bx); + UNUSED(by); + UNUSED(bs); + assert(n % QK_MXFP4 == 0); + static_assert(QK_MXFP4 == QK8_0, "QK_MXFP4 and QK8_0 must be the same"); + + const block_mxfp4 * GGML_RESTRICT x = vx; + const block_q8_0 * GGML_RESTRICT y = vy; + + const int nb = n / QK_MXFP4; + + int ib = 0; + float sumf = 0; + +#if defined __ARM_NEON + const int8x16_t values = vld1q_s8(kvalues_mxfp4); + const uint8x16_t m4b = vdupq_n_u8(0x0f); + uint8x16x2_t q4bits; + int8x16x4_t q4b; + int8x16x4_t q8b; + int32x4_t prod_1; + int32x4_t prod_2; + + for (; ib + 1 < nb; ib += 2) { + q4bits.val[0] = vld1q_u8(x[ib + 0].qs); + q4bits.val[1] = vld1q_u8(x[ib + 1].qs); + q8b.val[0] = vld1q_s8(y[ib + 0].qs); + q8b.val[1] = vld1q_s8(y[ib + 0].qs + 16); + q8b.val[2] = vld1q_s8(y[ib + 1].qs); + q8b.val[3] = vld1q_s8(y[ib + 1].qs + 16); + + q4b.val[0] = ggml_vqtbl1q_s8(values, vandq_u8 (q4bits.val[0], m4b)); + q4b.val[1] = ggml_vqtbl1q_s8(values, vshrq_n_u8(q4bits.val[0], 4)); + q4b.val[2] = ggml_vqtbl1q_s8(values, vandq_u8 (q4bits.val[1], m4b)); + q4b.val[3] = ggml_vqtbl1q_s8(values, vshrq_n_u8(q4bits.val[1], 4)); + + prod_1 = ggml_vdotq_s32(ggml_vdotq_s32(vdupq_n_s32(0), q4b.val[0], q8b.val[0]), q4b.val[1], q8b.val[1]); + prod_2 = ggml_vdotq_s32(ggml_vdotq_s32(vdupq_n_s32(0), q4b.val[2], q8b.val[2]), q4b.val[3], q8b.val[3]); + + sumf += + GGML_E8M0_TO_FP32_HALF(x[ib + 0].e) * GGML_CPU_FP16_TO_FP32(y[ib + 0].d) * vaddvq_s32(prod_1) + + GGML_E8M0_TO_FP32_HALF(x[ib + 1].e) * GGML_CPU_FP16_TO_FP32(y[ib + 1].d) * vaddvq_s32(prod_2); + } + +#endif + for (; ib < nb; ++ib) { + const float d = GGML_CPU_FP16_TO_FP32(y[ib].d)*GGML_E8M0_TO_FP32_HALF(x[ib].e); + int sumi1 = 0; + int sumi2 = 0; + for (int j = 0; j < QK_MXFP4/2; ++j) { + sumi1 += y[ib].qs[j + 0] * kvalues_mxfp4[x[ib].qs[j] & 0xf]; + sumi2 += y[ib].qs[j + QK_MXFP4/2] * kvalues_mxfp4[x[ib].qs[j] >> 4]; + } + sumf += d * (sumi1 + sumi2); + } + *s = sumf; +} + void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { const int qk = QK8_0; const int nb = n / qk; @@ -1236,44 +1297,10 @@ void ggml_vec_dot_tq1_0_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = sumf; #else - const uint8_t pow3[6] = {1, 3, 9, 27, 81, 243}; - - float sumf = 0.0f; - - for (int i = 0; i < nb; ++i) { - int sum = 0; - - for (size_t j = 0; j < sizeof(x->qs) - sizeof(x->qs) % 32; j += 32) { - for (size_t l = 0; l < 5; ++l) { - for (size_t m = 0; m < 32; ++m) { - uint8_t q = x[i].qs[j + m] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[j*5 + l*32 + m]; - } - } - } - for (size_t j = sizeof(x->qs) - sizeof(x->qs) % 32; j < sizeof(x->qs); j += 16) { - for (size_t l = 0; l < 5; ++l) { - for (size_t m = 0; m < 16; ++m) { - uint8_t q = x[i].qs[j + m] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[j*5 + l*16 + m]; - } - } - } - - for (size_t l = 0; l < 4; ++l) { - for (size_t j = 0; j < sizeof(x->qh); ++j) { - uint8_t q = x[i].qh[j] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[sizeof(x->qs)*5 + l*sizeof(x->qh) + j]; - } - } - - sumf += (float) sum * (GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d); - } - - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_tq1_0_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1381,25 +1408,10 @@ void ggml_vec_dot_tq2_0_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = sumf; #else - float sumf = 0.0f; - - for (int i = 0; i < nb; ++i) { - int32_t sumi = 0; - - for (size_t j = 0; j < sizeof(x->qs); j += 32) { - for (size_t l = 0; l < 4; ++l) { - for (size_t k = 0; k < 32; ++k) { - sumi += y[i].qs[j*4 + l*32 + k] * (((x[i].qs[j + k] >> (l*2)) & 3) - 1); - } - } - } - - const float d = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - - sumf += (float) sumi * d; - } - - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_tq2_0_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1729,45 +1741,10 @@ void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sum; #else - - float sumf = 0; - - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2057,68 +2034,12 @@ void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sum; #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2431,61 +2352,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2578,66 +2452,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3093,47 +2915,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi } *s = sum; #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3229,34 +3014,10 @@ void ggml_vec_dot_iq2_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const *s = 0.25f * sumf; #else - - uint32_t aux32[2]; - const uint8_t * aux8 = (const uint8_t *)aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(aux32, q2, 2*sizeof(uint32_t)); - q2 += 4; - const uint32_t ls = 2*(aux32[1] >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xxs_grid + aux8[l]); - const uint8_t signs = ksigns_iq2xs[(aux32[1] >> 7*l) & 127]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3327,42 +3088,10 @@ void ggml_vec_dot_iq2_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const v *s = 0.125f * sumf; #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const uint8_t * GGML_RESTRICT sc = x[i].scales; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - const uint16_t ls1 = 2*(sc[ib32] & 0xf) + 1; - const uint16_t ls2 = 2*(sc[ib32] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls1; - sumi = 0; - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls2; - q2 += 4; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3455,45 +3184,10 @@ void ggml_vec_dot_iq2_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = 0.125f * sumf; #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint8_t * signs = qs + QK_K/8; - - int bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - int ls1 = 1 + 2*(x[i].scales[ib32] & 0xf); - int ls2 = 1 + 2*(x[i].scales[ib32] >> 4); - int sumi1 = 0, sumi2 = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi1 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi2 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += ls1 * sumi1 + ls2 * sumi2; - qs += 4; - signs += 4; - } - - sumf += d * bsum; - } - - *s = 0.125f * sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3553,36 +3247,10 @@ void ggml_vec_dot_iq3_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const *s = 0.5f * sumf; #else - - uint32_t aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT gas = x[i].qs + QK_K/4; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(&aux32, gas, sizeof(uint32_t)); gas += sizeof(uint32_t); - const uint32_t ls = 2*(aux32 >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3xxs_grid + q3[2*l+0]); - const uint8_t * grid2 = (const uint8_t *)(iq3xxs_grid + q3[2*l+1]); - const uint8_t signs = ksigns_iq2xs[(aux32 >> 7*l) & 127]; - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - q3 += 8; - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.25f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3689,48 +3357,10 @@ void ggml_vec_dot_iq3_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = sumf; #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT qs = x[i].qs; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const uint8_t * GGML_RESTRICT signs = x[i].signs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ib32 += 2) { - const uint32_t ls1 = 2*(x[i].scales[ib32/2] & 0xf) + 1; - const uint32_t ls2 = 2*(x[i].scales[ib32/2] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+0] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+0] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls1; - sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+1] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+1] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls2; - } - sumf += d * bsum; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3793,36 +3423,10 @@ void ggml_vec_dot_iq1_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = sumf; #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint16_t * qh = x[i].qh; - - int sumi = 0, sumi1 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - const int ls = 2*((qh[ib] >> 12) & 7) + 1; - const int delta = qh[ib] & 0x8000 ? -1 : 1; - int lsum = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((qh[ib] >> 3*l) & 7) << 8))); - for (int j = 0; j < 8; ++j) { - lsum += q8[j] * grid[j]; - } - q8 += 8; - } - sumi += ls * lsum; - sumi1 += ls * delta * (y[i].bsums[2*ib+0] + y[i].bsums[2*ib+1]); - qs += 4; - } - - sumf += GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d * (sumi + IQ1S_DELTA * sumi1); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq1_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3912,52 +3516,11 @@ void ggml_vec_dot_iq1_m_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = sumf; #else - - int sum1[2], sum2[2], delta[4]; - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint16_t * sc = (const uint16_t *)x[i].scales; - - scale.u16 = (sc[0] >> 12) | ((sc[1] >> 8) & 0x00f0) | ((sc[2] >> 4) & 0x0f00) | (sc[3] & 0xf000); - - int sumi1 = 0, sumi2 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - delta[0] = qh[0] & 0x08 ? -1 : 1; - delta[1] = qh[0] & 0x80 ? -1 : 1; - delta[2] = qh[1] & 0x08 ? -1 : 1; - delta[3] = qh[1] & 0x80 ? -1 : 1; - sum1[0] = sum1[1] = sum2[0] = sum2[1] = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((uint16_t)qh[l/2] << (8 - 4*(l%2))) & 0x700))); - int lsum1 = 0, lsum2 = 0; - for (int j = 0; j < 8; ++j) { - lsum1 += q8[j] * grid[j]; - lsum2 += q8[j]; - } - q8 += 8; - sum1[l/2] += lsum1; - sum2[l/2] += lsum2*delta[l]; - } - - const int ls1 = 2*((sc[ib/2] >> (6*(ib%2)+0)) & 0x7) + 1; - const int ls2 = 2*((sc[ib/2] >> (6*(ib%2)+3)) & 0x7) + 1; - - sumi1 += sum1[0] * ls1 + sum1[1] * ls2; - sumi2 += sum2[0] * ls1 + sum2[1] * ls2; - qs += 4; - qh += 2; - } - - sumf += GGML_CPU_FP16_TO_FP32(scale.f16) * y[i].d * (sumi1 + IQ1M_DELTA * sumi2); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(scale); + ggml_vec_dot_iq1_m_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -4078,37 +3641,10 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const v *s = sumf; #else - float sumf = 0; - for (int ibl = 0; ibl < nb; ++ibl) { - const float d4d8 = GGML_CPU_FP16_TO_FP32(x[ibl].d) * y[ibl].d; - uint16_t h = x[ibl].scales_h; - const uint8_t * qs = x[ibl].qs; - const int8_t * q8 = y[ibl].qs; - for (int ib = 0; ib < QK_K/32; ib += 2) { - const uint8_t ls1 = (x[ibl].scales_l[ib/2] & 0xf) | ((h << 4) & 0x30); - const uint8_t ls2 = (x[ibl].scales_l[ib/2] >> 4) | ((h << 2) & 0x30); - h >>= 4; - const float d1 = d4d8*(ls1 - 32); - const float d2 = d4d8*(ls2 - 32); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d1 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - sumi1 = sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d2 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - } - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq4_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff --git a/ggml/src/ggml-cpu/arch/arm/repack.cpp b/ggml/src/ggml-cpu/arch/arm/repack.cpp index 2f8bc9e251..fdd0a513b8 100644 --- a/ggml/src/ggml-cpu/arch/arm/repack.cpp +++ b/ggml/src/ggml-cpu/arch/arm/repack.cpp @@ -86,35 +86,9 @@ void ggml_quantize_mat_q8_0_4x4(const float * GGML_RESTRICT x, void * GGML_RESTR } } #else - // scalar - const int blck_size_interleave = 4; - float srcv[4][QK8_0]; - float id[4]; - - for (int i = 0; i < nb; i++) { - for (int row_iter = 0; row_iter < 4; row_iter++) { - float amax = 0.0f; // absolute max - - for (int j = 0; j < QK8_0; j++) { - srcv[row_iter][j] = x[row_iter * k + i * QK8_0 + j]; - amax = MAX(amax, fabsf(srcv[row_iter][j])); - } - - const float d = amax / ((1 << 7) - 1); - id[row_iter] = d ? 1.0f / d : 0.0f; - - y[i].d[row_iter] = GGML_CPU_FP32_TO_FP16(d); - } - - for (int j = 0; j < QK8_0 * 4; j++) { - int src_offset = (j / (4 * blck_size_interleave)) * blck_size_interleave; - int src_id = (j % (4 * blck_size_interleave)) / blck_size_interleave; - src_offset += (j % blck_size_interleave); - - float x0 = srcv[src_id][src_offset] * id[src_id]; - y[i].qs[j] = roundf(x0); - } - } + UNUSED(nb); + UNUSED(y); + ggml_quantize_mat_q8_0_4x4_generic(x, vy, k); #endif } @@ -205,35 +179,9 @@ void ggml_quantize_mat_q8_0_4x8(const float * GGML_RESTRICT x, void * GGML_RESTR } #else - // scalar - const int blck_size_interleave = 8; - float srcv[4][QK8_0]; - float id[4]; - - for (int i = 0; i < nb; i++) { - for (int row_iter = 0; row_iter < 4; row_iter++) { - float amax = 0.0f; // absolute max - - for (int j = 0; j < QK8_0; j++) { - srcv[row_iter][j] = x[row_iter * k + i * QK8_0 + j]; - amax = MAX(amax, fabsf(srcv[row_iter][j])); - } - - const float d = amax / ((1 << 7) - 1); - id[row_iter] = d ? 1.0f / d : 0.0f; - - y[i].d[row_iter] = GGML_CPU_FP32_TO_FP16(d); - } - - for (int j = 0; j < QK8_0 * 4; j++) { - int src_offset = (j / (4 * blck_size_interleave)) * blck_size_interleave; - int src_id = (j % (4 * blck_size_interleave)) / blck_size_interleave; - src_offset += (j % blck_size_interleave); - - float x0 = srcv[src_id][src_offset] * id[src_id]; - y[i].qs[j] = roundf(x0); - } - } + UNUSED(nb); + UNUSED(y); + ggml_quantize_mat_q8_0_4x8_generic(x, vy, k); #endif } @@ -295,29 +243,7 @@ void ggml_gemv_q4_0_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo } return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_DOTPROD) - float sumf[4]; - int sumi; - - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x4 * b_ptr = (const block_q4_0x4 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } - } - } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; - } + ggml_gemv_q4_0_4x4_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemv_q4_0_4x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -383,29 +309,7 @@ void ggml_gemv_q4_0_4x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo } return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_DOTPROD) - float sumf[4]; - int sumi; - - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x4 * b_ptr = (const block_q4_0x4 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } - } - } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; - } + ggml_gemv_q4_0_4x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -497,31 +401,7 @@ void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo #endif // #if defined(__ARM_FEATURE_SVE) #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) - { - float sumf[8]; - int sumi; - - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } - } - } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; - } - } + ggml_gemv_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemv_iq4_nl_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -591,31 +471,7 @@ void ggml_gemv_iq4_nl_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const } return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) - { - float sumf[4]; - int sumi; - - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_iq4_nlx4 * b_ptr = (const block_iq4_nlx4 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; - const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])); - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } - } - } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; - } - } + ggml_gemv_iq4_nl_4x4_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_q4_0_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -1096,40 +952,7 @@ void ggml_gemm_q4_0_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo ); return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) - { - float sumf[4][4]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x4 * b_ptr = (const block_q4_0x4 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])) >> 4; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } - } + ggml_gemm_q4_0_4x4_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_q4_0_4x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -1550,38 +1373,7 @@ void ggml_gemm_q4_0_4x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo ); return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_MATMUL_INT8) - float sumf[4][4]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x4 * b_ptr = (const block_q4_0x4 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])) >> 4; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } + ggml_gemm_q4_0_4x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -2019,38 +1811,7 @@ void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo #endif // #if defined(__ARM_FEATURE_SVE) && defined(__ARM_FEATURE_MATMUL_INT8) #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) - float sumf[4][8]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])) >> 4; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } + ggml_gemm_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_iq4_nl_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -2126,38 +1887,5 @@ void ggml_gemm_iq4_nl_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const } return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) - { - float sumf[4][4]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_iq4_nlx4 * b_ptr = (const block_iq4_nlx4 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; - const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])); - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } - } + ggml_gemm_iq4_nl_4x4_q8_0_generic(n, s, bs, vx, vy, nr, nc); } diff --git a/ggml/src/ggml-cpu/arch/loongarch/quants.c b/ggml/src/ggml-cpu/arch/loongarch/quants.c index 9e33fb3228..0f9af7bf52 100644 --- a/ggml/src/ggml-cpu/arch/loongarch/quants.c +++ b/ggml/src/ggml-cpu/arch/loongarch/quants.c @@ -544,7 +544,7 @@ void quantize_row_q8_1(const float * GGML_RESTRICT x, void * GGML_RESTRICT vy, i __m128 max4 = __lsx_vfmax_s( lasx_extractf128( max_abs, 1 ), lasx_extractf128( max_abs, 0) ); max4 = __lsx_vfmax_s( max4, (__m128)__lsx_vpickod_d((__m128i) max4, (__m128i)max4 ) ); __m128 tmp = max4; - max4 = __lsx_vfmax_s( max4, (__m128)__lsx_vextrins_w((__m128i)tmp, (__m128i)max4, 0x10 )); + max4 = __lsx_vfmax_s( max4, (__m128)__lsx_vextrins_w((__m128i)tmp, (__m128i)max4, 0x1 )); const float max_scalar = ((v4f32)max4)[0]; // Quantize these floats @@ -821,24 +821,15 @@ void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = hsum_float_8(acc) + summs; -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F); - const int v1 = (x[ib].qs[j] >> 4); - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q4_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -883,30 +874,15 @@ void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = hsum_float_8(acc); -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh & (1u << (j + 0 ))) >> (j + 0 )) << 4; - const uint8_t xh_1 = ((qh & (1u << (j + 16))) >> (j + 12)); - - const int32_t x0 = (int8_t)(((x[ib].qs[j] & 0x0F) | xh_0) - 16); - const int32_t x1 = (int8_t)(((x[ib].qs[j] >> 4) | xh_1) - 16); - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -954,30 +930,15 @@ void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = hsum_float_8(acc) + summs; -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh >> (j + 0)) << 4) & 0x10; - const uint8_t xh_1 = ((qh >> (j + 12)) ) & 0x10; - - const int32_t x0 = (x[ib].qs[j] & 0xF) | xh_0; - const int32_t x1 = (x[ib].qs[j] >> 4) | xh_1; - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1016,18 +977,15 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = hsum_float_8(acc); -#endif - for (; ib < nb; ++ib) { - int sumi = 0; - - for (int j = 0; j < qk; j++) { - sumi += x[ib].qs[j]*y[ib].qs[j]; - } - - sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q8_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1103,45 +1061,10 @@ void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = hsum_float_8(acc); #else - - float sumf = 0; - - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1239,70 +1162,13 @@ void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = hsum_float_8(acc); #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1391,61 +1257,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = hsum_float_8(acc) + ((v4f32)acc_m)[0]; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1541,66 +1360,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = hsum_float_8(acc) + ((v4f32)acc_m)[0]; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1678,47 +1445,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = hsum_float_8(acc); #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1815,34 +1545,10 @@ void ggml_vec_dot_iq2_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const *s = 0.125f * hsum_float_8(accumf); #else - - uint32_t aux32[2]; - const uint8_t * aux8 = (const uint8_t *)aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(aux32, q2, 2*sizeof(uint32_t)); - q2 += 4; - const uint32_t ls = 2*(aux32[1] >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xxs_grid + aux8[l]); - const uint8_t signs = ksigns_iq2xs[(aux32[1] >> 7*l) & 127]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1978,42 +1684,10 @@ void ggml_vec_dot_iq2_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const v *s = 0.125f * hsum_float_8(accumf); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const uint8_t * GGML_RESTRICT sc = x[i].scales; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - const uint16_t ls1 = 2*(sc[ib32] & 0xf) + 1; - const uint16_t ls2 = 2*(sc[ib32] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls1; - sumi = 0; - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls2; - q2 += 4; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2105,47 +1779,11 @@ void ggml_vec_dot_iq2_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = 0.125f * hsum_float_8(accumf); #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint8_t * signs = qs + QK_K/8; - - int bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - int ls1 = 1 + 2*(x[i].scales[ib32] & 0xf); - int ls2 = 1 + 2*(x[i].scales[ib32] >> 4); - int sumi1 = 0, sumi2 = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi1 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi2 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += ls1 * sumi1 + ls2 * sumi2; - qs += 4; - signs += 4; - } - - sumf += d * bsum; - } - - *s = 0.125f * sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_iq3_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -2209,36 +1847,10 @@ void ggml_vec_dot_iq3_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const *s = 0.25f * hsum_float_8(accumf); #else - - uint32_t aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT gas = x[i].qs + QK_K/4; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(&aux32, gas, sizeof(uint32_t)); gas += sizeof(uint32_t); - const uint32_t ls = 2*(aux32 >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3xxs_grid + q3[2*l+0]); - const uint8_t * grid2 = (const uint8_t *)(iq3xxs_grid + q3[2*l+1]); - const uint8_t signs = ksigns_iq2xs[(aux32 >> 7*l) & 127]; - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - q3 += 8; - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.25f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2338,48 +1950,10 @@ void ggml_vec_dot_iq3_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = hsum_float_8(accumf); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT qs = x[i].qs; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const uint8_t * GGML_RESTRICT signs = x[i].signs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ib32 += 2) { - const uint32_t ls1 = 2*(x[i].scales[ib32/2] & 0xf) + 1; - const uint32_t ls2 = 2*(x[i].scales[ib32/2] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+0] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+0] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls1; - sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+1] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+1] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls2; - } - sumf += d * bsum; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2460,36 +2034,10 @@ void ggml_vec_dot_iq1_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = hsum_float_8(accum) + IQ1S_DELTA * accum1; #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint16_t * qh = x[i].qh; - - int sumi = 0, sumi1 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - const int ls = 2*((qh[ib] >> 12) & 7) + 1; - const int delta = qh[ib] & 0x8000 ? -1 : 1; - int lsum = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((qh[ib] >> 3*l) & 7) << 8))); - for (int j = 0; j < 8; ++j) { - lsum += q8[j] * grid[j]; - } - q8 += 8; - } - sumi += ls * lsum; - sumi1 += ls * delta * (y[i].bsums[2*ib+0] + y[i].bsums[2*ib+1]); - qs += 4; - } - - sumf += GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d * (sumi + IQ1S_DELTA * sumi1); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq1_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2603,37 +2151,10 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const v *s = hsum_float_8(accum); #else - float sumf = 0; - for (int ibl = 0; ibl < nb; ++ibl) { - const float d4d8 = GGML_CPU_FP16_TO_FP32(x[ibl].d) * y[ibl].d; - uint16_t h = x[ibl].scales_h; - const uint8_t * qs = x[ibl].qs; - const int8_t * q8 = y[ibl].qs; - for (int ib = 0; ib < QK_K/32; ib += 2) { - const uint8_t ls1 = (x[ibl].scales_l[ib/2] & 0xf) | ((h << 4) & 0x30); - const uint8_t ls2 = (x[ibl].scales_l[ib/2] >> 4) | ((h << 2) & 0x30); - h >>= 4; - const float d1 = d4d8*(ls1 - 32); - const float d2 = d4d8*(ls2 - 32); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d1 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - sumi1 = sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d2 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - } - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq4_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff --git a/ggml/src/ggml-cpu/arch/powerpc/quants.c b/ggml/src/ggml-cpu/arch/powerpc/quants.c index 053d5cbdc7..49aae7a23b 100644 --- a/ggml/src/ggml-cpu/arch/powerpc/quants.c +++ b/ggml/src/ggml-cpu/arch/powerpc/quants.c @@ -201,24 +201,14 @@ void ggml_vec_dot_q4_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = vec_extract(vsumf0, 0); -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F) - 8; - const int v1 = (x[ib].qs[j] >> 4) - 8; - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += sumi*GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d); - } - *s = sumf; +#else + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q4_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -278,24 +268,14 @@ void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = vec_extract(vsumf0, 0); -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F); - const int v1 = (x[ib].qs[j] >> 4); - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q4_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -360,30 +340,14 @@ void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = vec_extract(vsumf0, 0); -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh & (1u << (j + 0 ))) >> (j + 0 )) << 4; - const uint8_t xh_1 = ((qh & (1u << (j + 16))) >> (j + 12)); - - const int32_t x0 = (int8_t)(((x[ib].qs[j] & 0x0F) | xh_0) - 16); - const int32_t x1 = (int8_t)(((x[ib].qs[j] >> 4) | xh_1) - 16); - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; - } - *s = sumf; +#else + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -451,30 +415,15 @@ void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = vec_extract(vsumf0, 0); -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh >> (j + 0)) << 4) & 0x10; - const uint8_t xh_1 = ((qh >> (j + 12)) ) & 0x10; - - const int32_t x0 = (x[ib].qs[j] & 0xF) | xh_0; - const int32_t x1 = (x[ib].qs[j] >> 4) | xh_1; - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -535,18 +484,15 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = vec_extract(vsumf0, 0); -#endif - for (; ib < nb; ++ib) { - int sumi = 0; - - for (int j = 0; j < qk; j++) { - sumi += x[ib].qs[j]*y[ib].qs[j]; - } - - sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q8_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -695,45 +641,10 @@ void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = vec_extract(vsumf0, 0); #else - - float sumf = 0; - - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -907,70 +818,13 @@ void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = vec_extract(vsumf0, 0); #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1130,61 +984,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = vec_extract(vsumf0, 0); #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1342,66 +1149,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = vec_extract(vsumf0, 0); #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1556,47 +1311,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = vec_extract(vsumf0, 0); #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1737,34 +1455,10 @@ void ggml_vec_dot_iq2_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const *s = 0.125f * vec_extract(vsumf0, 0); #else - - uint32_t aux32[2]; - const uint8_t * aux8 = (const uint8_t *)aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(aux32, q2, 2*sizeof(uint32_t)); - q2 += 4; - const uint32_t ls = 2*(aux32[1] >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xxs_grid + aux8[l]); - const uint8_t signs = ksigns_iq2xs[(aux32[1] >> 7*l) & 127]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1869,42 +1563,10 @@ void ggml_vec_dot_iq2_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const v *s = 0.125f * vec_extract(vsumf0, 0); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const uint8_t * GGML_RESTRICT sc = x[i].scales; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - const uint16_t ls1 = 2*(sc[ib32] & 0xf) + 1; - const uint16_t ls2 = 2*(sc[ib32] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls1; - sumi = 0; - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls2; - q2 += 4; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2030,47 +1692,11 @@ void ggml_vec_dot_iq2_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = 0.125f * vec_extract(vsumf0, 0); #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint8_t * signs = qs + QK_K/8; - - int bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - int ls1 = 1 + 2*(x[i].scales[ib32] & 0xf); - int ls2 = 1 + 2*(x[i].scales[ib32] >> 4); - int sumi1 = 0, sumi2 = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi1 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi2 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += ls1 * sumi1 + ls2 * sumi2; - qs += 4; - signs += 4; - } - - sumf += d * bsum; - } - - *s = 0.125f * sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_iq3_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -2172,36 +1798,10 @@ void ggml_vec_dot_iq3_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const *s = 0.25f * vec_extract(vsumf0, 0); #else - - uint32_t aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT gas = x[i].qs + QK_K/4; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(&aux32, gas, sizeof(uint32_t)); gas += sizeof(uint32_t); - const uint32_t ls = 2*(aux32 >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3xxs_grid + q3[2*l+0]); - const uint8_t * grid2 = (const uint8_t *)(iq3xxs_grid + q3[2*l+1]); - const uint8_t signs = ksigns_iq2xs[(aux32 >> 7*l) & 127]; - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - q3 += 8; - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.25f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2327,48 +1927,10 @@ void ggml_vec_dot_iq3_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = vec_extract(vsumf0, 0); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT qs = x[i].qs; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const uint8_t * GGML_RESTRICT signs = x[i].signs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ib32 += 2) { - const uint32_t ls1 = 2*(x[i].scales[ib32/2] & 0xf) + 1; - const uint32_t ls2 = 2*(x[i].scales[ib32/2] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+0] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+0] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls1; - sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+1] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+1] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls2; - } - sumf += d * bsum; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2481,36 +2043,10 @@ void ggml_vec_dot_iq1_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = vec_extract(vsumf0, 0); #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint16_t * qh = x[i].qh; - - int sumi = 0, sumi1 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - const int ls = 2*((qh[ib] >> 12) & 7) + 1; - const int delta = qh[ib] & 0x8000 ? -1 : 1; - int lsum = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((qh[ib] >> 3*l) & 7) << 8))); - for (int j = 0; j < 8; ++j) { - lsum += q8[j] * grid[j]; - } - q8 += 8; - } - sumi += ls * lsum; - sumi1 += ls * delta * (y[i].bsums[2*ib+0] + y[i].bsums[2*ib+1]); - qs += 4; - } - - sumf += GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d * (sumi + IQ1S_DELTA * sumi1); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq1_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2581,17 +2117,15 @@ void ggml_vec_dot_iq4_nl_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const v sumf = vec_extract(vsumf0, 0); -#endif - for (; ib < nb; ++ib) { - const float d = GGML_CPU_FP16_TO_FP32(y[ib].d)*GGML_CPU_FP16_TO_FP32(x[ib].d); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < QK4_NL/2; ++j) { - sumi1 += y[ib].qs[j+ 0] * kvalues_iq4nl[x[ib].qs[j] & 0xf]; - sumi2 += y[ib].qs[j+QK4_NL/2] * kvalues_iq4nl[x[ib].qs[j] >> 4]; - } - sumf += d * (sumi1 + sumi2); - } *s = sumf; +#else + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_iq4_nl_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_iq4_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -2696,37 +2230,10 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const v *s = vec_extract(vsumf0, 0); #else - float sumf = 0; - for (int ibl = 0; ibl < nb; ++ibl) { - const float d4d8 = GGML_CPU_FP16_TO_FP32(x[ibl].d) * y[ibl].d; - uint16_t h = x[ibl].scales_h; - const uint8_t * qs = x[ibl].qs; - const int8_t * q8 = y[ibl].qs; - for (int ib = 0; ib < QK_K/32; ib += 2) { - const uint8_t ls1 = (x[ibl].scales_l[ib/2] & 0xf) | ((h << 4) & 0x30); - const uint8_t ls2 = (x[ibl].scales_l[ib/2] >> 4) | ((h << 2) & 0x30); - h >>= 4; - const float d1 = d4d8*(ls1 - 32); - const float d2 = d4d8*(ls2 - 32); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d1 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - sumi1 = sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d2 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - } - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq4_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff --git a/ggml/src/ggml-cpu/arch/riscv/quants.c b/ggml/src/ggml-cpu/arch/riscv/quants.c index 8b64d8adc4..6c74417c90 100644 --- a/ggml/src/ggml-cpu/arch/riscv/quants.c +++ b/ggml/src/ggml-cpu/arch/riscv/quants.c @@ -116,6 +116,7 @@ void quantize_row_q8_1(const float * GGML_RESTRICT x, void * GGML_RESTRICT vy, i //===================================== Dot products ================================= void ggml_vec_dot_q4_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { +#if defined(__riscv_v) const int qk = QK8_0; const int nb = n / qk; @@ -132,7 +133,6 @@ void ggml_vec_dot_q4_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi int ib = 0; float sumf = 0; -#if defined(__riscv_v) size_t vl = qk / 2; for (; ib < nb; ++ib) { @@ -164,27 +164,14 @@ void ggml_vec_dot_q4_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf += sumi*GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d); } -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F) - 8; - const int v1 = (x[ib].qs[j] >> 4) - 8; - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += sumi*GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d); - } - *s = sumf; +#else + ggml_vec_dot_q4_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { +#if defined(__riscv_v) const int qk = QK8_1; const int nb = n / qk; @@ -201,7 +188,6 @@ void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi int ib = 0; float sumf = 0; -#if defined(__riscv_v) size_t vl = qk / 2; for (; ib < nb; ++ib) { @@ -229,27 +215,14 @@ void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); } -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F); - const int v1 = (x[ib].qs[j] >> 4); - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + ggml_vec_dot_q4_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { +#if defined(__riscv_v) const int qk = QK8_0; const int nb = n / qk; @@ -267,7 +240,6 @@ void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi const block_q5_0 * GGML_RESTRICT x = vx; const block_q8_0 * GGML_RESTRICT y = vy; -#if defined(__riscv_v) size_t vl; size_t vlenb = __riscv_vlenb(); @@ -297,33 +269,14 @@ void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d) * GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; } -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh & (1u << (j + 0 ))) >> (j + 0 )) << 4; - const uint8_t xh_1 = ((qh & (1u << (j + 16))) >> (j + 12)); - - const int32_t x0 = (int8_t)(((x[ib].qs[j] & 0x0F) | xh_0) - 16); - const int32_t x1 = (int8_t)(((x[ib].qs[j] >> 4) | xh_1) - 16); - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; - } - *s = sumf; +#else + ggml_vec_dot_q5_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { +#if defined(__riscv_v) const int qk = QK8_1; const int nb = n / qk; @@ -341,7 +294,6 @@ void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi const block_q5_1 * GGML_RESTRICT x = vx; const block_q8_1 * GGML_RESTRICT y = vy; -#if defined(__riscv_v) size_t vl; size_t vlenb = __riscv_vlenb(); @@ -370,30 +322,10 @@ void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); } -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh >> (j + 0)) << 4) & 0x10; - const uint8_t xh_1 = ((qh >> (j + 12)) ) & 0x10; - - const int32_t x0 = (x[ib].qs[j] & 0xF) | xh_0; - const int32_t x1 = (x[ib].qs[j] >> 4) | xh_1; - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + ggml_vec_dot_q5_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -431,18 +363,17 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); } -#endif - for (; ib < nb; ++ib) { - int sumi = 0; - - for (int j = 0; j < qk; j++) { - sumi += x[ib].qs[j]*y[ib].qs[j]; - } - - sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); - } - *s = sumf; +#else + + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + + ggml_vec_dot_q8_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -738,44 +669,11 @@ void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi #else - float sumf = 0; + UNUSED(x); + UNUSED(y); + UNUSED(nb); - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1147,68 +1045,14 @@ void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sumf; #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1534,60 +1378,15 @@ void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi #else - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; + UNUSED(x); + UNUSED(y); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(nb); + UNUSED(utmp); - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1698,65 +1497,15 @@ void ggml_vec_dot_q5_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi #else - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; + UNUSED(x); + UNUSED(y); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(nb); + UNUSED(utmp); - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2024,46 +1773,11 @@ void ggml_vec_dot_q6_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi #else - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); + UNUSED(x); + UNUSED(y); + UNUSED(nb); - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff --git a/ggml/src/ggml-cpu/arch/riscv/repack.cpp b/ggml/src/ggml-cpu/arch/riscv/repack.cpp index 45c91a6948..2a35ff9ad8 100644 --- a/ggml/src/ggml-cpu/arch/riscv/repack.cpp +++ b/ggml/src/ggml-cpu/arch/riscv/repack.cpp @@ -112,31 +112,7 @@ void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo } #endif - { - float sumf[8]; - int sumi; - - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } - } - } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; - } - } + ggml_gemv_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -361,37 +337,6 @@ void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo return; } -#endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) - float sumf[4][8]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])) >> 4; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } +#endif + ggml_gemm_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } diff --git a/ggml/src/ggml-cpu/arch/s390/quants.c b/ggml/src/ggml-cpu/arch/s390/quants.c index a840219a4f..7e4229d0e4 100644 --- a/ggml/src/ggml-cpu/arch/s390/quants.c +++ b/ggml/src/ggml-cpu/arch/s390/quants.c @@ -172,24 +172,15 @@ void ggml_vec_dot_q4_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = acc[0] + acc[1] + acc[2] + acc[3]; -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F) - 8; - const int v1 = (x[ib].qs[j] >> 4) - 8; - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += sumi*GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q4_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -239,24 +230,15 @@ void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = acc[0] + acc[1] + acc[2] + acc[3] + summs; -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F); - const int v1 = (x[ib].qs[j] >> 4); - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q4_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -298,18 +280,15 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = acc[0] + acc[1] + acc[2] + acc[3]; -#endif - for (; ib < nb; ++ib) { - int sumi = 0; - - for (int j = 0; j < qk; j++) { - sumi += x[ib].qs[j]*y[ib].qs[j]; - } - - sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q8_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -442,70 +421,13 @@ void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sum; #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -600,61 +522,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -767,66 +642,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -969,47 +792,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sum; #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1186,17 +972,15 @@ void ggml_vec_dot_iq4_nl_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const v sumf += GGML_CPU_FP16_TO_FP32(x0->d) * GGML_CPU_FP16_TO_FP32(y0->d) * (v_xy[0] + v_xy[1] + v_xy[2] + v_xy[3]); } -#endif - for (; ib < nb; ++ib) { - const float d = GGML_CPU_FP16_TO_FP32(y[ib].d)*GGML_CPU_FP16_TO_FP32(x[ib].d); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < QK4_NL/2; ++j) { - sumi1 += y[ib].qs[j+ 0] * kvalues_iq4nl[x[ib].qs[j] & 0xf]; - sumi2 += y[ib].qs[j+QK4_NL/2] * kvalues_iq4nl[x[ib].qs[j] >> 4]; - } - sumf += d * (sumi1 + sumi2); - } *s = sumf; +#else + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_iq4_nl_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_iq4_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1264,37 +1048,10 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const v *s = sumf; #else - float sumf = 0; - for (int ibl = 0; ibl < nb; ++ibl) { - const float d4d8 = GGML_CPU_FP16_TO_FP32(x[ibl].d) * y[ibl].d; - uint16_t h = x[ibl].scales_h; - const uint8_t * qs = x[ibl].qs; - const int8_t * q8 = y[ibl].qs; - for (int ib = 0; ib < QK_K/32; ib += 2) { - const uint8_t ls1 = (x[ibl].scales_l[ib/2] & 0xf) | ((h << 4) & 0x30); - const uint8_t ls2 = (x[ibl].scales_l[ib/2] >> 4) | ((h << 2) & 0x30); - h >>= 4; - const float d1 = d4d8*(ls1 - 32); - const float d2 = d4d8*(ls2 - 32); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d1 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - sumi1 = sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d2 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - } - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq4_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff --git a/ggml/src/ggml-cpu/arch/wasm/quants.c b/ggml/src/ggml-cpu/arch/wasm/quants.c index b0904d8a3a..74a359e6d1 100644 --- a/ggml/src/ggml-cpu/arch/wasm/quants.c +++ b/ggml/src/ggml-cpu/arch/wasm/quants.c @@ -435,30 +435,15 @@ void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = wasm_f32x4_extract_lane(sumv, 0) + wasm_f32x4_extract_lane(sumv, 1) + wasm_f32x4_extract_lane(sumv, 2) + wasm_f32x4_extract_lane(sumv, 3); -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh & (1u << (j + 0 ))) >> (j + 0 )) << 4; - const uint8_t xh_1 = ((qh & (1u << (j + 16))) >> (j + 12)); - - const int32_t x0 = (int8_t)(((x[ib].qs[j] & 0x0F) | xh_0) - 16); - const int32_t x1 = (int8_t)(((x[ib].qs[j] >> 4) | xh_1) - 16); - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -545,30 +530,15 @@ void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = wasm_f32x4_extract_lane(sumv, 0) + wasm_f32x4_extract_lane(sumv, 1) + wasm_f32x4_extract_lane(sumv, 2) + wasm_f32x4_extract_lane(sumv, 3) + summs; -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh >> (j + 0)) << 4) & 0x10; - const uint8_t xh_1 = ((qh >> (j + 12)) ) & 0x10; - - const int32_t x0 = (x[ib].qs[j] & 0xF) | xh_0; - const int32_t x1 = (x[ib].qs[j] >> 4) | xh_1; - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -628,18 +598,15 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi sumf = wasm_f32x4_extract_lane(sumv, 0) + wasm_f32x4_extract_lane(sumv, 1) + wasm_f32x4_extract_lane(sumv, 2) + wasm_f32x4_extract_lane(sumv, 3); -#endif - for (; ib < nb; ++ib) { - int sumi = 0; - - for (int j = 0; j < qk; j++) { - sumi += x[ib].qs[j]*y[ib].qs[j]; - } - - sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q8_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -755,45 +722,10 @@ void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sumf; #else - - float sumf = 0; - - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -902,68 +834,12 @@ void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sumf; #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1089,61 +965,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1279,66 +1108,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1435,47 +1212,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = sumf; #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff --git a/ggml/src/ggml-cpu/arch/x86/quants.c b/ggml/src/ggml-cpu/arch/x86/quants.c index e7527c00a8..cb49320a67 100644 --- a/ggml/src/ggml-cpu/arch/x86/quants.c +++ b/ggml/src/ggml-cpu/arch/x86/quants.c @@ -66,6 +66,12 @@ static inline int hsum_i32_4(const __m128i a) { } #if defined(__AVX2__) || defined(__AVX512F__) +static inline __m256i mul_add_epi8(const __m256i x, const __m256i y) { + const __m256i ax = _mm256_sign_epi8(x, x); + const __m256i sy = _mm256_sign_epi8(y, x); + return _mm256_maddubs_epi16(ax, sy); +} + // spread 32 bits to 32 bytes { 0x00, 0xFF } static inline __m256i bytes_from_bits_32(const uint8_t * x) { uint32_t x32; @@ -261,6 +267,11 @@ static inline __m256 quad_fp16_delta_float(const float x0, const float y0, const return _mm256_set_m128(_mm_set1_ps(GGML_CPU_FP16_TO_FP32(x1) * GGML_CPU_FP16_TO_FP32(y1)), _mm_set1_ps(GGML_CPU_FP16_TO_FP32(x0) * GGML_CPU_FP16_TO_FP32(y0))); } + +static inline __m256 quad_mx_delta_float(const int8_t x0, const float y0, const int8_t x1, const float y1) { + return _mm256_set_m128(_mm_set1_ps(GGML_E8M0_TO_FP32_HALF(x1) * GGML_CPU_FP16_TO_FP32(y1)), + _mm_set1_ps(GGML_E8M0_TO_FP32_HALF(x0) * GGML_CPU_FP16_TO_FP32(y0))); +} #endif #elif defined(__SSSE3__) // horizontally add 4x4 floats @@ -702,7 +713,6 @@ void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi const block_q8_1 * GGML_RESTRICT y = vy; int ib = 0; - float sumf = 0; #if defined(__AVX2__) || defined(__AVX__) // Initialize accumulator with zeros @@ -737,25 +747,98 @@ void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi #endif } - sumf = hsum_float_8(acc) + summs; + *s = hsum_float_8(acc) + summs; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + ggml_vec_dot_q4_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif +} + +void ggml_vec_dot_mxfp4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { + assert(nrc == 1); + UNUSED(nrc); + UNUSED(bx); + UNUSED(by); + UNUSED(bs); + assert(n % QK_MXFP4 == 0); + static_assert(QK_MXFP4 == QK8_0, "QK_MXFP4 and QK8_0 must be the same"); + + const block_mxfp4 * GGML_RESTRICT x = vx; + const block_q8_0 * GGML_RESTRICT y = vy; + + const int nb = n / QK_MXFP4; + + int ib = 0; + float sumf = 0; + +#if defined __AVX2__ + + const __m128i values128 = _mm_loadu_si128((const __m128i*)kvalues_mxfp4); + const __m128i m4b = _mm_set1_epi8(0x0f); + const __m256i mone = _mm256_set1_epi16(1); + + __m256 accum1 = _mm256_setzero_ps(); + __m256 accum2 = _mm256_setzero_ps(); + for (; ib + 1 < nb; ib += 2) { + const __m128i q4bits_1 = _mm_loadu_si128((const __m128i*)x[ib + 0].qs); + const __m128i q4bits_2 = _mm_loadu_si128((const __m128i*)x[ib + 1].qs); + const __m256i q8b_1 = _mm256_loadu_si256((const __m256i *)y[ib + 0].qs); + const __m256i q8b_2 = _mm256_loadu_si256((const __m256i *)y[ib + 1].qs); + const __m256i q4b_1 = MM256_SET_M128I(_mm_shuffle_epi8(values128, _mm_and_si128(_mm_srli_epi16(q4bits_1, 4), m4b)), + _mm_shuffle_epi8(values128, _mm_and_si128(q4bits_1, m4b))); + const __m256i q4b_2 = MM256_SET_M128I(_mm_shuffle_epi8(values128, _mm_and_si128(_mm_srli_epi16(q4bits_2, 4), m4b)), + _mm_shuffle_epi8(values128, _mm_and_si128(q4bits_2, m4b))); + const __m256i p16_1 = mul_add_epi8(q4b_1, q8b_1); + const __m256i p16_2 = mul_add_epi8(q4b_2, q8b_2); + const __m256i p_1 = _mm256_madd_epi16(p16_1, mone); + const __m256i p_2 = _mm256_madd_epi16(p16_2, mone); + accum1 = _mm256_fmadd_ps(_mm256_set1_ps(GGML_CPU_FP16_TO_FP32(y[ib + 0].d)*GGML_E8M0_TO_FP32_HALF(x[ib + 0].e)), + _mm256_cvtepi32_ps(p_1), accum1); + accum2 = _mm256_fmadd_ps(_mm256_set1_ps(GGML_CPU_FP16_TO_FP32(y[ib + 1].d)*GGML_E8M0_TO_FP32_HALF(x[ib + 1].e)), + _mm256_cvtepi32_ps(p_2), accum2); + } + + sumf = hsum_float_8(_mm256_add_ps(accum1, accum2)); + +#elif defined __AVX__ + const __m128i values128 = _mm_loadu_si128((const __m128i*)kvalues_mxfp4); + const __m128i m4b = _mm_set1_epi8(0x0f); + + __m256 accum = _mm256_setzero_ps(); + for (; ib + 1 < nb; ib += 2) { + const __m128i q4bits_1 = _mm_loadu_si128((const __m128i *)x[ib + 0].qs); + const __m128i q4bits_2 = _mm_loadu_si128((const __m128i *)x[ib + 1].qs); + const __m128i q8b_1_0 = _mm_loadu_si128((const __m128i *)y[ib + 0].qs); + const __m128i q8b_1_1 = _mm_loadu_si128((const __m128i *)y[ib + 0].qs + 1); + const __m128i q8b_2_0 = _mm_loadu_si128((const __m128i *)y[ib + 1].qs); + const __m128i q8b_2_1 = _mm_loadu_si128((const __m128i *)y[ib + 1].qs + 1); + + const __m128i q4b_1_0 = _mm_shuffle_epi8(values128, _mm_and_si128(q4bits_1, m4b)); + const __m128i q4b_1_1 = _mm_shuffle_epi8(values128, _mm_and_si128(_mm_srli_epi16(q4bits_1, 4), m4b)); + const __m128i q4b_2_0 = _mm_shuffle_epi8(values128, _mm_and_si128(q4bits_2, m4b)); + const __m128i q4b_2_1 = _mm_shuffle_epi8(values128, _mm_and_si128(_mm_srli_epi16(q4bits_2, 4), m4b)); + + const __m256 p = mul_sum_i8_quad_float(q4b_1_0, q4b_1_1, q4b_2_0, q4b_2_1, q8b_1_0, q8b_1_1, q8b_2_0, q8b_2_1); + const __m256 deltas = quad_mx_delta_float(x[ib].e, y[ib].d, x[ib + 1].e, y[ib + 1].d); + accum = _mm256_add_ps(_mm256_mul_ps(deltas, p), accum); + } + + sumf = hsum_float_8(accum); #endif for (; ib < nb; ++ib) { - int sumi0 = 0; + const float d = GGML_CPU_FP16_TO_FP32(y[ib].d)*GGML_E8M0_TO_FP32_HALF(x[ib].e); int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F); - const int v1 = (x[ib].qs[j] >> 4); - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); + int sumi2 = 0; + for (int j = 0; j < QK_MXFP4/2; ++j) { + sumi1 += y[ib].qs[j + 0] * kvalues_mxfp4[x[ib].qs[j] & 0xf]; + sumi2 += y[ib].qs[j + QK_MXFP4/2] * kvalues_mxfp4[x[ib].qs[j] >> 4]; } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); + sumf += d * (sumi1 + sumi2); } - *s = sumf; } @@ -764,7 +847,6 @@ void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi const int nb = n / qk; int ib = 0; - float sumf = 0; assert(n % qk == 0); assert(qk == QK5_0); @@ -799,7 +881,7 @@ void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi acc = _mm256_fmadd_ps(d, q, acc); } - sumf = hsum_float_8(acc); + *s = hsum_float_8(acc); #elif defined(__AVX__) // Initialize accumulator with zeros __m256 acc = _mm256_setzero_ps(); @@ -830,32 +912,14 @@ void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi acc = _mm256_add_ps(_mm256_mul_ps(d, q), acc); } - sumf = hsum_float_8(acc); - + *s = hsum_float_8(acc); +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh & (1u << (j + 0 ))) >> (j + 0 )) << 4; - const uint8_t xh_1 = ((qh & (1u << (j + 16))) >> (j + 12)); - - const int32_t x0 = (int8_t)(((x[ib].qs[j] & 0x0F) | xh_0) - 16); - const int32_t x1 = (int8_t)(((x[ib].qs[j] >> 4) | xh_1) - 16); - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; - } - - *s = sumf; } void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -863,7 +927,6 @@ void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi const int nb = n / qk; int ib = 0; - float sumf = 0; assert(n % qk == 0); assert(qk == QK5_1); @@ -901,7 +964,7 @@ void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi acc = _mm256_fmadd_ps(q, _mm256_mul_ps(dx, dy), acc); } - sumf = hsum_float_8(acc) + summs; + *s = hsum_float_8(acc) + summs; #elif defined(__AVX__) // Initialize accumulator with zeros __m256 acc = _mm256_setzero_ps(); @@ -935,32 +998,14 @@ void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const voi acc = _mm256_add_ps(_mm256_mul_ps(q, _mm256_mul_ps(dx, dy)), acc); } - sumf = hsum_float_8(acc) + summs; - + *s = hsum_float_8(acc) + summs; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh >> (j + 0)) << 4) & 0x10; - const uint8_t xh_1 = ((qh >> (j + 12)) ) & 0x10; - - const int32_t x0 = (x[ib].qs[j] & 0xF) | xh_0; - const int32_t x1 = (x[ib].qs[j] >> 4) | xh_1; - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - - *s = sumf; } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1017,7 +1062,6 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi } sumf = hsum_float_8(accum); - #endif for (; ib < nb; ++ib) { int sumi = 0; @@ -1157,44 +1201,10 @@ void ggml_vec_dot_tq1_0_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = hsum_float_8(sumf); #else - const uint8_t pow3[6] = {1, 3, 9, 27, 81, 243}; - - float sumf = 0.0f; - - for (int i = 0; i < nb; ++i) { - int sum = 0; - - for (size_t j = 0; j < sizeof(x->qs) - sizeof(x->qs) % 32; j += 32) { - for (size_t l = 0; l < 5; ++l) { - for (size_t m = 0; m < 32; ++m) { - uint8_t q = x[i].qs[j + m] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[j*5 + l*32 + m]; - } - } - } - for (size_t j = sizeof(x->qs) - sizeof(x->qs) % 32; j < sizeof(x->qs); j += 16) { - for (size_t l = 0; l < 5; ++l) { - for (size_t m = 0; m < 16; ++m) { - uint8_t q = x[i].qs[j + m] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[j*5 + l*16 + m]; - } - } - } - - for (size_t l = 0; l < 4; ++l) { - for (size_t j = 0; j < sizeof(x->qh); ++j) { - uint8_t q = x[i].qh[j] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[sizeof(x->qs)*5 + l*sizeof(x->qh) + j]; - } - } - - sumf += (float) sum * (GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d); - } - - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_tq1_0_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1257,25 +1267,10 @@ void ggml_vec_dot_tq2_0_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = hsum_float_8(sumf); #else - float sumf = 0.0f; - - for (int i = 0; i < nb; ++i) { - int32_t sumi = 0; - - for (size_t j = 0; j < sizeof(x->qs); j += 32) { - for (size_t l = 0; l < 4; ++l) { - for (size_t k = 0; k < 32; ++k) { - sumi += y[i].qs[j*4 + l*32 + k] * (((x[i].qs[j + k] >> (l*2)) & 3) - 1); - } - } - } - - const float d = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - - sumf += (float) sumi * d; - } - - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_tq2_0_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1464,45 +1459,10 @@ void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = hsum_float_8(acc); #else - - float sumf = 0; - - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1769,70 +1729,13 @@ void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = hsum_float_8(acc); #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -2002,61 +1905,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = hsum_float_8(acc) + _mm_cvtss_f32(acc_m); #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2259,66 +2115,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = hsum_float_8(acc) + summs; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2520,47 +2324,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const voi *s = hsum_float_8(acc); #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2712,34 +2479,10 @@ void ggml_vec_dot_iq2_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const *s = 0.125f * hsum_float_8(accumf); #else - - uint32_t aux32[2]; - const uint8_t * aux8 = (const uint8_t *)aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(aux32, q2, 2*sizeof(uint32_t)); - q2 += 4; - const uint32_t ls = 2*(aux32[1] >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xxs_grid + aux8[l]); - const uint8_t signs = ksigns_iq2xs[(aux32[1] >> 7*l) & 127]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3033,42 +2776,10 @@ void ggml_vec_dot_iq2_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const v *s = 0.125f * hsum_float_8(accumf); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const uint8_t * GGML_RESTRICT sc = x[i].scales; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - const uint16_t ls1 = 2*(sc[ib32] & 0xf) + 1; - const uint16_t ls2 = 2*(sc[ib32] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls1; - sumi = 0; - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls2; - q2 += 4; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3250,47 +2961,11 @@ void ggml_vec_dot_iq2_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = 0.125f * hsum_float_8(accumf); #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint8_t * signs = qs + QK_K/8; - - int bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - int ls1 = 1 + 2*(x[i].scales[ib32] & 0xf); - int ls2 = 1 + 2*(x[i].scales[ib32] >> 4); - int sumi1 = 0, sumi2 = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi1 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi2 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += ls1 * sumi1 + ls2 * sumi2; - qs += 4; - signs += 4; - } - - sumf += d * bsum; - } - - *s = 0.125f * sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_iq3_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -3410,36 +3085,10 @@ void ggml_vec_dot_iq3_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const *s = 0.25f * hsum_float_8(accumf); #else - - uint32_t aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT gas = x[i].qs + QK_K/4; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(&aux32, gas, sizeof(uint32_t)); gas += sizeof(uint32_t); - const uint32_t ls = 2*(aux32 >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3xxs_grid + q3[2*l+0]); - const uint8_t * grid2 = (const uint8_t *)(iq3xxs_grid + q3[2*l+1]); - const uint8_t signs = ksigns_iq2xs[(aux32 >> 7*l) & 127]; - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - q3 += 8; - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.25f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3646,59 +3295,13 @@ void ggml_vec_dot_iq3_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = hsum_float_8(accumf); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT qs = x[i].qs; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const uint8_t * GGML_RESTRICT signs = x[i].signs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ib32 += 2) { - const uint32_t ls1 = 2*(x[i].scales[ib32/2] & 0xf) + 1; - const uint32_t ls2 = 2*(x[i].scales[ib32/2] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+0] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+0] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls1; - sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+1] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+1] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls2; - } - sumf += d * bsum; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } -#if defined(__AVX2__) -static inline __m256i mul_add_epi8(const __m256i x, const __m256i y) { - const __m256i ax = _mm256_sign_epi8(x, x); - const __m256i sy = _mm256_sign_epi8(y, x); - return _mm256_maddubs_epi16(ax, sy); -} -#endif - void ggml_vec_dot_iq1_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { assert(n % QK_K == 0); assert(nrc == 1); @@ -3811,36 +3414,10 @@ void ggml_vec_dot_iq1_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = hsum_float_8(accum) + IQ1S_DELTA * accum1; #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint16_t * qh = x[i].qh; - - int sumi = 0, sumi1 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - const int ls = 2*((qh[ib] >> 12) & 7) + 1; - const int delta = qh[ib] & 0x8000 ? -1 : 1; - int lsum = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((qh[ib] >> 3*l) & 7) << 8))); - for (int j = 0; j < 8; ++j) { - lsum += q8[j] * grid[j]; - } - q8 += 8; - } - sumi += ls * lsum; - sumi1 += ls * delta * (y[i].bsums[2*ib+0] + y[i].bsums[2*ib+1]); - qs += 4; - } - - sumf += GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d * (sumi + IQ1S_DELTA * sumi1); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq1_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -4043,52 +3620,11 @@ void ggml_vec_dot_iq1_m_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo *s = hsum_float_8(accum1) + IQ1M_DELTA * hsum_float_8(accum2); #else - - int sum1[2], sum2[2], delta[4]; - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint16_t * sc = (const uint16_t *)x[i].scales; - - scale.u16 = (sc[0] >> 12) | ((sc[1] >> 8) & 0x00f0) | ((sc[2] >> 4) & 0x0f00) | (sc[3] & 0xf000); - - int sumi1 = 0, sumi2 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - delta[0] = qh[0] & 0x08 ? -1 : 1; - delta[1] = qh[0] & 0x80 ? -1 : 1; - delta[2] = qh[1] & 0x08 ? -1 : 1; - delta[3] = qh[1] & 0x80 ? -1 : 1; - sum1[0] = sum1[1] = sum2[0] = sum2[1] = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((uint16_t)qh[l/2] << (8 - 4*(l%2))) & 0x700))); - int lsum1 = 0, lsum2 = 0; - for (int j = 0; j < 8; ++j) { - lsum1 += q8[j] * grid[j]; - lsum2 += q8[j]; - } - q8 += 8; - sum1[l/2] += lsum1; - sum2[l/2] += lsum2*delta[l]; - } - - const int ls1 = 2*((sc[ib/2] >> (6*(ib%2)+0)) & 0x7) + 1; - const int ls2 = 2*((sc[ib/2] >> (6*(ib%2)+3)) & 0x7) + 1; - - sumi1 += sum1[0] * ls1 + sum1[1] * ls2; - sumi2 += sum2[0] * ls1 + sum2[1] * ls2; - qs += 4; - qh += 2; - } - - sumf += GGML_CPU_FP16_TO_FP32(scale.f16) * y[i].d * (sumi1 + IQ1M_DELTA * sumi2); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(scale); + ggml_vec_dot_iq1_m_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -4275,37 +3811,10 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const v *s = hsum_float_8(accum); #else - float sumf = 0; - for (int ibl = 0; ibl < nb; ++ibl) { - const float d4d8 = GGML_CPU_FP16_TO_FP32(x[ibl].d) * y[ibl].d; - uint16_t h = x[ibl].scales_h; - const uint8_t * qs = x[ibl].qs; - const int8_t * q8 = y[ibl].qs; - for (int ib = 0; ib < QK_K/32; ib += 2) { - const uint8_t ls1 = (x[ibl].scales_l[ib/2] & 0xf) | ((h << 4) & 0x30); - const uint8_t ls2 = (x[ibl].scales_l[ib/2] >> 4) | ((h << 2) & 0x30); - h >>= 4; - const float d1 = d4d8*(ls1 - 32); - const float d2 = d4d8*(ls2 - 32); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d1 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - sumi1 = sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d2 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - } - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq4_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff --git a/ggml/src/ggml-cpu/arch/x86/repack.cpp b/ggml/src/ggml-cpu/arch/x86/repack.cpp index c00c1e541c..d95bb6d8aa 100644 --- a/ggml/src/ggml-cpu/arch/x86/repack.cpp +++ b/ggml/src/ggml-cpu/arch/x86/repack.cpp @@ -281,35 +281,9 @@ void ggml_quantize_mat_q8_0_4x8(const float * GGML_RESTRICT x, void * GGML_RESTR } #else - // scalar - const int blck_size_interleave = 8; - float srcv[4][QK8_0]; - float id[4]; - - for (int i = 0; i < nb; i++) { - for (int row_iter = 0; row_iter < 4; row_iter++) { - float amax = 0.0f; // absolute max - - for (int j = 0; j < QK8_0; j++) { - srcv[row_iter][j] = x[row_iter * k + i * QK8_0 + j]; - amax = MAX(amax, fabsf(srcv[row_iter][j])); - } - - const float d = amax / ((1 << 7) - 1); - id[row_iter] = d ? 1.0f / d : 0.0f; - - y[i].d[row_iter] = GGML_CPU_FP32_TO_FP16(d); - } - - for (int j = 0; j < QK8_0 * 4; j++) { - int src_offset = (j / (4 * blck_size_interleave)) * blck_size_interleave; - int src_id = (j % (4 * blck_size_interleave)) / blck_size_interleave; - src_offset += (j % blck_size_interleave); - - float x0 = srcv[src_id][src_offset] * id[src_id]; - y[i].qs[j] = roundf(x0); - } - } + UNUSED(nb); + UNUSED(y); + ggml_quantize_mat_q8_0_4x8_generic(x, vy, k); #endif } @@ -531,84 +505,40 @@ void ggml_quantize_mat_q8_K_4x8(const float * GGML_RESTRICT x, void * GGML_RESTR } #else - - // scalar - const int blck_size_interleave = 8; - float srcv[4][QK_K]; - float iscale[4]; - - for (int i = 0; i < nb; i++) { - for (int row_iter = 0; row_iter < 4; row_iter++) { - float amax = 0.0f; // absolute max - float max = 0; - - for (int j = 0; j < QK_K; j++) { - srcv[row_iter][j] = x[row_iter * k + i * QK_K + j]; - // Update the maximum value of the corresponding super block - if(amax < fabsf(srcv[row_iter][j])) { - amax = fabsf(srcv[row_iter][j]); - max = srcv[row_iter][j]; - } - } - - iscale[row_iter] = amax ? -127.f/max : 0; - - y[i].d[row_iter] = amax ? 1/iscale[row_iter] : 0; - } - - for (int j = 0; j < QK_K / 4; j++) { - y[i].bsums[j] = 0; - } - - // Quants values are interleaved in sequence of eight bytes from corresponding super blocks - // Bsums values are interleaved in sequence of four bsums from each super block taken for interleaving - // i.e first four bsums from the first super block, followed by first four bsums from second super block and so on - for (int j = 0; j < QK_K * 4; j++) { - int src_offset = (j / (4 * blck_size_interleave)) * blck_size_interleave; - int src_id = (j % (4 * blck_size_interleave)) / blck_size_interleave; - src_offset += (j % blck_size_interleave); - int index = (((j & 31) >> 3) << 2) + ((j >> 8) << 4) + ((j >> 6) & 3); - - float x0 = srcv[src_id][src_offset] * iscale[src_id]; - y[i].qs[j] = nearest_int(x0); - y[i].bsums[index] += y[i].qs[j]; - } - } + UNUSED(nb); + UNUSED(y); + ggml_quantize_mat_q8_K_4x8_generic(x, vy, k); #endif } -void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { +// +// GEMV/GEMM templates +// + +#if defined(__AVX2__) || defined(__AVX512F__) + +// GEMV for 8x blocks of 32 4-bit quants with a single scale factor per block +template +static void gemv_q4_b32_8x8_q8_0_lut_avx(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc, __m256i signextendlut) { + static_assert( + std::is_same_v || + std::is_same_v, + "Unsupported block type"); + const int qk = QK8_0; const int nb = n / qk; - const int ncols_interleaved = 8; - const int blocklen = 8; - assert (n % qk == 0); - assert (nc % ncols_interleaved == 0); - - UNUSED(s); UNUSED(bs); - UNUSED(vx); - UNUSED(vy); - UNUSED(nr); - UNUSED(nc); - UNUSED(nb); - UNUSED(ncols_interleaved); - UNUSED(blocklen); -#if defined(__AVX2__) - // Lookup table to convert signed nibbles to signed bytes - __m256i signextendlut = _mm256_castsi128_si256(_mm_set_epi8(-1, -2, -3, -4, -5, -6, -7, -8, 7, 6, 5, 4, 3, 2, 1, 0)); - signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); __m128i changemask = _mm_set_epi8(15, 14, 7, 6, 13, 12, 5, 4, 11, 10, 3, 2, 9, 8, 1, 0); __m256i finalpermutemask = _mm256_set_epi32(7, 5, 3, 1, 6, 4, 2, 0); // Permute mask used for easier vector processing at later stages const __m256i m4b = _mm256_set1_epi8(0x0F); - int64_t b_nb = n / QK4_0; + int64_t b_nb = n / 32; - const block_q4_0x8 * b_ptr_start = (const block_q4_0x8 *)vx; + const block_tx8 * b_ptr_start = (const block_tx8 *)vx; const block_q8_0 * a_ptr_start = (const block_q8_0 *)vy; // Process Q8_0 blocks one by one @@ -617,17 +547,17 @@ void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo // Pointers to LHS blocks of block_q8_0 format const block_q8_0 * a_ptr = a_ptr_start + (y * nb); - // Take group of eight block_q4_0x8 structures at each pass of the loop and perform dot product operation + // Take group of eight blocks at each pass of the loop and perform dot product operation for (int64_t x = 0; x < nc / 8; x++) { // Pointers to RHS blocks - const block_q4_0x8 * b_ptr = b_ptr_start + (x * b_nb); + const block_tx8 * b_ptr = b_ptr_start + (x * b_nb); // Master FP accumulator __m256 acc_row = _mm256_setzero_ps(); for (int64_t b = 0; b < nb; b++) { - // Load 8 blocks of Q4_0 interleaved as 8 bytes (B0 - B7) + // Load 8 blocks of 32 interleaved as 8 bytes (B0 - B7) const __m256i rhs_raw_vec_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs)); const __m256i rhs_raw_vec_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs) + 1); const __m256i rhs_raw_vec_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs) + 2); @@ -644,8 +574,13 @@ void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo const __m256i rhs_vec_0123_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_1, 4), m4b)); // B0(24-31) B1(24-31) B2(24-31) B3(24-31) const __m256i rhs_vec_4567_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_1, 4), m4b)); // B4(24-31) B5(24-31) B6(24-31) B7(24-31) - // Load the scale values for the 8 blocks interleaved in block_q4_0x8 - const __m256 col_scale_f32 = GGML_F32Cx8_REARRANGE_LOAD(b_ptr[b].d, changemask); + // Load the scale values for the 8 blocks interleaved in block_tx8 + __m256 col_scale_f32; + if constexpr ( + std::is_same_v || + std::is_same_v) { + col_scale_f32 = GGML_F32Cx8_REARRANGE_LOAD(b_ptr[b].d, changemask); + } // Load and convert to FP32 scale from block_q8_0 const __m256 row_scale_f32 = _mm256_set1_ps(GGML_CPU_FP16_TO_FP32(a_ptr[b].d)); @@ -686,34 +621,772 @@ void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo _mm256_storeu_ps(s + (y * nr + x * 8), acc_row); } } - return; +} -#endif - { - float sumf[8]; - int sumi; +// GEMM for 8x blocks of 32 4-bit quants with a single scale factor per block +template +static void gemm_q4_b32_8x8_q8_0_lut_avx(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc, __m256i signextendlut) { + static_assert( + std::is_same_v || + std::is_same_v, + "Unsupported block type"); - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); + const int qk = QK8_0; + const int nb = n / qk; - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } + const block_tx8 * b_ptr_start = (const block_tx8 *)vx; + const block_q8_0x4 * a_ptr_start = (const block_q8_0x4 *)vy; + + int64_t b_nb = n / 32; + int64_t y = 0; + // Mask to mask out nibbles from packed bytes + const __m256i m4b = _mm256_set1_epi8(0x0F); + const __m128i loadMask = _mm_blend_epi32(_mm_setzero_si128(), _mm_set1_epi32(0xFFFFFFFF), 3); + // Permute mask used for easier vector processing at later stages + __m256i requiredOrder = _mm256_set_epi32(3, 2, 1, 0, 7, 6, 5, 4); + int64_t xstart = 0; + int anr = nr - nr%16; // Used to align nr with boundary of 16 +#ifdef __AVX512F__ + int anc = nc - nc%16; // Used to align nc with boundary of 16 + // Mask to mask out nibbles from packed bytes expanded to 512 bit length + const __m512i m4bexpanded = _mm512_set1_epi8(0x0F); + // Lookup table to convert signed nibbles to signed bytes expanded to 512 bit length + __m512i signextendlutexpanded = _mm512_inserti32x8(_mm512_castsi256_si512(signextendlut), signextendlut, 1); + + // Take group of four block_q8_0x4 structures at each pass of the loop and perform dot product operation + for (; y < anr / 4; y += 4) { + + const block_q8_0x4 * a_ptrs[4]; + + a_ptrs[0] = a_ptr_start + (y * nb); + for (int i = 0; i < 3; ++i) { + a_ptrs[i + 1] = a_ptrs[i] + nb; + } + + // Take group of two block_tx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = 0; x < anc / 8; x += 2) { + + const block_tx8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); + const block_tx8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); + + // Master FP accumulators + __m512 acc_rows[16]; + for (int i = 0; i < 16; i++) { + acc_rows[i] = _mm512_setzero_ps(); + } + + for (int64_t b = 0; b < nb; b++) { + // Load the sixteen blocks of quantized values interleaved with each other in chunks of eight - B0,B1 ....BE,BF + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 32)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 64)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 96)); + + const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs)); + const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 32)); + const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 64)); + const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 96)); + + // Save the values in the following vectors in the formats B0B1B4B5B8B9BCBD, B2B3B6B7BABBBEBF for further processing and storing of values + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); + const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); + + const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); + const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); + const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); + const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); + + // 4-bit -> 8-bit - Sign is maintained + const __m512i rhs_mat_014589CD_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_0, m4bexpanded)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) B8(0-7) B9(0-7) BC(0-7) BD(0-7) + const __m512i rhs_mat_2367ABEF_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_0, m4bexpanded)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) BA(0-7) BB(0-7) BE(0-7) BF(0-7) + + const __m512i rhs_mat_014589CD_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_1, m4bexpanded)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) B8(8-15) B9(8-15) BC(8-15) BD(8-15) + const __m512i rhs_mat_2367ABEF_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_1, m4bexpanded)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) BA(8-15) BB(8-15) BE(8-15) BF(8-15) + + const __m512i rhs_mat_014589CD_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m4bexpanded)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) B8(16-23) B9(16-23) BC(16-23) BD(16-23) + const __m512i rhs_mat_2367ABEF_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m4bexpanded)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) BA(16-23) BB(16-23) BE(16-23) BF(16-23) + + const __m512i rhs_mat_014589CD_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m4bexpanded)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) B8(24-31) B9(24-31) BC(24-31) BD(24-31) + const __m512i rhs_mat_2367ABEF_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m4bexpanded)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) BA(24-31) BB(24-31) BE(24-31) BF(24-31) + + // Shuffle pattern one - right side input + const __m512i rhs_mat_014589CD_0_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) B8(0-3) B9(0-3) B8(0-3) B9(0-3) BC(0-3) BD(0-3) BC(0-3) BD(0-3) + const __m512i rhs_mat_2367ABEF_0_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) BA(0-3) BB(0-3) BA(0-3) BB(0-3) BE(0-3) BF(0-3) BE(0-3) BF(0-3) + + const __m512i rhs_mat_014589CD_1_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) B8(8-11) B9(8-11) B8(8-11) B9(8-11) BC(8-11) BD(8-11) BC(8-11) BD(8-11) + const __m512i rhs_mat_2367ABEF_1_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) BA(8-11) BB(8-11) BA(8-11) BB(8-11) BE(8-11) BF(8-11) BE(8-11) BF(8-11) + + const __m512i rhs_mat_014589CD_2_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) B8(16-19) B9(16-19) B8(16-19) B9(16-19) BC(16-19) BD(16-19) BC(16-19) BD(16-19) + const __m512i rhs_mat_2367ABEF_2_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) BA(16-19) BB(16-19) BA(16-19) BB(16-19) BE(16-19) BF(16-19) BE(16-19) BF(16-19) + + const __m512i rhs_mat_014589CD_3_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) B8(24-27) B9(24-27) B8(24-27) B9(24-27) BC(24-27) BD(24-27) BC(24-27) BD(24-27) + const __m512i rhs_mat_2367ABEF_3_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) BA(24-27) BB(24-27) BA(24-27) BB(24-27) BE(24-27) BF(24-27) BE(24-27) BF(24-27) + + // Shuffle pattern two - right side input + + const __m512i rhs_mat_014589CD_0_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) B8(4-7) B9(4-7) B8(4-7) B9(4-7) BC(4-7) BD(4-7) BC(4-7) BD(4-7) + const __m512i rhs_mat_2367ABEF_0_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) BA(4-7) BB(4-7) BA(4-7) BB(4-7) BE(4-7) BF(4-7) BE(4-7) BF(4-7) + + const __m512i rhs_mat_014589CD_1_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) B8(12-15) B9(12-15) B8(12-15) B9(12-15) BC(12-15) BD(12-15) BC(12-15) BD(12-15) + const __m512i rhs_mat_2367ABEF_1_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) BA(12-15) BB(12-15) BA(12-15) BB(12-15) BE(12-15) BF(12-15) BE(12-15) BF(12-15) + + const __m512i rhs_mat_014589CD_2_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) B8(20-23) B9(20-23) B8(20-23) B9(20-23) BC(20-23) BD(20-23) BC(20-23) BD(20-23) + const __m512i rhs_mat_2367ABEF_2_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) BA(20-23) BB(20-23) BA(20-23) BB(20-23) BE(20-23) BF(20-23) BE(20-23) BF(20-23) + + const __m512i rhs_mat_014589CD_3_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) B8(28-31) B9(28-31) B8(28-31) B9(28-31) BC(28-31) BD(28-31) BC(28-31) BD(28-31) + const __m512i rhs_mat_2367ABEF_3_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) BA(28-31) BB(28-31) BA(28-31) BB(28-31) BE(28-31) BF(28-31) BE(28-31) BF(28-31) + + // Scale values - Load the weight scale values of two block_tx8 + __m512 col_scale_f32; + if constexpr ( + std::is_same_v || + std::is_same_v) { + col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); + } + + // Process LHS in pairs of rows + for (int rp = 0; rp < 4; rp++) { + + // Load the four blocks of quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated and stored into a 256 bit vector before again repeating into 512 bit vector + __m256i lhs_mat_ymm_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs))); + __m256i lhs_mat_ymm_01_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 0); + __m256i lhs_mat_ymm_23_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 17); + __m256i lhs_mat_ymm_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 32))); + __m256i lhs_mat_ymm_01_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 0); + __m256i lhs_mat_ymm_23_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 17); + __m256i lhs_mat_ymm_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 64))); + __m256i lhs_mat_ymm_01_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 0); + __m256i lhs_mat_ymm_23_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 17); + __m256i lhs_mat_ymm_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 96))); + __m256i lhs_mat_ymm_01_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 0); + __m256i lhs_mat_ymm_23_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 17); + + __m512i lhs_mat_01_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_0), lhs_mat_ymm_01_0, 1); + __m512i lhs_mat_23_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_0), lhs_mat_ymm_23_0, 1); + __m512i lhs_mat_01_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_1), lhs_mat_ymm_01_1, 1); + __m512i lhs_mat_23_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_1), lhs_mat_ymm_23_1, 1); + __m512i lhs_mat_01_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_2), lhs_mat_ymm_01_2, 1); + __m512i lhs_mat_23_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_2), lhs_mat_ymm_23_2, 1); + __m512i lhs_mat_01_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_3), lhs_mat_ymm_01_3, 1); + __m512i lhs_mat_23_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_3), lhs_mat_ymm_23_3, 1); + + // Shuffle pattern one - left side input + + const __m512i lhs_mat_01_0_sp1 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) + const __m512i lhs_mat_23_0_sp1 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) + + const __m512i lhs_mat_01_1_sp1 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) + const __m512i lhs_mat_23_1_sp1 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) + + const __m512i lhs_mat_01_2_sp1 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) + const __m512i lhs_mat_23_2_sp1 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) + + const __m512i lhs_mat_01_3_sp1 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) + const __m512i lhs_mat_23_3_sp1 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) + + // Shuffle pattern two - left side input + + const __m512i lhs_mat_01_0_sp2 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) + const __m512i lhs_mat_23_0_sp2 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) + + const __m512i lhs_mat_01_1_sp2 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) + const __m512i lhs_mat_23_1_sp2 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) + + const __m512i lhs_mat_01_2_sp2 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) + const __m512i lhs_mat_23_2_sp2 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) + + const __m512i lhs_mat_01_3_sp2 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) + const __m512i lhs_mat_23_3_sp2 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + // Resembles MMLAs into 2x2 matrices in ARM Version + const __m512i zero = _mm512_setzero_epi32(); + __m512i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_01_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_01_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_01_0_sp1, rhs_mat_014589CD_0_sp1); + __m512i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367ABEF_0_sp1); + __m512i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_23_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_23_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_23_0_sp1, rhs_mat_014589CD_0_sp1); + __m512i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367ABEF_0_sp1); + __m512i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_01_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_01_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_01_0_sp2, rhs_mat_014589CD_0_sp2); + __m512i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367ABEF_0_sp2); + __m512i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_23_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_23_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_23_0_sp2, rhs_mat_014589CD_0_sp2); + __m512i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367ABEF_0_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + __m512i iacc_mat_00 = _mm512_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); + __m512i iacc_mat_01 = _mm512_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); + __m512i iacc_mat_10 = _mm512_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); + __m512i iacc_mat_11 = _mm512_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); + + + // Straighten out to make 4 row vectors + __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); + __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); + __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); + __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); + + // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes + const __m128i row_scale_f16 = _mm_shuffle_epi32(_mm_maskload_epi32((int const*)(a_ptrs[rp][b].d), loadMask), 68); + const __m512 row_scale_f32 = GGML_F32Cx16_REPEAT_LOAD(row_scale_f16); + + // Multiply with appropiate scales and accumulate + acc_rows[rp * 4] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); + acc_rows[rp * 4 + 1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); + acc_rows[rp * 4 + 2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); + acc_rows[rp * 4 + 3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); } } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; + + // Store the accumulated values + for (int i = 0; i < 16; i++) { + _mm512_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); + } } } + + // Take a block_q8_0x4 structures at each pass of the loop and perform dot product operation + for (; y < nr / 4; y ++) { + const block_q8_0x4 * a_ptr = a_ptr_start + (y * nb); + + // Take group of two block_tx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = 0; x < anc / 8; x += 2) { + + const block_tx8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); + const block_tx8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); + + // Master FP accumulators + __m512 acc_rows[4]; + for (int i = 0; i < 4; i++) { + acc_rows[i] = _mm512_setzero_ps(); + } + + for (int64_t b = 0; b < nb; b++) { + // Load the sixteen blocks of quantized values interleaved with each other in chunks of eight - B0,B1 ....BE,BF + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 32)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 64)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 96)); + + const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs)); + const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 32)); + const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 64)); + const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 96)); + + // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of valuess + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); + const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); + + const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); + const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); + const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); + const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); + + // 4-bit -> 8-bit - Sign is maintained + const __m512i rhs_mat_014589CD_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_0, m4bexpanded)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) B8(0-7) B9(0-7) BC(0-7) BD(0-7) + const __m512i rhs_mat_2367ABEF_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_0, m4bexpanded)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) BA(0-7) BB(0-7) BE(0-7) BF(0-7) + + const __m512i rhs_mat_014589CD_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_1, m4bexpanded)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) B8(8-15) B9(8-15) BC(8-15) BD(8-15) + const __m512i rhs_mat_2367ABEF_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_1, m4bexpanded)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) BA(8-15) BB(8-15) BE(8-15) BF(8-15) + + const __m512i rhs_mat_014589CD_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m4bexpanded)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) B8(16-23) B9(16-23) BC(16-23) BD(16-23) + const __m512i rhs_mat_2367ABEF_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m4bexpanded)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) BA(16-23) BB(16-23) BE(16-23) BF(16-23) + + const __m512i rhs_mat_014589CD_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m4bexpanded)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) B8(24-31) B9(24-31) BC(24-31) BD(24-31) + const __m512i rhs_mat_2367ABEF_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m4bexpanded)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) BA(24-31) BB(24-31) BE(24-31) BF(24-31) + + // Shuffle pattern one - right side input + const __m512i rhs_mat_014589CD_0_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) B8(0-3) B9(0-3) B8(0-3) B9(0-3) BC(0-3) BD(0-3) BC(0-3) BD(0-3) + const __m512i rhs_mat_2367ABEF_0_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) BA(0-3) BB(0-3) BA(0-3) BB(0-3) BE(0-3) BF(0-3) BE(0-3) BF(0-3) + + const __m512i rhs_mat_014589CD_1_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) B8(8-11) B9(8-11) B8(8-11) B9(8-11) BC(8-11) BD(8-11) BC(8-11) BD(8-11) + const __m512i rhs_mat_2367ABEF_1_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) BA(8-11) BB(8-11) BA(8-11) BB(8-11) BE(8-11) BF(8-11) BE(8-11) BF(8-11) + + const __m512i rhs_mat_014589CD_2_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) B8(16-19) B9(16-19) B8(16-19) B9(16-19) BC(16-19) BD(16-19) BC(16-19) BD(16-19) + const __m512i rhs_mat_2367ABEF_2_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) BA(16-19) BB(16-19) BA(16-19) BB(16-19) BE(16-19) BF(16-19) BE(16-19) BF(16-19) + + const __m512i rhs_mat_014589CD_3_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) B8(24-27) B9(24-27) B8(24-27) B9(24-27) BC(24-27) BD(24-27) BC(24-27) BD(24-27) + const __m512i rhs_mat_2367ABEF_3_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) BA(24-27) BB(24-27) BA(24-27) BB(24-27) BE(24-27) BF(24-27) BE(24-27) BF(24-27) + + // Shuffle pattern two - right side input + + const __m512i rhs_mat_014589CD_0_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) B8(4-7) B9(4-7) B8(4-7) B9(4-7) BC(4-7) BD(4-7) BC(4-7) BD(4-7) + const __m512i rhs_mat_2367ABEF_0_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) BA(4-7) BB(4-7) BA(4-7) BB(4-7) BE(4-7) BF(4-7) BE(4-7) BF(4-7) + + const __m512i rhs_mat_014589CD_1_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) B8(12-15) B9(12-15) B8(12-15) B9(12-15) BC(12-15) BD(12-15) BC(12-15) BD(12-15) + const __m512i rhs_mat_2367ABEF_1_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) BA(12-15) BB(12-15) BA(12-15) BB(12-15) BE(12-15) BF(12-15) BE(12-15) BF(12-15) + + const __m512i rhs_mat_014589CD_2_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) B8(20-23) B9(20-23) B8(20-23) B9(20-23) BC(20-23) BD(20-23) BC(20-23) BD(20-23) + const __m512i rhs_mat_2367ABEF_2_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) BA(20-23) BB(20-23) BA(20-23) BB(20-23) BE(20-23) BF(20-23) BE(20-23) BF(20-23) + + const __m512i rhs_mat_014589CD_3_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) B8(28-31) B9(28-31) B8(28-31) B9(28-31) BC(28-31) BD(28-31) BC(28-31) BD(28-31) + const __m512i rhs_mat_2367ABEF_3_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) BA(28-31) BB(28-31) BA(28-31) BB(28-31) BE(28-31) BF(28-31) BE(28-31) BF(28-31) + + + // Scale values - Load the weight scale values of two block_tx8 + __m512 col_scale_f32; + if constexpr ( + std::is_same_v || + std::is_same_v) { + col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); + } + + // Load the four blocks of quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated and stored into a 256 bit vector before again repeating into 512 bit vector + __m256i lhs_mat_ymm_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs))); + __m256i lhs_mat_ymm_01_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 0); + __m256i lhs_mat_ymm_23_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 17); + __m256i lhs_mat_ymm_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 32))); + __m256i lhs_mat_ymm_01_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 0); + __m256i lhs_mat_ymm_23_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 17); + __m256i lhs_mat_ymm_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 64))); + __m256i lhs_mat_ymm_01_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 0); + __m256i lhs_mat_ymm_23_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 17); + __m256i lhs_mat_ymm_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 96))); + __m256i lhs_mat_ymm_01_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 0); + __m256i lhs_mat_ymm_23_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 17); + + __m512i lhs_mat_01_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_0), lhs_mat_ymm_01_0, 1); + __m512i lhs_mat_23_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_0), lhs_mat_ymm_23_0, 1); + __m512i lhs_mat_01_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_1), lhs_mat_ymm_01_1, 1); + __m512i lhs_mat_23_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_1), lhs_mat_ymm_23_1, 1); + __m512i lhs_mat_01_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_2), lhs_mat_ymm_01_2, 1); + __m512i lhs_mat_23_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_2), lhs_mat_ymm_23_2, 1); + __m512i lhs_mat_01_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_3), lhs_mat_ymm_01_3, 1); + __m512i lhs_mat_23_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_3), lhs_mat_ymm_23_3, 1); + + // Shuffle pattern one - left side input + + const __m512i lhs_mat_01_0_sp1 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) + const __m512i lhs_mat_23_0_sp1 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) + + const __m512i lhs_mat_01_1_sp1 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) + const __m512i lhs_mat_23_1_sp1 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) + + const __m512i lhs_mat_01_2_sp1 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) + const __m512i lhs_mat_23_2_sp1 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) + + const __m512i lhs_mat_01_3_sp1 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) + const __m512i lhs_mat_23_3_sp1 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) + + // Shuffle pattern two - left side input + + const __m512i lhs_mat_01_0_sp2 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) + const __m512i lhs_mat_23_0_sp2 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) + + const __m512i lhs_mat_01_1_sp2 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) + const __m512i lhs_mat_23_1_sp2 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) + + const __m512i lhs_mat_01_2_sp2 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) + const __m512i lhs_mat_23_2_sp2 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) + + const __m512i lhs_mat_01_3_sp2 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) + const __m512i lhs_mat_23_3_sp2 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + // Resembles MMLAs into 2x2 matrices in ARM Version + const __m512i zero = _mm512_setzero_epi32(); + __m512i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_01_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_01_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_01_0_sp1, rhs_mat_014589CD_0_sp1); + __m512i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367ABEF_0_sp1); + __m512i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_23_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_23_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_23_0_sp1, rhs_mat_014589CD_0_sp1); + __m512i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367ABEF_0_sp1); + __m512i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_01_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_01_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_01_0_sp2, rhs_mat_014589CD_0_sp2); + __m512i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367ABEF_0_sp2); + __m512i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_23_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_23_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_23_0_sp2, rhs_mat_014589CD_0_sp2); + __m512i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367ABEF_0_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + __m512i iacc_mat_00 = _mm512_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); + __m512i iacc_mat_01 = _mm512_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); + __m512i iacc_mat_10 = _mm512_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); + __m512i iacc_mat_11 = _mm512_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); + + + // Straighten out to make 4 row vectors + __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); + __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); + __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); + __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); + + // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes + const __m128i row_scale_f16 = _mm_shuffle_epi32(_mm_maskload_epi32((int const*)(a_ptr[b].d), loadMask), 68); + const __m512 row_scale_f32 = GGML_F32Cx16_REPEAT_LOAD(row_scale_f16); + + // Multiply with appropiate scales and accumulate + acc_rows[0] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); + acc_rows[1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); + acc_rows[2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); + acc_rows[3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); + } + + // Store the accumulated values + for (int i = 0; i < 4; i++) { + _mm512_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); + } + } + } + if (anc != nc) { + xstart = anc/8; + y = 0; + } +#endif // __AVX512F__ + + // Take group of four block_q8_0x4 structures at each pass of the loop and perform dot product operation + + for (; y < anr / 4; y += 4) { + const block_q8_0x4 * a_ptrs[4]; + + a_ptrs[0] = a_ptr_start + (y * nb); + for (int i = 0; i < 3; ++i) { + a_ptrs[i + 1] = a_ptrs[i] + nb; + } + + // Take group of eight block_tx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = xstart; x < nc / 8; x++) { + + const block_tx8 * b_ptr = b_ptr_start + (x * b_nb); + + // Master FP accumulators + __m256 acc_rows[16]; + for (int i = 0; i < 16; i++) { + acc_rows[i] = _mm256_setzero_ps(); + } + + for (int64_t b = 0; b < nb; b++) { + // Load the eight blocks of quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96)); + + // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of values + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + // 4-bit -> 8-bit - Sign is maintained + const __m256i rhs_mat_0145_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_0, m4b)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) + const __m256i rhs_mat_2367_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_0, m4b)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) + + const __m256i rhs_mat_0145_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_1, m4b)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) + const __m256i rhs_mat_2367_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_1, m4b)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) + + const __m256i rhs_mat_0145_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m4b)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) + const __m256i rhs_mat_2367_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m4b)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) + + const __m256i rhs_mat_0145_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m4b)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) + const __m256i rhs_mat_2367_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m4b)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) + + // Shuffle pattern one - right side input + const __m256i rhs_mat_0145_0_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_0, 136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) + const __m256i rhs_mat_2367_0_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_0, 136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) + + const __m256i rhs_mat_0145_1_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_1, 136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) + const __m256i rhs_mat_2367_1_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_1, 136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) + + const __m256i rhs_mat_0145_2_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_2, 136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) + const __m256i rhs_mat_2367_2_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_2, 136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) + + const __m256i rhs_mat_0145_3_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_3, 136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) + const __m256i rhs_mat_2367_3_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_3, 136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) + + // Shuffle pattern two - right side input + + const __m256i rhs_mat_0145_0_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_0, 221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) + const __m256i rhs_mat_2367_0_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_0, 221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) + + const __m256i rhs_mat_0145_1_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_1, 221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) + const __m256i rhs_mat_2367_1_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_1, 221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) + + const __m256i rhs_mat_0145_2_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_2, 221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) + const __m256i rhs_mat_2367_2_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_2, 221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) + + const __m256i rhs_mat_0145_3_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_3, 221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) + const __m256i rhs_mat_2367_3_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_3, 221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) + + // Scale values - Load the wight scale values of block_tx8 + __m256 col_scale_f32; + if constexpr ( + std::is_same_v || + std::is_same_v) { + col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); + } + + // Process LHS in groups of four + for (int rp = 0; rp < 4; rp++) { + // Load the four blocks of quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated into a 256 bit vector + __m256i lhs_mat_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs))); + __m256i lhs_mat_01_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 0); + __m256i lhs_mat_23_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 17); + __m256i lhs_mat_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 32))); + __m256i lhs_mat_01_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 0); + __m256i lhs_mat_23_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 17); + __m256i lhs_mat_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 64))); + __m256i lhs_mat_01_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 0); + __m256i lhs_mat_23_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 17); + __m256i lhs_mat_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 96))); + __m256i lhs_mat_01_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 0); + __m256i lhs_mat_23_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 17); + + // Shuffle pattern one - left side input + const __m256i lhs_mat_01_0_sp1 = _mm256_shuffle_epi32(lhs_mat_01_0, 160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) + const __m256i lhs_mat_23_0_sp1 = _mm256_shuffle_epi32(lhs_mat_23_0, 160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) + + const __m256i lhs_mat_01_1_sp1 = _mm256_shuffle_epi32(lhs_mat_01_1, 160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) + const __m256i lhs_mat_23_1_sp1 = _mm256_shuffle_epi32(lhs_mat_23_1, 160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) + + const __m256i lhs_mat_01_2_sp1 = _mm256_shuffle_epi32(lhs_mat_01_2, 160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) + const __m256i lhs_mat_23_2_sp1 = _mm256_shuffle_epi32(lhs_mat_23_2, 160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) + + const __m256i lhs_mat_01_3_sp1 = _mm256_shuffle_epi32(lhs_mat_01_3, 160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) + const __m256i lhs_mat_23_3_sp1 = _mm256_shuffle_epi32(lhs_mat_23_3, 160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) + + // Shuffle pattern two - left side input + const __m256i lhs_mat_01_0_sp2 = _mm256_shuffle_epi32(lhs_mat_01_0, 245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) + const __m256i lhs_mat_23_0_sp2 = _mm256_shuffle_epi32(lhs_mat_23_0, 245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) + + const __m256i lhs_mat_01_1_sp2 = _mm256_shuffle_epi32(lhs_mat_01_1, 245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) + const __m256i lhs_mat_23_1_sp2 = _mm256_shuffle_epi32(lhs_mat_23_1, 245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) + + const __m256i lhs_mat_01_2_sp2 = _mm256_shuffle_epi32(lhs_mat_01_2, 245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) + const __m256i lhs_mat_23_2_sp2 = _mm256_shuffle_epi32(lhs_mat_23_2, 245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) + + const __m256i lhs_mat_01_3_sp2 = _mm256_shuffle_epi32(lhs_mat_01_3, 245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) + const __m256i lhs_mat_23_3_sp2 = _mm256_shuffle_epi32(lhs_mat_23_3, 245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + // Resembles MMLAs into 2x2 matrices in ARM Version + const __m256i zero = _mm256_setzero_si256(); + __m256i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_01_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_01_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_01_0_sp1, rhs_mat_0145_0_sp1); + __m256i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367_0_sp1); + __m256i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_23_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_23_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_23_0_sp1, rhs_mat_0145_0_sp1); + __m256i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367_0_sp1); + __m256i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_01_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_01_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_01_0_sp2, rhs_mat_0145_0_sp2); + __m256i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367_0_sp2); + __m256i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_23_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_23_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_23_0_sp2, rhs_mat_0145_0_sp2); + __m256i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367_0_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + __m256i iacc_mat_00 = _mm256_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); + __m256i iacc_mat_01 = _mm256_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); + __m256i iacc_mat_10 = _mm256_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); + __m256i iacc_mat_11 = _mm256_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); + + // Straighten out to make 4 row vectors + __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); + __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); + __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); + __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); + + // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes + const __m256 row_scale_f32 = GGML_F32Cx8_REPEAT_LOAD(a_ptrs[rp][b].d, loadMask); + + // Multiply with appropiate scales and accumulate + acc_rows[rp * 4] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); + acc_rows[rp * 4 + 1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); + acc_rows[rp * 4 + 2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); + acc_rows[rp * 4 + 3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); + } + } + + // Store the accumulated values + for (int i = 0; i < 16; i++) { + _mm256_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); + } + } + } + + // Take a block_q8_0x4 structures at each pass of the loop and perform dot product operation + for (; y < nr / 4; y ++) { + const block_q8_0x4 * a_ptr = a_ptr_start + (y * nb); + + // Load the eight blocks of quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 + for (int64_t x = xstart; x < nc / 8; x++) { + const block_tx8 * b_ptr = b_ptr_start + (x * b_nb); + + // Master FP accumulators + __m256 acc_rows[4]; + for (int i = 0; i < 4; i++) { + acc_rows[i] = _mm256_setzero_ps(); + } + + for (int64_t b = 0; b < nb; b++) { + // Load the eight block_q8_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96)); + + // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of valuess + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + // 4-bit -> 8-bit - Sign is maintained + const __m256i rhs_mat_0145_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_0, m4b)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) + const __m256i rhs_mat_2367_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_0, m4b)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) + + const __m256i rhs_mat_0145_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_1, m4b)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) + const __m256i rhs_mat_2367_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_1, m4b)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) + + const __m256i rhs_mat_0145_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m4b)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) + const __m256i rhs_mat_2367_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m4b)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) + + const __m256i rhs_mat_0145_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m4b)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) + const __m256i rhs_mat_2367_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m4b)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) + + // Shuffle pattern one - right side input + const __m256i rhs_mat_0145_0_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_0, 136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) + const __m256i rhs_mat_2367_0_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_0, 136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) + + const __m256i rhs_mat_0145_1_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_1, 136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) + const __m256i rhs_mat_2367_1_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_1, 136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) + + const __m256i rhs_mat_0145_2_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_2, 136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) + const __m256i rhs_mat_2367_2_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_2, 136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) + + const __m256i rhs_mat_0145_3_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_3, 136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) + const __m256i rhs_mat_2367_3_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_3, 136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) + + // Shuffle pattern two - right side input + + const __m256i rhs_mat_0145_0_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_0, 221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) + const __m256i rhs_mat_2367_0_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_0, 221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) + + const __m256i rhs_mat_0145_1_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_1, 221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) + const __m256i rhs_mat_2367_1_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_1, 221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) + + const __m256i rhs_mat_0145_2_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_2, 221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) + const __m256i rhs_mat_2367_2_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_2, 221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) + + const __m256i rhs_mat_0145_3_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_3, 221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) + const __m256i rhs_mat_2367_3_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_3, 221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) + + // Scale values - Load the wight scale values of block_tx8 + __m256 col_scale_f32; + if constexpr ( + std::is_same_v || + std::is_same_v) { + col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); + } + + // Load the four blocks of quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated into a 256 bit vector + __m256i lhs_mat_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs))); + __m256i lhs_mat_01_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 0); + __m256i lhs_mat_23_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 17); + __m256i lhs_mat_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 32))); + __m256i lhs_mat_01_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 0); + __m256i lhs_mat_23_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 17); + __m256i lhs_mat_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 64))); + __m256i lhs_mat_01_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 0); + __m256i lhs_mat_23_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 17); + __m256i lhs_mat_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 96))); + __m256i lhs_mat_01_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 0); + __m256i lhs_mat_23_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 17); + + // Shuffle pattern one - left side input + + const __m256i lhs_mat_01_0_sp1 = _mm256_shuffle_epi32(lhs_mat_01_0, 160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) + const __m256i lhs_mat_23_0_sp1 = _mm256_shuffle_epi32(lhs_mat_23_0, 160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) + + const __m256i lhs_mat_01_1_sp1 = _mm256_shuffle_epi32(lhs_mat_01_1, 160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) + const __m256i lhs_mat_23_1_sp1 = _mm256_shuffle_epi32(lhs_mat_23_1, 160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) + + const __m256i lhs_mat_01_2_sp1 = _mm256_shuffle_epi32(lhs_mat_01_2, 160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) + const __m256i lhs_mat_23_2_sp1 = _mm256_shuffle_epi32(lhs_mat_23_2, 160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) + + const __m256i lhs_mat_01_3_sp1 = _mm256_shuffle_epi32(lhs_mat_01_3, 160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) + const __m256i lhs_mat_23_3_sp1 = _mm256_shuffle_epi32(lhs_mat_23_3, 160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) + + // Shuffle pattern two - left side input + + const __m256i lhs_mat_01_0_sp2 = _mm256_shuffle_epi32(lhs_mat_01_0, 245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) + const __m256i lhs_mat_23_0_sp2 = _mm256_shuffle_epi32(lhs_mat_23_0, 245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) + + const __m256i lhs_mat_01_1_sp2 = _mm256_shuffle_epi32(lhs_mat_01_1, 245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) + const __m256i lhs_mat_23_1_sp2 = _mm256_shuffle_epi32(lhs_mat_23_1, 245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) + + const __m256i lhs_mat_01_2_sp2 = _mm256_shuffle_epi32(lhs_mat_01_2, 245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) + const __m256i lhs_mat_23_2_sp2 = _mm256_shuffle_epi32(lhs_mat_23_2, 245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) + + const __m256i lhs_mat_01_3_sp2 = _mm256_shuffle_epi32(lhs_mat_01_3, 245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) + const __m256i lhs_mat_23_3_sp2 = _mm256_shuffle_epi32(lhs_mat_23_3, 245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + // Resembles MMLAs into 2x2 matrices in ARM Version + const __m256i zero = _mm256_setzero_si256(); + __m256i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_01_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_01_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_01_0_sp1, rhs_mat_0145_0_sp1); + __m256i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367_0_sp1); + __m256i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_23_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_23_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_23_0_sp1, rhs_mat_0145_0_sp1); + __m256i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367_0_sp1); + __m256i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_01_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_01_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_01_0_sp2, rhs_mat_0145_0_sp2); + __m256i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367_0_sp2); + __m256i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_23_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_23_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_23_0_sp2, rhs_mat_0145_0_sp2); + __m256i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367_0_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + __m256i iacc_mat_00 = _mm256_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); + __m256i iacc_mat_01 = _mm256_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); + __m256i iacc_mat_10 = _mm256_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); + __m256i iacc_mat_11 = _mm256_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); + + + // Straighten out to make 4 row vectors + __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); + __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); + __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); + __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); + + // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes + const __m256 row_scale_f32 = GGML_F32Cx8_REPEAT_LOAD(a_ptr[b].d, loadMask); + + // Multiply with appropiate scales and accumulate + acc_rows[0] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); + acc_rows[1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); + acc_rows[2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); + acc_rows[3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); + } + + // Store the accumulated values + for (int i = 0; i < 4; i++) { + _mm256_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); + } + } + } +} + +#endif // defined(__AVX2__) || defined(__AVX512F__) + +void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { +#if defined(__AVX2__) || defined(__AVX512F__) + { + // Lookup table to convert signed nibbles to signed bytes + __m256i signextendlut = _mm256_castsi128_si256(_mm_set_epi8(-1, -2, -3, -4, -5, -6, -7, -8, 7, 6, 5, 4, 3, 2, 1, 0)); + signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); + + gemv_q4_b32_8x8_q8_0_lut_avx(n, s, bs, vx, vy, nr, nc, signextendlut); + + return; + } +#endif + + ggml_gemv_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemv_q4_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -932,72 +1605,33 @@ void ggml_gemv_q4_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo } #else - - float sumf[8]; - float sum_minf[8]; - uint32_t utmp[32]; - int sumi1; - int sumi2; - int sumi; - - const block_q8_K * a_ptr = (const block_q8_K *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_Kx8 * b_ptr = (const block_q4_Kx8 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) { - sumf[j] = 0.0; - sum_minf[j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int sb = 0; sb < 8; sb++) { - memcpy(utmp + sb * 4, b_ptr[l].scales + sb * 12, 12); - utmp[sb * 4 + 3] = ((utmp[sb * 4 + 2] >> 4) & kmask2) | (((utmp[sb * 4 + 1] >> 6) & kmask3) << 4); - const uint32_t uaux_0 = utmp[sb * 4 + 1] & kmask1; - utmp[sb * 4 + 1] = (utmp[sb * 4 + 2] & kmask2) | (((utmp[sb * 4 + 0] >> 6) & kmask3) << 4); - utmp[sb * 4 + 2] = uaux_0; - utmp[sb * 4 + 0] &= kmask1; - } - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - uint8_t *scales_0 = (uint8_t*) utmp + (k / 4) * 32; - uint8_t *scales_1 = (uint8_t*) utmp + (k / 4) * 32 + 16; - for (int j = 0; j < ncols_interleaved; j++) { - sumi1 = 0; - sumi2 = 0; - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4); - sumi1 = (v0 * a_ptr[l].qs[(k >> 2) * 64 + (k % 4) * blocklen + i]); - sumi2 = (v1 * a_ptr[l].qs[(k >> 2) * 64 + (k % 4) * blocklen + i + 32]); - sumi1 = sumi1 * scales_0[j]; - sumi2 = sumi2 * scales_1[j]; - sumi += sumi1 + sumi2; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * a_ptr[l].d; - } - } - for (int sb = 0; sb < 8; sb++) { - uint8_t *mins = (uint8_t*) utmp + 8 + sb * 16; - for (int j = 0; j < ncols_interleaved; j++) { - sum_minf[j] += mins[j] * (a_ptr[l].bsums[sb * 2] + a_ptr[l].bsums[sb * 2 + 1]) * GGML_CPU_FP16_TO_FP32(b_ptr[l].dmin[j]) * a_ptr[l].d; - } - } - } - for (int j = 0; j < ncols_interleaved; j++) { - s[x * ncols_interleaved + j] = sumf[j] - sum_minf[j]; - } - } + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + ggml_gemv_q4_K_8x8_q8_K_generic(n, s, bs, vx, vy, nr, nc); #endif } -void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { - const int qk = QK8_0; +void ggml_gemv_iq4_nl_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { +#if defined(__AVX2__) + __m256i signextendlut = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i*)kvalues_iq4nl)); + signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); + + gemv_q4_b32_8x8_q8_0_lut_avx(n, s, bs, vx, vy, nr, nc, signextendlut); + + return; +#endif + + ggml_gemv_iq4_nl_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); +} + +void ggml_gemv_q2_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK_K; const int nb = n / qk; const int ncols_interleaved = 8; const int blocklen = 8; assert (n % qk == 0); - assert (nr % 4 == 0); assert (nc % ncols_interleaved == 0); UNUSED(s); @@ -1010,763 +1644,314 @@ void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo UNUSED(ncols_interleaved); UNUSED(blocklen); +#if defined(__AVX2__) + // Lookup table to convert signed nibbles to signed bytes + __m256i signextendlut = _mm256_castsi128_si256(_mm_set_epi8(-1, -2, -3, -4, -5, -6, -7, -8, 7, 6, 5, 4, 3, 2, 1, 0)); + signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); + // Shuffle masks to rearrange delta values to multiply with appropriate scales + __m128i deltamask = _mm_set_epi8(15, 14, 7, 6, 13, 12, 5, 4, 11, 10, 3, 2, 9, 8, 1, 0); + // Permute mask used for easier vector processing at later stages + __m256i finalpermutemask = _mm256_set_epi32(7, 5, 3, 1, 6, 4, 2, 0); + + const __m256i m3b = _mm256_set1_epi8(3); + const __m128i m4b_sse = _mm_set1_epi8(0xF); + + //Mask to get appropriate scales + __m128i scalemask1 = _mm_set_epi8(14,14,6,6,12,12,4,4,10,10,2,2,8,8,0,0); + __m128i scalemask2 = _mm_set_epi8(15,15,7,7,13,13,5,5,11,11,3,3,9,9,1,1); + + int64_t b_nb = n / QK_K; + + const block_q2_Kx8 * b_ptr_start = (const block_q2_Kx8 *)vx; + const block_q8_K * a_ptr_start = (const block_q8_K *)vy; + + // Process Q8_K blocks one by one + for (int64_t y = 0; y < nr; y++) { + + // Pointers to LHS blocks of block_q8_K format + const block_q8_K * a_ptr = a_ptr_start + (y * nb); + + // Take group of eight interleaved block_q2_K structures at each pass of the loop and perform dot product operation + for(int64_t x = 0; x < nc / 8; x++) { + + // Pointers to RHS blocks + const block_q2_Kx8 * b_ptr = b_ptr_start + (x * b_nb); + + // Master FP accumulators + __m256 acc_row = _mm256_setzero_ps(); + __m256 acc_min_rows = _mm256_setzero_ps(); + + for (int64_t b = 0; b < nb; b++) { + + // Load and convert to FP32 delta from block_q8_K + const __m256 row_scale_f32 = _mm256_set1_ps((a_ptr[b].d)); + + // Load the delta values for the 8 blocks interleaved in block_q2_Kx8 + // col_scale_f32 rearranged so as to multiply with appropriate quants + const __m256 col_scale_f32 = GGML_F32Cx8_REARRANGE_LOAD(b_ptr[b].d, deltamask); + const __m256 col_dmin_f32 = GGML_F32Cx8_LOAD(b_ptr[b].dmin); + + __m256i iacc_b = _mm256_setzero_si256(); + __m256i iacc_min_b = _mm256_setzero_si256(); + + // Processes eight sub blocks from each Q2_K in each iteration + for(int sb = 0; sb < QK_K / 128; sb++) { + + // Load the eight block_q2_K for eight sub blocks quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 + const __m256i rhs_raw_vec_0123_0 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + sb * 256)); + const __m256i rhs_raw_vec_4567_0 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_vec_0123_1 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_vec_4567_1 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_vec_0123_2 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_vec_4567_2 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_vec_0123_3 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_vec_4567_3 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 224 + sb * 256)); + + // 2-bit -> 8-bit + // Values of the 0th,2nd,4th,6th sub blocks of eight block_q2_K structures for the sb loop + const __m256i rhs_vec_0123_00 = _mm256_and_si256(rhs_raw_vec_0123_0, m3b); //B00(0-7) B01(0-7) B02(0-7) B03(0-7) + const __m256i rhs_vec_0123_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_0, 2), m3b); //B20(0-7) B21(0-7) B22(0-7) B23(0-7) + const __m256i rhs_vec_0123_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_0, 4), m3b); //B40(0-7) B41(0-7) B42(0-7) B43(0-7) + const __m256i rhs_vec_0123_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_0, 6), m3b); //B60(0-7) B61(0-7) B62(0-7) B63(0-7) + + const __m256i rhs_vec_4567_00 = _mm256_and_si256(rhs_raw_vec_4567_0, m3b); //B04(0-7) B05(0-7) B06(0-7) B07(0-7) + const __m256i rhs_vec_4567_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_0, 2), m3b); //B24(0-7) B25(0-7) B26(0-7) B27(0-7) + const __m256i rhs_vec_4567_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_0, 4), m3b); //B44(0-7) B45(0-7) B46(0-7) B47(0-7) + const __m256i rhs_vec_4567_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_0, 6), m3b); //B64(0-7) B65(0-7) B66(0-7) B67(0-7) + + const __m256i rhs_vec_0123_01 = _mm256_and_si256(rhs_raw_vec_0123_1, m3b); //B00(8-15) B01(8-15) B02(8-15) B03(8-15) + const __m256i rhs_vec_0123_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_1, 2), m3b); //B20(8-15) B21(8-15) B22(8-15) B23(8-15) + const __m256i rhs_vec_0123_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_1, 4), m3b); //B40(8-15) B41(8-15) B42(8-15) B43(8-15) + const __m256i rhs_vec_0123_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_1, 6), m3b); //B60(8-15) B61(8-15) B62(8-15) B63(8-15) + + const __m256i rhs_vec_4567_01 = _mm256_and_si256(rhs_raw_vec_4567_1, m3b); //B04(8-15) B05(8-15) B06(8-15) B07(8-15) + const __m256i rhs_vec_4567_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_1, 2), m3b); //B24(8-15) B25(8-15) B26(8-15) B27(8-15) + const __m256i rhs_vec_4567_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_1, 4), m3b); //B44(8-15) B45(8-15) B46(8-15) B47(8-15) + const __m256i rhs_vec_4567_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_1, 6), m3b); //B64(8-15) B65(8-15) B66(8-15) B67(8-15) + + // Values of the 1st,3rd,5th,7th sub blocks of eight block_q2_K structures for the sb loop + const __m256i rhs_vec_0123_10 = _mm256_and_si256(rhs_raw_vec_0123_2, m3b); //B10(0-7) B11(0-7) B12(0-7) B13(0-7) + const __m256i rhs_vec_0123_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_2, 2), m3b); //B30(0-7) B31(0-7) B32(0-7) B33(0-7) + const __m256i rhs_vec_0123_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_2, 4), m3b); //B50(0-7) B51(0-7) B52(0-7) B53(0-7) + const __m256i rhs_vec_0123_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_2, 6), m3b); //B70(0-7) B71(0-7) B72(0-7) B73(0-7) + + const __m256i rhs_vec_4567_10 = _mm256_and_si256(rhs_raw_vec_4567_2, m3b); //B14(0-7) B15(0-7) B16(0-7) B17(0-7) + const __m256i rhs_vec_4567_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_2, 2), m3b); //B34(0-7) B35(0-7) B36(0-7) B37(0-7) + const __m256i rhs_vec_4567_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_2, 4), m3b); //B54(0-7) B55(0-7) B56(0-7) B57(0-7) + const __m256i rhs_vec_4567_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_2, 6), m3b); //B74(0-7) B75(0-7) B76(0-7) B77(0-7) + + const __m256i rhs_vec_0123_11 = _mm256_and_si256(rhs_raw_vec_0123_3, m3b); //B10(8-15) B11(8-15) B12(8-15) B13(8-15) + const __m256i rhs_vec_0123_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_3, 2), m3b); //B30(8-15) B31(8-15) B32(8-15) B33(8-15) + const __m256i rhs_vec_0123_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_3, 4), m3b); //B50(8-15) B51(8-15) B52(8-15) B53(8-15) + const __m256i rhs_vec_0123_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_3, 6), m3b); //B70(8-15) B71(8-15) B72(8-15) B73(8-15) + + const __m256i rhs_vec_4567_11 = _mm256_and_si256(rhs_raw_vec_4567_3, m3b); //B14(8-15) B15(8-15) B16(8-15) B17(8-15) + const __m256i rhs_vec_4567_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_3, 2), m3b); //B34(8-15) B35(8-15) B36(8-15) B37(8-15) + const __m256i rhs_vec_4567_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_3, 4), m3b); //B54(8-15) B55(8-15) B56(8-15) B57(8-15) + const __m256i rhs_vec_4567_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_3, 6), m3b); //B74(8-15) B75(8-15) B76(8-15) B77(8-15) + + //Scales and Mins of corresponding sub blocks from different Q2_K structures are stored together + //s00 m00 s01 m01 s10 m10 s11 m11 s20 m20 s21 m21 s30 m30 s31 m31 s40 m40 s41 m41 s50 m50 s51 m51 s60 m60 s61 m61 s70 m70 s71 m71 + + const __m128i mins_and_scales_01 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + sb * 64)); + const __m128i mins_and_scales_23 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 48 + sb * 64)); + + // Extract scales which is lower half from mins_and_scales + const __m128i scales_01 = _mm_and_si128(mins_and_scales_01, m4b_sse); + const __m128i scales_23 = _mm_and_si128(mins_and_scales_23, m4b_sse); + const __m128i scales_45 = _mm_and_si128(mins_and_scales_45, m4b_sse); + const __m128i scales_67 = _mm_and_si128(mins_and_scales_67, m4b_sse); + + // Extract mins which is upper half from mins_and_scales + const __m256i mins_01 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_01, 4), m4b_sse)); + const __m256i mins_23 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_23, 4), m4b_sse)); + const __m256i mins_45 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_45, 4), m4b_sse)); + const __m256i mins_67 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_67, 4), m4b_sse)); + + // Scales of sub blocks in the sb loop + // Scales of the 0th sub block from each super block + __m128i scales_rearrange_0 = _mm_shuffle_epi8(scales_01, scalemask1); + __m256i scales_0 = _mm256_cvtepu8_epi16(scales_rearrange_0); + + // Scales of the 1st sub block from each super block + __m128i scales_rearrange_1 = _mm_shuffle_epi8(scales_01, scalemask2); + __m256i scales_1 = _mm256_cvtepu8_epi16(scales_rearrange_1); + + // Scales of the 2nd sub block from each super block + __m128i scales_rearrange_2 = _mm_shuffle_epi8(scales_23, scalemask1); + __m256i scales_2 = _mm256_cvtepu8_epi16(scales_rearrange_2); + + // Scales of the 3rd sub block from each super block + __m128i scales_rearrange_3 = _mm_shuffle_epi8(scales_23, scalemask2); + __m256i scales_3 = _mm256_cvtepu8_epi16(scales_rearrange_3); + + // Scales of the 4th sub block from each super block + __m128i scales_rearrange_4 = _mm_shuffle_epi8(scales_45, scalemask1); + __m256i scales_4 = _mm256_cvtepu8_epi16(scales_rearrange_4); + + // Scales of the 5th sub block from each super block + __m128i scales_rearrange_5 = _mm_shuffle_epi8(scales_45, scalemask2); + __m256i scales_5 = _mm256_cvtepu8_epi16(scales_rearrange_5); + + // Scales of the 6th sub block from each super block + __m128i scales_rearrange_6 = _mm_shuffle_epi8(scales_67, scalemask1); + __m256i scales_6 = _mm256_cvtepu8_epi16(scales_rearrange_6); + + // Scales of the 7th sub block from each super block + __m128i scales_rearrange_7 = _mm_shuffle_epi8(scales_67, scalemask2); + __m256i scales_7 = _mm256_cvtepu8_epi16(scales_rearrange_7); + + // Load the sub block values corresponding to sb in block_q8_K in batches of 16 bytes and replicate the same across 256 bit vector + __m256i lhs_vec_0 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + sb * 128))); + __m256i lhs_vec_1 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 16 + sb * 128))); + __m256i lhs_vec_2 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 32 + sb * 128))); + __m256i lhs_vec_3 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 48 + sb * 128))); + __m256i lhs_vec_4 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 64 + sb * 128))); + __m256i lhs_vec_5 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 80 + sb * 128))); + __m256i lhs_vec_6 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 96 + sb * 128))); + __m256i lhs_vec_7 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 112 + sb * 128))); + + lhs_vec_0 = _mm256_permute2f128_si256(lhs_vec_0, lhs_vec_0, 0); + lhs_vec_1 = _mm256_permute2f128_si256(lhs_vec_1, lhs_vec_1, 0); + lhs_vec_2 = _mm256_permute2f128_si256(lhs_vec_2, lhs_vec_2, 0); + lhs_vec_3 = _mm256_permute2f128_si256(lhs_vec_3, lhs_vec_3, 0); + lhs_vec_4 = _mm256_permute2f128_si256(lhs_vec_4, lhs_vec_4, 0); + lhs_vec_5 = _mm256_permute2f128_si256(lhs_vec_5, lhs_vec_5, 0); + lhs_vec_6 = _mm256_permute2f128_si256(lhs_vec_6, lhs_vec_6, 0); + lhs_vec_7 = _mm256_permute2f128_si256(lhs_vec_7, lhs_vec_7, 0); + + __m256i iacc_0 = _mm256_setzero_si256(); + __m256i iacc_1 = _mm256_setzero_si256(); + __m256i iacc_2 = _mm256_setzero_si256(); + __m256i iacc_3 = _mm256_setzero_si256(); + __m256i iacc_4 = _mm256_setzero_si256(); + __m256i iacc_5 = _mm256_setzero_si256(); + __m256i iacc_6 = _mm256_setzero_si256(); + __m256i iacc_7 = _mm256_setzero_si256(); + + // Dot product done within 32 bit lanes and accumulated in the same vector + // First done for 0th sub block and then for seven (1st - 7th) other sub blocks processed for each sb (sb < QK_K/128 loop) // B0(0-3) B4(0-3) B1(0-3) B5(0-3) B2(0-3) B6(0-3) B3(0-3) B7(0-3) with A0(0-3) + // B0(4-7) B4(4-7) B1(4-7) B5(4-7) B2(4-7) B6(4-7) B3(4-7) B7(4-7) with A0(4-7) + // B0(8-11) B4(8-11) B1(8-11) B5(8-11) B2(8-11) B6(8-11) B3(8-11) B7(8-11) with A0(8-11) + // B0(12-15) B4(12-15) B1(12-15) B5(12-15) B2(12-15) B6(12-15) B3(12-15) B7(12-15) with A0(12-15) + + iacc_0 = _mm256_add_epi16(iacc_0, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_00 ,_mm256_shuffle_epi32(rhs_vec_4567_00, 177), 170), _mm256_shuffle_epi32(lhs_vec_0, 0))); + iacc_0 = _mm256_add_epi16(iacc_0, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_00, 177) ,rhs_vec_4567_00, 170), _mm256_shuffle_epi32(lhs_vec_0, 85))); + + iacc_0 = _mm256_add_epi16(iacc_0, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_01 ,_mm256_shuffle_epi32(rhs_vec_4567_01, 177), 170), _mm256_shuffle_epi32(lhs_vec_0, 170))); + iacc_0 = _mm256_add_epi16(iacc_0, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_01, 177) ,rhs_vec_4567_01, 170), _mm256_shuffle_epi32(lhs_vec_0, 255))); + + iacc_0 = _mm256_madd_epi16(iacc_0, scales_0); + + iacc_1 = _mm256_add_epi16(iacc_1, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_10 ,_mm256_shuffle_epi32(rhs_vec_4567_10, 177), 170), _mm256_shuffle_epi32(lhs_vec_1, 0))); + iacc_1 = _mm256_add_epi16(iacc_1, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_10, 177) ,rhs_vec_4567_10, 170), _mm256_shuffle_epi32(lhs_vec_1, 85))); + + iacc_1 = _mm256_add_epi16(iacc_1, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_11 ,_mm256_shuffle_epi32(rhs_vec_4567_11, 177), 170), _mm256_shuffle_epi32(lhs_vec_1, 170))); + iacc_1 = _mm256_add_epi16(iacc_1, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_11, 177) ,rhs_vec_4567_11, 170), _mm256_shuffle_epi32(lhs_vec_1, 255))); + + iacc_1 = _mm256_madd_epi16(iacc_1, scales_1); + + iacc_2 = _mm256_add_epi16(iacc_2, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_20 ,_mm256_shuffle_epi32(rhs_vec_4567_20, 177), 170), _mm256_shuffle_epi32(lhs_vec_2, 0))); + iacc_2 = _mm256_add_epi16(iacc_2, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_20, 177) ,rhs_vec_4567_20, 170), _mm256_shuffle_epi32(lhs_vec_2, 85))); + + iacc_2 = _mm256_add_epi16(iacc_2, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_21 ,_mm256_shuffle_epi32(rhs_vec_4567_21, 177), 170), _mm256_shuffle_epi32(lhs_vec_2, 170))); + iacc_2 = _mm256_add_epi16(iacc_2, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_21, 177) ,rhs_vec_4567_21, 170), _mm256_shuffle_epi32(lhs_vec_2, 255))); + + iacc_2 = _mm256_madd_epi16(iacc_2, scales_2); + + iacc_3 = _mm256_add_epi16(iacc_3, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_30 ,_mm256_shuffle_epi32(rhs_vec_4567_30, 177), 170), _mm256_shuffle_epi32(lhs_vec_3, 0))); + iacc_3 = _mm256_add_epi16(iacc_3, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_30, 177) ,rhs_vec_4567_30, 170), _mm256_shuffle_epi32(lhs_vec_3, 85))); + + iacc_3 = _mm256_add_epi16(iacc_3, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_31 ,_mm256_shuffle_epi32(rhs_vec_4567_31, 177), 170), _mm256_shuffle_epi32(lhs_vec_3, 170))); + iacc_3 = _mm256_add_epi16(iacc_3, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_31, 177) ,rhs_vec_4567_31, 170), _mm256_shuffle_epi32(lhs_vec_3, 255))); + + iacc_3 = _mm256_madd_epi16(iacc_3, scales_3); + + iacc_4 = _mm256_add_epi16(iacc_4, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_40 ,_mm256_shuffle_epi32(rhs_vec_4567_40, 177), 170), _mm256_shuffle_epi32(lhs_vec_4, 0))); + iacc_4 = _mm256_add_epi16(iacc_4, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_40, 177) ,rhs_vec_4567_40, 170), _mm256_shuffle_epi32(lhs_vec_4, 85))); + + iacc_4 = _mm256_add_epi16(iacc_4, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_41 ,_mm256_shuffle_epi32(rhs_vec_4567_41, 177), 170), _mm256_shuffle_epi32(lhs_vec_4, 170))); + iacc_4 = _mm256_add_epi16(iacc_4, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_41, 177) ,rhs_vec_4567_41, 170), _mm256_shuffle_epi32(lhs_vec_4, 255))); + + iacc_4 = _mm256_madd_epi16(iacc_4, scales_4); + + iacc_5 = _mm256_add_epi16(iacc_5, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_50 ,_mm256_shuffle_epi32(rhs_vec_4567_50, 177), 170), _mm256_shuffle_epi32(lhs_vec_5, 0))); + iacc_5 = _mm256_add_epi16(iacc_5, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_50, 177) ,rhs_vec_4567_50, 170), _mm256_shuffle_epi32(lhs_vec_5, 85))); + + iacc_5 = _mm256_add_epi16(iacc_5, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_51 ,_mm256_shuffle_epi32(rhs_vec_4567_51, 177), 170), _mm256_shuffle_epi32(lhs_vec_5, 170))); + iacc_5 = _mm256_add_epi16(iacc_5, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_51, 177) ,rhs_vec_4567_51, 170), _mm256_shuffle_epi32(lhs_vec_5, 255))); + + iacc_5 = _mm256_madd_epi16(iacc_5, scales_5); + + iacc_6 = _mm256_add_epi16(iacc_6, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_60 ,_mm256_shuffle_epi32(rhs_vec_4567_60, 177), 170), _mm256_shuffle_epi32(lhs_vec_6, 0))); + iacc_6 = _mm256_add_epi16(iacc_6, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_60, 177) ,rhs_vec_4567_60, 170), _mm256_shuffle_epi32(lhs_vec_6, 85))); + + iacc_6 = _mm256_add_epi16(iacc_6, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_61 ,_mm256_shuffle_epi32(rhs_vec_4567_61, 177), 170), _mm256_shuffle_epi32(lhs_vec_6, 170))); + iacc_6 = _mm256_add_epi16(iacc_6, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_61, 177) ,rhs_vec_4567_61, 170), _mm256_shuffle_epi32(lhs_vec_6, 255))); + + iacc_6 = _mm256_madd_epi16(iacc_6, scales_6); + + iacc_7 = _mm256_add_epi16(iacc_7, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_70 ,_mm256_shuffle_epi32(rhs_vec_4567_70, 177), 170), _mm256_shuffle_epi32(lhs_vec_7, 0))); + iacc_7 = _mm256_add_epi16(iacc_7, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_70, 177) ,rhs_vec_4567_70, 170), _mm256_shuffle_epi32(lhs_vec_7, 85))); + + iacc_7 = _mm256_add_epi16(iacc_7, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_71 ,_mm256_shuffle_epi32(rhs_vec_4567_71, 177), 170), _mm256_shuffle_epi32(lhs_vec_7, 170))); + iacc_7 = _mm256_add_epi16(iacc_7, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_71, 177) ,rhs_vec_4567_71, 170), _mm256_shuffle_epi32(lhs_vec_7, 255))); + + iacc_7 = _mm256_madd_epi16(iacc_7, scales_7); + + // Accumulate the iacc value for one sb + __m256i iacc_sb = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_0, iacc_1), _mm256_add_epi32(iacc_2, iacc_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_4, iacc_5), _mm256_add_epi32(iacc_6, iacc_7))); + + __m128i q8sums = _mm_loadu_si128((const __m128i *)(a_ptr[b].bsums + sb * 8)); + __m256i q8s = _mm256_castsi128_si256(q8sums); + q8s= _mm256_permute2f128_si256(q8s, q8s, 0); + + // Broadcast the bsums of the two corresponding subblocks of q8_k + // Multiply-Add with corresponding mins of Q2_Kx8 with bsums + __m256i iacc_min_sb_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(q8s, 0), mins_01); + __m256i iacc_min_sb_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(q8s, 85), mins_23); + __m256i iacc_min_sb_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(q8s, 170), mins_45); + __m256i iacc_min_sb_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(q8s, 255), mins_67); + + __m256i iacc_min_sb = _mm256_add_epi32(_mm256_add_epi32(iacc_min_sb_01, iacc_min_sb_23), _mm256_add_epi32(iacc_min_sb_45,iacc_min_sb_67)); + + // Accumulate for the complete block + iacc_b = _mm256_add_epi32(iacc_b, iacc_sb); + iacc_min_b = _mm256_add_epi32(iacc_min_b, iacc_min_sb); + } + + //Multiply-Add with scale values for complete super block + acc_row = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_b), _mm256_mul_ps(col_scale_f32, row_scale_f32), acc_row); + acc_min_rows = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_min_b), _mm256_mul_ps(col_dmin_f32, row_scale_f32), acc_min_rows); + } + // Accumulated output values permuted so as to be stored in appropriate order post accumulation + acc_row = _mm256_permutevar8x32_ps(acc_row, finalpermutemask); + _mm256_storeu_ps(s + (y * nr + x * 8), _mm256_sub_ps(acc_row, acc_min_rows)); + } + } +#else + + ggml_gemv_q2_K_8x8_q8_K_generic(n, s, bs, vx, vy, nr, nc); + +#endif +} + +void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { #if defined(__AVX2__) || defined(__AVX512F__) { - const block_q4_0x8 * b_ptr_start = (const block_q4_0x8 *)vx; - const block_q8_0x4 * a_ptr_start = (const block_q8_0x4 *)vy; - int64_t b_nb = n / QK4_0; - int64_t y = 0; - // Mask to mask out nibbles from packed bytes - const __m256i m4b = _mm256_set1_epi8(0x0F); - const __m128i loadMask = _mm_blend_epi32(_mm_setzero_si128(), _mm_set1_epi32(0xFFFFFFFF), 3); // Lookup table to convert signed nibbles to signed bytes __m256i signextendlut = _mm256_castsi128_si256(_mm_set_epi8(-1, -2, -3, -4, -5, -6, -7, -8, 7, 6, 5, 4, 3, 2, 1, 0)); signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); - // Permute mask used for easier vector processing at later stages - __m256i requiredOrder = _mm256_set_epi32(3, 2, 1, 0, 7, 6, 5, 4); - int64_t xstart = 0; - int anr = nr - nr%16; // Used to align nr with boundary of 16 - #ifdef __AVX512F__ - int anc = nc - nc%16; // Used to align nc with boundary of 16 - // Mask to mask out nibbles from packed bytes expanded to 512 bit length - const __m512i m4bexpanded = _mm512_set1_epi8(0x0F); - // Lookup table to convert signed nibbles to signed bytes expanded to 512 bit length - __m512i signextendlutexpanded = _mm512_inserti32x8(_mm512_castsi256_si512(signextendlut), signextendlut, 1); - // Take group of four block_q8_0x4 structures at each pass of the loop and perform dot product operation - for (; y < anr / 4; y += 4) { + gemm_q4_b32_8x8_q8_0_lut_avx(n, s, bs, vx, vy, nr, nc, signextendlut); - const block_q8_0x4 * a_ptrs[4]; - - a_ptrs[0] = a_ptr_start + (y * nb); - for (int i = 0; i < 3; ++i) { - a_ptrs[i + 1] = a_ptrs[i] + nb; - } - - // Take group of two block_q4_0x8 structures at each pass of the loop and perform dot product operation - for (int64_t x = 0; x < anc / 8; x += 2) { - - const block_q4_0x8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); - const block_q4_0x8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); - - // Master FP accumulators - __m512 acc_rows[16]; - for (int i = 0; i < 16; i++) { - acc_rows[i] = _mm512_setzero_ps(); - } - - for (int64_t b = 0; b < nb; b++) { - // Load the sixteen block_q4_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....BE,BF - const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs)); - const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 32)); - const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 64)); - const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 96)); - - const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs)); - const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 32)); - const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 64)); - const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 96)); - - // Save the values in the following vectors in the formats B0B1B4B5B8B9BCBD, B2B3B6B7BABBBEBF for further processing and storing of values - const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); - const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); - - const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); - const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); - const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); - const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); - - const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); - const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); - const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); - const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); - - // 4-bit -> 8-bit - Sign is maintained - const __m512i rhs_mat_014589CD_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_0, m4bexpanded)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) B8(0-7) B9(0-7) BC(0-7) BD(0-7) - const __m512i rhs_mat_2367ABEF_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_0, m4bexpanded)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) BA(0-7) BB(0-7) BE(0-7) BF(0-7) - - const __m512i rhs_mat_014589CD_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_1, m4bexpanded)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) B8(8-15) B9(8-15) BC(8-15) BD(8-15) - const __m512i rhs_mat_2367ABEF_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_1, m4bexpanded)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) BA(8-15) BB(8-15) BE(8-15) BF(8-15) - - const __m512i rhs_mat_014589CD_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m4bexpanded)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) B8(16-23) B9(16-23) BC(16-23) BD(16-23) - const __m512i rhs_mat_2367ABEF_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m4bexpanded)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) BA(16-23) BB(16-23) BE(16-23) BF(16-23) - - const __m512i rhs_mat_014589CD_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m4bexpanded)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) B8(24-31) B9(24-31) BC(24-31) BD(24-31) - const __m512i rhs_mat_2367ABEF_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m4bexpanded)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) BA(24-31) BB(24-31) BE(24-31) BF(24-31) - - // Shuffle pattern one - right side input - const __m512i rhs_mat_014589CD_0_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) B8(0-3) B9(0-3) B8(0-3) B9(0-3) BC(0-3) BD(0-3) BC(0-3) BD(0-3) - const __m512i rhs_mat_2367ABEF_0_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) BA(0-3) BB(0-3) BA(0-3) BB(0-3) BE(0-3) BF(0-3) BE(0-3) BF(0-3) - - const __m512i rhs_mat_014589CD_1_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) B8(8-11) B9(8-11) B8(8-11) B9(8-11) BC(8-11) BD(8-11) BC(8-11) BD(8-11) - const __m512i rhs_mat_2367ABEF_1_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) BA(8-11) BB(8-11) BA(8-11) BB(8-11) BE(8-11) BF(8-11) BE(8-11) BF(8-11) - - const __m512i rhs_mat_014589CD_2_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) B8(16-19) B9(16-19) B8(16-19) B9(16-19) BC(16-19) BD(16-19) BC(16-19) BD(16-19) - const __m512i rhs_mat_2367ABEF_2_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) BA(16-19) BB(16-19) BA(16-19) BB(16-19) BE(16-19) BF(16-19) BE(16-19) BF(16-19) - - const __m512i rhs_mat_014589CD_3_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) B8(24-27) B9(24-27) B8(24-27) B9(24-27) BC(24-27) BD(24-27) BC(24-27) BD(24-27) - const __m512i rhs_mat_2367ABEF_3_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) BA(24-27) BB(24-27) BA(24-27) BB(24-27) BE(24-27) BF(24-27) BE(24-27) BF(24-27) - - // Shuffle pattern two - right side input - - const __m512i rhs_mat_014589CD_0_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) B8(4-7) B9(4-7) B8(4-7) B9(4-7) BC(4-7) BD(4-7) BC(4-7) BD(4-7) - const __m512i rhs_mat_2367ABEF_0_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) BA(4-7) BB(4-7) BA(4-7) BB(4-7) BE(4-7) BF(4-7) BE(4-7) BF(4-7) - - const __m512i rhs_mat_014589CD_1_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) B8(12-15) B9(12-15) B8(12-15) B9(12-15) BC(12-15) BD(12-15) BC(12-15) BD(12-15) - const __m512i rhs_mat_2367ABEF_1_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) BA(12-15) BB(12-15) BA(12-15) BB(12-15) BE(12-15) BF(12-15) BE(12-15) BF(12-15) - - const __m512i rhs_mat_014589CD_2_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) B8(20-23) B9(20-23) B8(20-23) B9(20-23) BC(20-23) BD(20-23) BC(20-23) BD(20-23) - const __m512i rhs_mat_2367ABEF_2_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) BA(20-23) BB(20-23) BA(20-23) BB(20-23) BE(20-23) BF(20-23) BE(20-23) BF(20-23) - - const __m512i rhs_mat_014589CD_3_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) B8(28-31) B9(28-31) B8(28-31) B9(28-31) BC(28-31) BD(28-31) BC(28-31) BD(28-31) - const __m512i rhs_mat_2367ABEF_3_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) BA(28-31) BB(28-31) BA(28-31) BB(28-31) BE(28-31) BF(28-31) BE(28-31) BF(28-31) - - // Scale values - Load the weight scale values of two block_q4_0x8 - const __m512 col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); - - // Process LHS in pairs of rows - for (int rp = 0; rp < 4; rp++) { - - // Load the four block_q4_0 quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 - // Loaded as set of 128 bit vectors and repeated and stored into a 256 bit vector before again repeating into 512 bit vector - __m256i lhs_mat_ymm_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs))); - __m256i lhs_mat_ymm_01_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 0); - __m256i lhs_mat_ymm_23_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 17); - __m256i lhs_mat_ymm_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 32))); - __m256i lhs_mat_ymm_01_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 0); - __m256i lhs_mat_ymm_23_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 17); - __m256i lhs_mat_ymm_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 64))); - __m256i lhs_mat_ymm_01_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 0); - __m256i lhs_mat_ymm_23_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 17); - __m256i lhs_mat_ymm_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 96))); - __m256i lhs_mat_ymm_01_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 0); - __m256i lhs_mat_ymm_23_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 17); - - __m512i lhs_mat_01_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_0), lhs_mat_ymm_01_0, 1); - __m512i lhs_mat_23_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_0), lhs_mat_ymm_23_0, 1); - __m512i lhs_mat_01_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_1), lhs_mat_ymm_01_1, 1); - __m512i lhs_mat_23_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_1), lhs_mat_ymm_23_1, 1); - __m512i lhs_mat_01_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_2), lhs_mat_ymm_01_2, 1); - __m512i lhs_mat_23_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_2), lhs_mat_ymm_23_2, 1); - __m512i lhs_mat_01_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_3), lhs_mat_ymm_01_3, 1); - __m512i lhs_mat_23_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_3), lhs_mat_ymm_23_3, 1); - - // Shuffle pattern one - left side input - - const __m512i lhs_mat_01_0_sp1 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) - const __m512i lhs_mat_23_0_sp1 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) - - const __m512i lhs_mat_01_1_sp1 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) - const __m512i lhs_mat_23_1_sp1 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) - - const __m512i lhs_mat_01_2_sp1 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) - const __m512i lhs_mat_23_2_sp1 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) - - const __m512i lhs_mat_01_3_sp1 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) - const __m512i lhs_mat_23_3_sp1 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) - - // Shuffle pattern two - left side input - - const __m512i lhs_mat_01_0_sp2 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) - const __m512i lhs_mat_23_0_sp2 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) - - const __m512i lhs_mat_01_1_sp2 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) - const __m512i lhs_mat_23_1_sp2 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) - - const __m512i lhs_mat_01_2_sp2 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) - const __m512i lhs_mat_23_2_sp2 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) - - const __m512i lhs_mat_01_3_sp2 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) - const __m512i lhs_mat_23_3_sp2 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) - - // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane - // Resembles MMLAs into 2x2 matrices in ARM Version - const __m512i zero = _mm512_setzero_epi32(); - __m512i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_01_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_01_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_01_0_sp1, rhs_mat_014589CD_0_sp1); - __m512i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367ABEF_0_sp1); - __m512i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_23_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_23_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_23_0_sp1, rhs_mat_014589CD_0_sp1); - __m512i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367ABEF_0_sp1); - __m512i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_01_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_01_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_01_0_sp2, rhs_mat_014589CD_0_sp2); - __m512i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367ABEF_0_sp2); - __m512i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_23_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_23_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_23_0_sp2, rhs_mat_014589CD_0_sp2); - __m512i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367ABEF_0_sp2); - - // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block - __m512i iacc_mat_00 = _mm512_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); - __m512i iacc_mat_01 = _mm512_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); - __m512i iacc_mat_10 = _mm512_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); - __m512i iacc_mat_11 = _mm512_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); - - - // Straighten out to make 4 row vectors - __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); - __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); - __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); - __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); - - // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes - const __m128i row_scale_f16 = _mm_shuffle_epi32(_mm_maskload_epi32((int const*)(a_ptrs[rp][b].d), loadMask), 68); - const __m512 row_scale_f32 = GGML_F32Cx16_REPEAT_LOAD(row_scale_f16); - - // Multiply with appropiate scales and accumulate - acc_rows[rp * 4] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); - acc_rows[rp * 4 + 1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); - acc_rows[rp * 4 + 2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); - acc_rows[rp * 4 + 3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); - } - } - - // Store the accumulated values - for (int i = 0; i < 16; i++) { - _mm512_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); - } - } - } - // Take a block_q8_0x4 structures at each pass of the loop and perform dot product operation - for (; y < nr / 4; y ++) { - - const block_q8_0x4 * a_ptr = a_ptr_start + (y * nb); - - // Take group of two block_q4_0x8 structures at each pass of the loop and perform dot product operation - for (int64_t x = 0; x < anc / 8; x += 2) { - - const block_q4_0x8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); - const block_q4_0x8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); - - // Master FP accumulators - __m512 acc_rows[4]; - for (int i = 0; i < 4; i++) { - acc_rows[i] = _mm512_setzero_ps(); - } - - for (int64_t b = 0; b < nb; b++) { - // Load the sixteen block_q4_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....BE,BF - const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs)); - const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 32)); - const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 64)); - const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 96)); - - const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs)); - const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 32)); - const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 64)); - const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 96)); - - // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of valuess - const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); - const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); - - const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); - const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); - const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); - const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); - - const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); - const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); - const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); - const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); - - // 4-bit -> 8-bit - Sign is maintained - const __m512i rhs_mat_014589CD_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_0, m4bexpanded)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) B8(0-7) B9(0-7) BC(0-7) BD(0-7) - const __m512i rhs_mat_2367ABEF_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_0, m4bexpanded)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) BA(0-7) BB(0-7) BE(0-7) BF(0-7) - - const __m512i rhs_mat_014589CD_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_1, m4bexpanded)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) B8(8-15) B9(8-15) BC(8-15) BD(8-15) - const __m512i rhs_mat_2367ABEF_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_1, m4bexpanded)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) BA(8-15) BB(8-15) BE(8-15) BF(8-15) - - const __m512i rhs_mat_014589CD_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m4bexpanded)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) B8(16-23) B9(16-23) BC(16-23) BD(16-23) - const __m512i rhs_mat_2367ABEF_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m4bexpanded)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) BA(16-23) BB(16-23) BE(16-23) BF(16-23) - - const __m512i rhs_mat_014589CD_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m4bexpanded)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) B8(24-31) B9(24-31) BC(24-31) BD(24-31) - const __m512i rhs_mat_2367ABEF_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m4bexpanded)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) BA(24-31) BB(24-31) BE(24-31) BF(24-31) - - // Shuffle pattern one - right side input - const __m512i rhs_mat_014589CD_0_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) B8(0-3) B9(0-3) B8(0-3) B9(0-3) BC(0-3) BD(0-3) BC(0-3) BD(0-3) - const __m512i rhs_mat_2367ABEF_0_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) BA(0-3) BB(0-3) BA(0-3) BB(0-3) BE(0-3) BF(0-3) BE(0-3) BF(0-3) - - const __m512i rhs_mat_014589CD_1_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) B8(8-11) B9(8-11) B8(8-11) B9(8-11) BC(8-11) BD(8-11) BC(8-11) BD(8-11) - const __m512i rhs_mat_2367ABEF_1_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) BA(8-11) BB(8-11) BA(8-11) BB(8-11) BE(8-11) BF(8-11) BE(8-11) BF(8-11) - - const __m512i rhs_mat_014589CD_2_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) B8(16-19) B9(16-19) B8(16-19) B9(16-19) BC(16-19) BD(16-19) BC(16-19) BD(16-19) - const __m512i rhs_mat_2367ABEF_2_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) BA(16-19) BB(16-19) BA(16-19) BB(16-19) BE(16-19) BF(16-19) BE(16-19) BF(16-19) - - const __m512i rhs_mat_014589CD_3_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) B8(24-27) B9(24-27) B8(24-27) B9(24-27) BC(24-27) BD(24-27) BC(24-27) BD(24-27) - const __m512i rhs_mat_2367ABEF_3_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) BA(24-27) BB(24-27) BA(24-27) BB(24-27) BE(24-27) BF(24-27) BE(24-27) BF(24-27) - - // Shuffle pattern two - right side input - - const __m512i rhs_mat_014589CD_0_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) B8(4-7) B9(4-7) B8(4-7) B9(4-7) BC(4-7) BD(4-7) BC(4-7) BD(4-7) - const __m512i rhs_mat_2367ABEF_0_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) BA(4-7) BB(4-7) BA(4-7) BB(4-7) BE(4-7) BF(4-7) BE(4-7) BF(4-7) - - const __m512i rhs_mat_014589CD_1_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) B8(12-15) B9(12-15) B8(12-15) B9(12-15) BC(12-15) BD(12-15) BC(12-15) BD(12-15) - const __m512i rhs_mat_2367ABEF_1_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) BA(12-15) BB(12-15) BA(12-15) BB(12-15) BE(12-15) BF(12-15) BE(12-15) BF(12-15) - - const __m512i rhs_mat_014589CD_2_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) B8(20-23) B9(20-23) B8(20-23) B9(20-23) BC(20-23) BD(20-23) BC(20-23) BD(20-23) - const __m512i rhs_mat_2367ABEF_2_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) BA(20-23) BB(20-23) BA(20-23) BB(20-23) BE(20-23) BF(20-23) BE(20-23) BF(20-23) - - const __m512i rhs_mat_014589CD_3_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) B8(28-31) B9(28-31) B8(28-31) B9(28-31) BC(28-31) BD(28-31) BC(28-31) BD(28-31) - const __m512i rhs_mat_2367ABEF_3_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) BA(28-31) BB(28-31) BA(28-31) BB(28-31) BE(28-31) BF(28-31) BE(28-31) BF(28-31) - - - // Scale values - Load the weight scale values of two block_q4_0x8 - const __m512 col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); - - // Load the four block_q4_0 quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 - // Loaded as set of 128 bit vectors and repeated and stored into a 256 bit vector before again repeating into 512 bit vector - __m256i lhs_mat_ymm_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs))); - __m256i lhs_mat_ymm_01_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 0); - __m256i lhs_mat_ymm_23_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 17); - __m256i lhs_mat_ymm_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 32))); - __m256i lhs_mat_ymm_01_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 0); - __m256i lhs_mat_ymm_23_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 17); - __m256i lhs_mat_ymm_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 64))); - __m256i lhs_mat_ymm_01_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 0); - __m256i lhs_mat_ymm_23_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 17); - __m256i lhs_mat_ymm_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 96))); - __m256i lhs_mat_ymm_01_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 0); - __m256i lhs_mat_ymm_23_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 17); - - __m512i lhs_mat_01_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_0), lhs_mat_ymm_01_0, 1); - __m512i lhs_mat_23_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_0), lhs_mat_ymm_23_0, 1); - __m512i lhs_mat_01_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_1), lhs_mat_ymm_01_1, 1); - __m512i lhs_mat_23_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_1), lhs_mat_ymm_23_1, 1); - __m512i lhs_mat_01_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_2), lhs_mat_ymm_01_2, 1); - __m512i lhs_mat_23_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_2), lhs_mat_ymm_23_2, 1); - __m512i lhs_mat_01_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_3), lhs_mat_ymm_01_3, 1); - __m512i lhs_mat_23_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_3), lhs_mat_ymm_23_3, 1); - - // Shuffle pattern one - left side input - - const __m512i lhs_mat_01_0_sp1 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) - const __m512i lhs_mat_23_0_sp1 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) - - const __m512i lhs_mat_01_1_sp1 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) - const __m512i lhs_mat_23_1_sp1 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) - - const __m512i lhs_mat_01_2_sp1 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) - const __m512i lhs_mat_23_2_sp1 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) - - const __m512i lhs_mat_01_3_sp1 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) - const __m512i lhs_mat_23_3_sp1 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) - - // Shuffle pattern two - left side input - - const __m512i lhs_mat_01_0_sp2 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) - const __m512i lhs_mat_23_0_sp2 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) - - const __m512i lhs_mat_01_1_sp2 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) - const __m512i lhs_mat_23_1_sp2 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) - - const __m512i lhs_mat_01_2_sp2 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) - const __m512i lhs_mat_23_2_sp2 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) - - const __m512i lhs_mat_01_3_sp2 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) - const __m512i lhs_mat_23_3_sp2 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) - - // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane - // Resembles MMLAs into 2x2 matrices in ARM Version - const __m512i zero = _mm512_setzero_epi32(); - __m512i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_01_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_01_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_01_0_sp1, rhs_mat_014589CD_0_sp1); - __m512i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367ABEF_0_sp1); - __m512i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_23_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_23_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_23_0_sp1, rhs_mat_014589CD_0_sp1); - __m512i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367ABEF_0_sp1); - __m512i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_01_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_01_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_01_0_sp2, rhs_mat_014589CD_0_sp2); - __m512i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367ABEF_0_sp2); - __m512i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_23_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_23_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_23_0_sp2, rhs_mat_014589CD_0_sp2); - __m512i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367ABEF_0_sp2); - - // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block - __m512i iacc_mat_00 = _mm512_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); - __m512i iacc_mat_01 = _mm512_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); - __m512i iacc_mat_10 = _mm512_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); - __m512i iacc_mat_11 = _mm512_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); - - - // Straighten out to make 4 row vectors - __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); - __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); - __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); - __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); - - // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes - const __m128i row_scale_f16 = _mm_shuffle_epi32(_mm_maskload_epi32((int const*)(a_ptr[b].d), loadMask), 68); - const __m512 row_scale_f32 = GGML_F32Cx16_REPEAT_LOAD(row_scale_f16); - - // Multiply with appropiate scales and accumulate - acc_rows[0] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); - acc_rows[1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); - acc_rows[2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); - acc_rows[3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); - } - - // Store the accumulated values - for (int i = 0; i < 4; i++) { - _mm512_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); - } - } - } - if (anc != nc) { - xstart = anc/8; - y = 0; - } - #endif // __AVX512F__ - - // Take group of four block_q8_0x4 structures at each pass of the loop and perform dot product operation - - for (; y < anr / 4; y += 4) { - const block_q8_0x4 * a_ptrs[4]; - - a_ptrs[0] = a_ptr_start + (y * nb); - for (int i = 0; i < 3; ++i) { - a_ptrs[i + 1] = a_ptrs[i] + nb; - } - - // Take group of eight block_q4_0x8 structures at each pass of the loop and perform dot product operation - for (int64_t x = xstart; x < nc / 8; x++) { - - const block_q4_0x8 * b_ptr = b_ptr_start + (x * b_nb); - - // Master FP accumulators - __m256 acc_rows[16]; - for (int i = 0; i < 16; i++) { - acc_rows[i] = _mm256_setzero_ps(); - } - - for (int64_t b = 0; b < nb; b++) { - // Load the eight block_q4_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 - const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs)); - const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32)); - const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64)); - const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96)); - - // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of values - const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); - const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); - - // 4-bit -> 8-bit - Sign is maintained - const __m256i rhs_mat_0145_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_0, m4b)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) - const __m256i rhs_mat_2367_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_0, m4b)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) - - const __m256i rhs_mat_0145_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_1, m4b)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) - const __m256i rhs_mat_2367_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_1, m4b)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) - - const __m256i rhs_mat_0145_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m4b)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) - const __m256i rhs_mat_2367_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m4b)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) - - const __m256i rhs_mat_0145_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m4b)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) - const __m256i rhs_mat_2367_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m4b)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) - - // Shuffle pattern one - right side input - const __m256i rhs_mat_0145_0_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_0, 136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) - const __m256i rhs_mat_2367_0_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_0, 136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) - - const __m256i rhs_mat_0145_1_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_1, 136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) - const __m256i rhs_mat_2367_1_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_1, 136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) - - const __m256i rhs_mat_0145_2_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_2, 136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) - const __m256i rhs_mat_2367_2_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_2, 136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) - - const __m256i rhs_mat_0145_3_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_3, 136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) - const __m256i rhs_mat_2367_3_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_3, 136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) - - // Shuffle pattern two - right side input - - const __m256i rhs_mat_0145_0_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_0, 221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) - const __m256i rhs_mat_2367_0_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_0, 221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) - - const __m256i rhs_mat_0145_1_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_1, 221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) - const __m256i rhs_mat_2367_1_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_1, 221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) - - const __m256i rhs_mat_0145_2_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_2, 221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) - const __m256i rhs_mat_2367_2_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_2, 221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) - - const __m256i rhs_mat_0145_3_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_3, 221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) - const __m256i rhs_mat_2367_3_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_3, 221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) - - // Scale values - Load the wight scale values of block_q4_0x8 - const __m256 col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); - - // Process LHS in groups of four - for (int rp = 0; rp < 4; rp++) { - // Load the four block_q4_0 quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 - // Loaded as set of 128 bit vectors and repeated into a 256 bit vector - __m256i lhs_mat_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs))); - __m256i lhs_mat_01_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 0); - __m256i lhs_mat_23_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 17); - __m256i lhs_mat_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 32))); - __m256i lhs_mat_01_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 0); - __m256i lhs_mat_23_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 17); - __m256i lhs_mat_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 64))); - __m256i lhs_mat_01_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 0); - __m256i lhs_mat_23_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 17); - __m256i lhs_mat_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 96))); - __m256i lhs_mat_01_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 0); - __m256i lhs_mat_23_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 17); - - // Shuffle pattern one - left side input - const __m256i lhs_mat_01_0_sp1 = _mm256_shuffle_epi32(lhs_mat_01_0, 160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) - const __m256i lhs_mat_23_0_sp1 = _mm256_shuffle_epi32(lhs_mat_23_0, 160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) - - const __m256i lhs_mat_01_1_sp1 = _mm256_shuffle_epi32(lhs_mat_01_1, 160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) - const __m256i lhs_mat_23_1_sp1 = _mm256_shuffle_epi32(lhs_mat_23_1, 160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) - - const __m256i lhs_mat_01_2_sp1 = _mm256_shuffle_epi32(lhs_mat_01_2, 160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) - const __m256i lhs_mat_23_2_sp1 = _mm256_shuffle_epi32(lhs_mat_23_2, 160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) - - const __m256i lhs_mat_01_3_sp1 = _mm256_shuffle_epi32(lhs_mat_01_3, 160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) - const __m256i lhs_mat_23_3_sp1 = _mm256_shuffle_epi32(lhs_mat_23_3, 160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) - - // Shuffle pattern two - left side input - const __m256i lhs_mat_01_0_sp2 = _mm256_shuffle_epi32(lhs_mat_01_0, 245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) - const __m256i lhs_mat_23_0_sp2 = _mm256_shuffle_epi32(lhs_mat_23_0, 245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) - - const __m256i lhs_mat_01_1_sp2 = _mm256_shuffle_epi32(lhs_mat_01_1, 245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) - const __m256i lhs_mat_23_1_sp2 = _mm256_shuffle_epi32(lhs_mat_23_1, 245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) - - const __m256i lhs_mat_01_2_sp2 = _mm256_shuffle_epi32(lhs_mat_01_2, 245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) - const __m256i lhs_mat_23_2_sp2 = _mm256_shuffle_epi32(lhs_mat_23_2, 245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) - - const __m256i lhs_mat_01_3_sp2 = _mm256_shuffle_epi32(lhs_mat_01_3, 245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) - const __m256i lhs_mat_23_3_sp2 = _mm256_shuffle_epi32(lhs_mat_23_3, 245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) - - // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane - // Resembles MMLAs into 2x2 matrices in ARM Version - const __m256i zero = _mm256_setzero_si256(); - __m256i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_01_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_01_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_01_0_sp1, rhs_mat_0145_0_sp1); - __m256i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367_0_sp1); - __m256i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_23_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_23_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_23_0_sp1, rhs_mat_0145_0_sp1); - __m256i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367_0_sp1); - __m256i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_01_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_01_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_01_0_sp2, rhs_mat_0145_0_sp2); - __m256i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367_0_sp2); - __m256i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_23_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_23_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_23_0_sp2, rhs_mat_0145_0_sp2); - __m256i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367_0_sp2); - - // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block - __m256i iacc_mat_00 = _mm256_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); - __m256i iacc_mat_01 = _mm256_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); - __m256i iacc_mat_10 = _mm256_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); - __m256i iacc_mat_11 = _mm256_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); - - // Straighten out to make 4 row vectors - __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); - __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); - __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); - __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); - - // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes - const __m256 row_scale_f32 = GGML_F32Cx8_REPEAT_LOAD(a_ptrs[rp][b].d, loadMask); - - // Multiply with appropiate scales and accumulate - acc_rows[rp * 4] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); - acc_rows[rp * 4 + 1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); - acc_rows[rp * 4 + 2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); - acc_rows[rp * 4 + 3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); - } - } - - // Store the accumulated values - for (int i = 0; i < 16; i++) { - _mm256_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); - } - } - } - - // Take a block_q8_0x4 structures at each pass of the loop and perform dot product operation - for (; y < nr / 4; y ++) { - - const block_q8_0x4 * a_ptr = a_ptr_start + (y * nb); - - // Load the eight block_q4_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 - for (int64_t x = xstart; x < nc / 8; x++) { - - const block_q4_0x8 * b_ptr = b_ptr_start + (x * b_nb); - - // Master FP accumulators - __m256 acc_rows[4]; - for (int i = 0; i < 4; i++) { - acc_rows[i] = _mm256_setzero_ps(); - } - - for (int64_t b = 0; b < nb; b++) { - // Load the eight block_q8_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 - const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs)); - const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32)); - const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64)); - const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96)); - - // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of valuess - const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); - const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); - - // 4-bit -> 8-bit - Sign is maintained - const __m256i rhs_mat_0145_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_0, m4b)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) - const __m256i rhs_mat_2367_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_0, m4b)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) - - const __m256i rhs_mat_0145_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_1, m4b)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) - const __m256i rhs_mat_2367_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_1, m4b)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) - - const __m256i rhs_mat_0145_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m4b)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) - const __m256i rhs_mat_2367_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m4b)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) - - const __m256i rhs_mat_0145_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m4b)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) - const __m256i rhs_mat_2367_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m4b)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) - - // Shuffle pattern one - right side input - const __m256i rhs_mat_0145_0_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_0, 136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) - const __m256i rhs_mat_2367_0_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_0, 136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) - - const __m256i rhs_mat_0145_1_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_1, 136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) - const __m256i rhs_mat_2367_1_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_1, 136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) - - const __m256i rhs_mat_0145_2_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_2, 136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) - const __m256i rhs_mat_2367_2_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_2, 136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) - - const __m256i rhs_mat_0145_3_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_3, 136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) - const __m256i rhs_mat_2367_3_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_3, 136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) - - // Shuffle pattern two - right side input - - const __m256i rhs_mat_0145_0_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_0, 221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) - const __m256i rhs_mat_2367_0_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_0, 221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) - - const __m256i rhs_mat_0145_1_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_1, 221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) - const __m256i rhs_mat_2367_1_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_1, 221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) - - const __m256i rhs_mat_0145_2_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_2, 221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) - const __m256i rhs_mat_2367_2_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_2, 221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) - - const __m256i rhs_mat_0145_3_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_3, 221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) - const __m256i rhs_mat_2367_3_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_3, 221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) - - // Scale values - Load the wight scale values of block_q4_0x8 - const __m256 col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); - - // Load the four block_q4_0 quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 - // Loaded as set of 128 bit vectors and repeated into a 256 bit vector - __m256i lhs_mat_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs))); - __m256i lhs_mat_01_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 0); - __m256i lhs_mat_23_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 17); - __m256i lhs_mat_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 32))); - __m256i lhs_mat_01_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 0); - __m256i lhs_mat_23_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 17); - __m256i lhs_mat_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 64))); - __m256i lhs_mat_01_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 0); - __m256i lhs_mat_23_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 17); - __m256i lhs_mat_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 96))); - __m256i lhs_mat_01_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 0); - __m256i lhs_mat_23_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 17); - - // Shuffle pattern one - left side input - - const __m256i lhs_mat_01_0_sp1 = _mm256_shuffle_epi32(lhs_mat_01_0, 160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) - const __m256i lhs_mat_23_0_sp1 = _mm256_shuffle_epi32(lhs_mat_23_0, 160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) - - const __m256i lhs_mat_01_1_sp1 = _mm256_shuffle_epi32(lhs_mat_01_1, 160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) - const __m256i lhs_mat_23_1_sp1 = _mm256_shuffle_epi32(lhs_mat_23_1, 160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) - - const __m256i lhs_mat_01_2_sp1 = _mm256_shuffle_epi32(lhs_mat_01_2, 160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) - const __m256i lhs_mat_23_2_sp1 = _mm256_shuffle_epi32(lhs_mat_23_2, 160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) - - const __m256i lhs_mat_01_3_sp1 = _mm256_shuffle_epi32(lhs_mat_01_3, 160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) - const __m256i lhs_mat_23_3_sp1 = _mm256_shuffle_epi32(lhs_mat_23_3, 160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) - - // Shuffle pattern two - left side input - - const __m256i lhs_mat_01_0_sp2 = _mm256_shuffle_epi32(lhs_mat_01_0, 245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) - const __m256i lhs_mat_23_0_sp2 = _mm256_shuffle_epi32(lhs_mat_23_0, 245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) - - const __m256i lhs_mat_01_1_sp2 = _mm256_shuffle_epi32(lhs_mat_01_1, 245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) - const __m256i lhs_mat_23_1_sp2 = _mm256_shuffle_epi32(lhs_mat_23_1, 245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) - - const __m256i lhs_mat_01_2_sp2 = _mm256_shuffle_epi32(lhs_mat_01_2, 245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) - const __m256i lhs_mat_23_2_sp2 = _mm256_shuffle_epi32(lhs_mat_23_2, 245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) - - const __m256i lhs_mat_01_3_sp2 = _mm256_shuffle_epi32(lhs_mat_01_3, 245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) - const __m256i lhs_mat_23_3_sp2 = _mm256_shuffle_epi32(lhs_mat_23_3, 245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) - - // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane - // Resembles MMLAs into 2x2 matrices in ARM Version - const __m256i zero = _mm256_setzero_si256(); - __m256i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_01_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_01_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_01_0_sp1, rhs_mat_0145_0_sp1); - __m256i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367_0_sp1); - __m256i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_23_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_23_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_23_0_sp1, rhs_mat_0145_0_sp1); - __m256i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367_0_sp1); - __m256i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_01_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_01_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_01_0_sp2, rhs_mat_0145_0_sp2); - __m256i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367_0_sp2); - __m256i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_23_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_23_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_23_0_sp2, rhs_mat_0145_0_sp2); - __m256i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367_0_sp2); - - // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block - __m256i iacc_mat_00 = _mm256_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); - __m256i iacc_mat_01 = _mm256_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); - __m256i iacc_mat_10 = _mm256_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); - __m256i iacc_mat_11 = _mm256_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); - - - // Straighten out to make 4 row vectors - __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); - __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); - __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); - __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); - - // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes - const __m256 row_scale_f32 = GGML_F32Cx8_REPEAT_LOAD(a_ptr[b].d, loadMask); - - // Multiply with appropiate scales and accumulate - acc_rows[0] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); - acc_rows[1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); - acc_rows[2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); - acc_rows[3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); - } - - // Store the accumulated values - for (int i = 0; i < 4; i++) { - _mm256_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); - } - } - } return; } +#endif // defined(__AVX2__) || defined(__AVX512F__) -#endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) - float sumf[4][8]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])) >> 4; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } + ggml_gemm_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_q4_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -3216,70 +3401,2907 @@ void ggml_gemm_q4_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const vo } #else + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + ggml_gemm_q4_K_8x8_q8_K_generic(n, s, bs, vx, vy, nr, nc); +#endif +} - float sumf[4][8]; - float sum_minf[4][8]; - uint32_t utmp[32]; - int sumi1; - int sumi2; - int sumi; +void ggml_gemm_iq4_nl_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { +#if defined(__AVX2__) || defined(__AVX512F__) + { + __m256i signextendlut = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i*)kvalues_iq4nl)); + signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); - for (int y = 0; y < nr / 4; y++) { - const block_q8_Kx4 * a_ptr = (const block_q8_Kx4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_Kx8 * b_ptr = (const block_q4_Kx8 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumf[m][j] = 0.0; - sum_minf[m][j] = 0.0; - } + gemm_q4_b32_8x8_q8_0_lut_avx(n, s, bs, vx, vy, nr, nc, signextendlut); + + return; + } +#endif // defined(__AVX2__) || defined(__AVX512F__) + + ggml_gemm_iq4_nl_4x4_q8_0(n, s, bs, vx, vy, nr, nc); +} + +void ggml_gemm_q2_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK_K; + const int nb = n / qk; + const int ncols_interleaved = 8; + const int blocklen = 8; + + assert (n % qk == 0); + assert (nr % 4 == 0); + assert (nc % ncols_interleaved == 0); + + UNUSED(s); + UNUSED(bs); + UNUSED(vx); + UNUSED(vy); + UNUSED(nr); + UNUSED(nc); + UNUSED(nb); + UNUSED(ncols_interleaved); + UNUSED(blocklen); + +#if defined(__AVX2__) || defined(__AVX512F__) + const block_q2_Kx8 * b_ptr_start = (const block_q2_Kx8 * ) vx; + const block_q8_Kx4 * a_ptr_start = (const block_q8_Kx4 * ) vy; + int64_t b_nb = n / QK_K; + int64_t y = 0; + + // Permute mask used for easier vector processing at later stages + __m256i requiredOrder = _mm256_set_epi32(3, 2, 1, 0, 7, 6, 5, 4); + int64_t xstart = 0; + int anr = nr - nr % 16; // Used to align nr with boundary of 16 + + // Mask to convert 2 bit and 4 bit values into a bytes + const __m256i m3b = _mm256_set1_epi8(3); + const __m128i m4b_sse = _mm_set1_epi8(0xF); + + //Mask to get appropriate scales + __m128i scalesmask1_sse = _mm_set_epi8(14,14,12,12,10,10,8,8,6,6,4,4,2,2,0,0); + __m128i scalesmask2_sse = _mm_set_epi8(15,15,13,13,11,11,9,9,7,7,5,5,3,3,1,1); + + __m256i scalesmask1 = _mm256_castsi128_si256(scalesmask1_sse); + scalesmask1 = _mm256_permute2f128_si256(scalesmask1, scalesmask1, 0); + __m256i scalesmask2 = _mm256_castsi128_si256(scalesmask2_sse); + scalesmask2 = _mm256_permute2f128_si256(scalesmask2, scalesmask2, 0); + +#ifdef __AVX512F__ + + int anc = nc - nc % 16; // Used to align nc with boundary of 16 + + // Mask to mask out nibbles from packed bytes + const __m256i m4b = _mm256_set1_epi8(0x0F); + // Mask to mask out nibbles from packed bytes expanded to 512 bit length + const __m512i m3bexpanded = _mm512_set1_epi8(3); + //Take group of four block_q8_Kx4 structures at each pass of the loop and perform dot product operation + for (; y < anr / 4; y += 4) { + + const block_q8_Kx4 * a_ptrs[4]; + + a_ptrs[0] = a_ptr_start + (y * nb); + for (int i = 0; i < 3; ++i) { + a_ptrs[i + 1] = a_ptrs[i] + nb; + } + + // Take group of eight block_q2_kx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = 0; x < anc / 8; x += 2) { + + const block_q2_Kx8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); + const block_q2_Kx8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); + + // Master FP accumulators + __m512 acc_rows[16]; + for (int i = 0; i < 16; i++) { + acc_rows[i] = _mm512_setzero_ps(); } - for (int l = 0; l < nb; l++) { - for (int sb = 0; sb < 8; sb++) { - memcpy(utmp + sb * 4, b_ptr[l].scales + sb * 12, 12); - utmp[sb * 4 + 3] = ((utmp[sb * 4 + 2] >> 4) & kmask2) | (((utmp[sb * 4 + 1] >> 6) & kmask3) << 4); - const uint32_t uaux_0 = utmp[sb * 4 + 1] & kmask1; - utmp[sb * 4 + 1] = (utmp[sb * 4 + 2] & kmask2) | (((utmp[sb * 4 + 0] >> 6) & kmask3) << 4); - utmp[sb * 4 + 2] = uaux_0; - utmp[sb * 4 + 0] &= kmask1; - } - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - uint8_t *scales_0 = (uint8_t*) utmp + (k / 4) * 32; - uint8_t *scales_1 = (uint8_t*) utmp + (k / 4) * 32 + 16; - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi1 = 0; - sumi2 = 0; - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4); - sumi1 = (v0 * a_ptr[l].qs[(k >> 2) * 256 + (k % 4) * 4 * blocklen + m * blocklen + i]); - sumi2 = (v1 * a_ptr[l].qs[(k >> 2) * 256 + (k % 4) * 4 * blocklen + m * blocklen + i + 128]); - sumi1 = sumi1 * scales_0[j]; - sumi2 = sumi2 * scales_1[j]; - sumi += sumi1 + sumi2; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * a_ptr[l].d[m]; - } - } - } - for (int sb = 0; sb < 8; sb++) { - uint8_t *mins = (uint8_t*) utmp + 8 + sb * 16; - for(int m = 0; m < 4; m++) { - const int16_t *bsums = a_ptr[l].bsums + (sb * 8) + (m * 4) - ((sb % 2) * 6); - for(int j = 0; j < ncols_interleaved; j++) { - sum_minf[m][j] += mins[j] * (bsums[0] + bsums[1]) * GGML_CPU_FP16_TO_FP32(b_ptr[l].dmin[j]) * a_ptr[l].d[m]; - } + + __m512 acc_min_rows[16]; + for (int i = 0; i < 16; i++) { + acc_min_rows[i] = _mm512_setzero_ps(); + } + // For super block + for (int64_t b = 0; b < nb; b++) { + // Delta values - Load the sixteen scale values from two block_q2_kx8 structures + const __m512 col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); + + // dmin values - Load the sixteen dmin values from two block_q2_kx8 structures + const __m512 col_dmin_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].dmin, b_ptr_1[b].dmin); + + // Loop to iterate over the sixteen sub blocks of a super block - eight sub blocks are processed per iteration + for (int sb = 0; sb < QK_K / 128; sb++) { + + // Load the eight block_q2_k for eight sub blocks quantized values interleaved with each other in chunks of eight bytes - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + sb * 256)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_0123_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_4567_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_0123_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_4567_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 224 + sb * 256)); + + const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + sb * 256)); + const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_89AB_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_89AB_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 224 + sb * 256)); + + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + const __m256i rhs_raw_mat_0145_2 = _mm256_blend_epi32(rhs_raw_mat_0123_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_2, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_2, requiredOrder), rhs_raw_mat_4567_2, 240); + const __m256i rhs_raw_mat_0145_3 = _mm256_blend_epi32(rhs_raw_mat_0123_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_3, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_3, requiredOrder), rhs_raw_mat_4567_3, 240); + + const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); + const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); + const __m256i rhs_raw_mat_89CD_2 = _mm256_blend_epi32(rhs_raw_mat_89AB_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_2, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_2, requiredOrder), rhs_raw_mat_CDEF_2, 240); + const __m256i rhs_raw_mat_89CD_3 = _mm256_blend_epi32(rhs_raw_mat_89AB_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_3, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_3, requiredOrder), rhs_raw_mat_CDEF_3, 240); + + const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); + const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); + const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); + const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); + + const __m512i rhs_raw_mat_014589CD_2 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_2), rhs_raw_mat_89CD_2, 1); + const __m512i rhs_raw_mat_2367ABEF_2 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_2), rhs_raw_mat_ABEF_2, 1); + const __m512i rhs_raw_mat_014589CD_3 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_3), rhs_raw_mat_89CD_3, 1); + const __m512i rhs_raw_mat_2367ABEF_3 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_3), rhs_raw_mat_ABEF_3, 1); + + //2-bit -> 8-bit + const __m512i rhs_mat_014589CD_00 = _mm512_and_si512(rhs_raw_mat_014589CD_0,m3bexpanded); //B00(0-7) B01(0-7) B04(0-7) B05(0-7) B08(0-7) B09(0-7) B0C(0-7) B0D(0-7) + const __m512i rhs_mat_2367ABEF_00 = _mm512_and_si512(rhs_raw_mat_2367ABEF_0,m3bexpanded); //B02(0-7) B03(0-7) B06(0-7) B07(0-7) B0A(0-7) B0B(0-7) B0E(0-7) B0F(0-7) + const __m512i rhs_mat_014589CD_01 = _mm512_and_si512(rhs_raw_mat_014589CD_1,m3bexpanded); //B00(8-15) B01(8-15) B04(8-15) B05(8-15) B08(8-15) B09(8-15) B0C(8-15) B0D(8-15) + const __m512i rhs_mat_2367ABEF_01 = _mm512_and_si512(rhs_raw_mat_2367ABEF_1,m3bexpanded); //B02(8-15) B03(8-15) B06(8-15) B07(8-15) B0A(8-15) B0B(8-15) B0E(8-15) B0F(8-15) + const __m512i rhs_mat_014589CD_10 = _mm512_and_si512(rhs_raw_mat_014589CD_2,m3bexpanded); //B10(0-7) B11(0-7) B14(0-7) B15(0-7) B18(0-7) B19(0-7) B1C(0-7) B1D(0-7) + const __m512i rhs_mat_2367ABEF_10 = _mm512_and_si512(rhs_raw_mat_2367ABEF_2,m3bexpanded); //B12(0-7) B13(0-7) B16(0-7) B17(0-7) B1A(0-7) B1B(0-7) B1E(0-7) B1F(0-7) + const __m512i rhs_mat_014589CD_11 = _mm512_and_si512(rhs_raw_mat_014589CD_3,m3bexpanded); //B10(8-15) B11(8-15) B14(8-15) B15(8-15) B18(8-15) B19(8-15) B1C(8-15) B1D(8-15) + const __m512i rhs_mat_2367ABEF_11 = _mm512_and_si512(rhs_raw_mat_2367ABEF_3,m3bexpanded); //B12(8-15) B13(8-15) B16(8-15) B17(8-15) B1A(8-15) B1B(8-15) B1E(8-15) B1F(8-15) + + const __m512i rhs_mat_014589CD_20 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 2), m3bexpanded); //B20(0-7) B21(0-7) B24(0-7) B25(0-7) B28(0-7) B29(0-7) B2C(0-7) B2D(0-7) + const __m512i rhs_mat_2367ABEF_20 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 2), m3bexpanded); //B22(0-7) B23(0-7) B26(0-7) B27(0-7) B2A(0-7) B2B(0-7) B2E(0-7) B2F(0-7) + + const __m512i rhs_mat_014589CD_21 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 2), m3bexpanded); //B20(8-15) B21(8-15) B24(8-15) B25(8-15) B28(8-15) B29(8-15) B2C(8-15) B2D(8-15) + const __m512i rhs_mat_2367ABEF_21 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 2), m3bexpanded); //B22(8-15) B23(8-15) B26(8-15) B27(8-15) B2A(8-15) B2B(8-15) B2E(8-15) B2F(8-15) + + const __m512i rhs_mat_014589CD_30 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 2), m3bexpanded); //B30(0-7) B31(0-7) B34(0-7) B35(0-7) B38(0-7) B39(0-7) B3C(0-7) B3D(0-7) + const __m512i rhs_mat_2367ABEF_30 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 2), m3bexpanded); //B32(0-7) B33(0-7) B36(0-7) B37(0-7) B3A(0-7) B3B(0-7) B3E(0-7) B3F(0-7) + + const __m512i rhs_mat_014589CD_31 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 2), m3bexpanded); //B30(8-15) B31(8-15) B34(8-15) B35(8-15) B38(8-15) B39(8-15) B3C(8-15) B3D(8-15) + const __m512i rhs_mat_2367ABEF_31 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 2), m3bexpanded); //B32(8-15) B33(8-15) B36(8-15) B37(8-15) B3A(8-15) B3B(8-15) B3E(8-15) B3F(8-15) + + const __m512i rhs_mat_014589CD_40 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m3bexpanded); //B40(0-7) B41(0-7) B44(0-7) B45(0-7) B48(0-7) B49(0-7) B4C(0-7) B4D(0-7) + const __m512i rhs_mat_2367ABEF_40 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m3bexpanded); //B42(0-7) B43(0-7) B46(0-7) B47(0-7) B4A(0-7) B4B(0-7) B4E(0-7) B4F(0-7) + + const __m512i rhs_mat_014589CD_41 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m3bexpanded); //B40(8-15) B41(8-15) B44(8-15) B45(8-15) B48(8-15) B49(8-15) B4C(8-15) B4D(8-15) + const __m512i rhs_mat_2367ABEF_41 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m3bexpanded); //B42(8-15) B43(8-15) B46(8-15) B47(8-15) B4A(8-15) B4B(8-15) B4E(8-15) B4F(8-15) + + const __m512i rhs_mat_014589CD_50 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 4), m3bexpanded); //B50(0-7) B51(0-7) B54(0-7) B55(0-7) B58(0-7) B59(0-7) B5C(0-7) B5D(0-7) + const __m512i rhs_mat_2367ABEF_50 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 4), m3bexpanded); //B52(0-7) B53(0-7) B56(0-7) B57(0-7) B5A(0-7) B5B(0-7) B5E(0-7) B5F(0-7) + + const __m512i rhs_mat_014589CD_51 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 4), m3bexpanded); //B50(8-15) B51(8-15) B54(8-15) B55(8-15) B58(8-15) B59(8-15) B5C(8-15) B5D(8-15) + const __m512i rhs_mat_2367ABEF_51 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 4), m3bexpanded); //B52(8-15) B53(8-15) B56(8-15) B57(8-15) B5A(8-15) B5B(8-15) B5E(8-15) B5F(8-15) + + const __m512i rhs_mat_014589CD_60 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 6), m3bexpanded); //B60(0-7) B61(0-7) B64(0-7) B65(0-7) B68(0-7) B69(0-7) B6C(0-7) B6D(0-7) + const __m512i rhs_mat_2367ABEF_60 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 6), m3bexpanded); //B62(0-7) B63(0-7) B66(0-7) B67(0-7) B6A(0-7) B6B(0-7) B6E(0-7) B6F(0-7) + + const __m512i rhs_mat_014589CD_61 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 6), m3bexpanded); //B60(8-15) B61(8-15) B64(8-15) B65(8-15) B68(8-15) B69(8-15) B6C(8-15) B6D(8-15) + const __m512i rhs_mat_2367ABEF_61 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 6), m3bexpanded); //B62(8-15) B63(8-15) B66(8-15) B67(8-15) B6A(8-15) B6B(8-15) B6E(8-15) B6F(8-15) + + const __m512i rhs_mat_014589CD_70 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 6), m3bexpanded); //B70(0-7) B71(0-7) B74(0-7) B75(0-7) B78(0-7) B79(0-7) B7C(0-7) B7D(0-7) + const __m512i rhs_mat_2367ABEF_70 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 6), m3bexpanded); //B72(0-7) B73(0-7) B76(0-7) B77(0-7) B7A(0-7) B7B(0-7) B7E(0-7) B7F(0-7) + + const __m512i rhs_mat_014589CD_71 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 6), m3bexpanded); //B70(8-15) B71(8-15) B74(8-15) B75(8-15) B78(8-15) B79(8-15) B7C(8-15) B7D(8-15) + const __m512i rhs_mat_2367ABEF_71 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 6), m3bexpanded); //B72(8-15) B73(8-15) B76(8-15) B77(8-15) B7A(8-15) B7B(8-15) B7E(8-15) B7F(8-15) + + const __m512i rhs_mat_014589CD_00_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_00, (_MM_PERM_ENUM)136); //B00(0-3) B01(0-3) B00(0-3) B01(0-3) B04(0-3) B05(0-3) B04(0-3) B05(0-3) B08(0-3) B09(0-3) B08(0-3) B09(0-3) B0C(0-3) B0D(0-3) B0C(0-3) B0D(0-3) + const __m512i rhs_mat_2367ABEF_00_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_00, (_MM_PERM_ENUM)136); //B02(0-3) B03(0-3) B02(0-3) B03(0-3) B06(0-3) B07(0-3) B06(0-3) B07(0-3) B0A(0-3) B0B(0-3) B0A(0-3) B0B(0-3) B0E(0-3) B0F(0-3) B0E(0-3) B0F(0-3) + + const __m512i rhs_mat_014589CD_01_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_01, (_MM_PERM_ENUM)136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) B08(8-11) B09(8-11) B08(8-11) B09(8-11) B0C(8-11) B0D(8-11) B0C(8-11) B0D(8-11) + const __m512i rhs_mat_2367ABEF_01_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_01, (_MM_PERM_ENUM)136); //B02(8-11) B03(8-11) B02(8-11) B03(8-11) B06(8-11) B07(8-11) B06(8-11) B07(8-11) B0A(8-11) B0B(8-11) B0A(8-11) B0B(8-11) B0E(8-11) B0F(8-11) B0E(8-11) B0F(8-11) + + const __m512i rhs_mat_014589CD_10_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_10, (_MM_PERM_ENUM)136); //B10(0-3) B11(0-3) B10(0-3) B11(0-3) B14(0-3) B15(0-3) B14(0-3) B15(0-3) B18(0-3) B19(0-3) B18(0-3) B19(0-3) B1C(0-3) B1D(0-3) B1C(0-3) B1D(0-3) + const __m512i rhs_mat_2367ABEF_10_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_10, (_MM_PERM_ENUM)136); //B12(0-3) B13(0-3) B12(0-3) B13(0-3) B16(0-3) B17(0-3) B16(0-3) B17(0-3) B1A(0-3) B1B(0-3) B1A(0-3) B1B(0-3) B1E(0-3) B1F(0-3) B1E(0-3) B1F(0-3) + + const __m512i rhs_mat_014589CD_11_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_11, (_MM_PERM_ENUM)136); //B10(8-11) B11(8-11) B10(8-11) B11(8-11) B14(8-11) B15(8-11) B14(8-11) B15(8-11) B18(8-11) B19(8-11) B18(8-11) B19(8-11) B1C(8-11) B1D(8-11) B1C(8-11) B1D(8-11) + const __m512i rhs_mat_2367ABEF_11_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_11, (_MM_PERM_ENUM)136); //B12(8-11) B13(8-11) B12(8-11) B13(8-11) B16(8-11) B17(8-11) B16(8-11) B17(8-11) B1A(8-11) B1B(8-11) B1A(8-11) B1B(8-11) B1E(8-11) B1F(8-11) B1E(8-11) B1F(8-11) + + const __m512i rhs_mat_014589CD_20_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_20, (_MM_PERM_ENUM)136); //B20(0-3) B21(0-3) B20(0-3) B21(0-3) B24(0-3) B25(0-3) B24(0-3) B25(0-3) B28(0-3) B29(0-3) B28(0-3) B29(0-3) B2C(0-3) B2D(0-3) B2C(0-3) B2D(0-3) + const __m512i rhs_mat_2367ABEF_20_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_20, (_MM_PERM_ENUM)136); //B22(0-3) B23(0-3) B22(0-3) B23(0-3) B26(0-3) B27(0-3) B26(0-3) B27(0-3) B2A(0-3) B2B(0-3) B2A(0-3) B2B(0-3) B2E(0-3) B2F(0-3) B2E(0-3) B2F(0-3) + + const __m512i rhs_mat_014589CD_21_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_21, (_MM_PERM_ENUM)136); //B20(8-11) B21(8-11) B20(8-11) B21(8-11) B24(8-11) B25(8-11) B24(8-11) B25(8-11) B28(8-11) B29(8-11) B28(8-11) B29(8-11) B2C(8-11) B2D(8-11) B2C(8-11) B2D(8-11) + const __m512i rhs_mat_2367ABEF_21_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_21, (_MM_PERM_ENUM)136); //B22(8-11) B23(8-11) B22(8-11) B23(8-11) B26(8-11) B27(8-11) B26(8-11) B27(8-11) B2A(8-11) B2B(8-11) B2A(8-11) B2B(8-11) B2E(8-11) B2F(8-11) B2E(8-11) B2F(8-11) + + const __m512i rhs_mat_014589CD_30_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_30, (_MM_PERM_ENUM)136); ///B30(0-3) B31(0-3) B30(0-3) B31(0-3) B34(0-3) B35(0-3) B34(0-3) B35(0-3) B38(0-3) B39(0-3) B38(0-3) B39(0-3) B3C(0-3) B3D(0-3) B3C(0-3) B3D(0-3) + const __m512i rhs_mat_2367ABEF_30_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_30, (_MM_PERM_ENUM)136); //B32(0-3) B33(0-3) B32(0-3) B33(0-3) B36(0-3) B37(0-3) B36(0-3) B37(0-3) B3A(0-3) B3B(0-3) B3A(0-3) B3B(0-3) B3E(0-3) B3F(0-3) B3E(0-3) B3F(0-3) + + const __m512i rhs_mat_014589CD_31_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_31, (_MM_PERM_ENUM)136); //B30(8-11) B31(8-11) B30(8-11) B31(8-11) B34(8-11) B35(8-11) B34(8-11) B35(8-11) B38(8-11) B39(8-11) B38(8-11) B39(8-11) B3C(8-11) B3D(8-11) B3C(8-11) B3D(8-11) + const __m512i rhs_mat_2367ABEF_31_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_31, (_MM_PERM_ENUM)136); //B32(8-11) B33(8-11) B32(8-11) B33(8-11) B36(8-11) B37(8-11) B36(8-11) B37(8-11) B3A(8-11) B3B(8-11) B3A(8-11) B3B(8-11) B3E(8-11) B3F(8-11) B3E(8-11) B3F(8-11) + + const __m512i rhs_mat_014589CD_40_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_40, (_MM_PERM_ENUM)136); //B40(0-3) B41(0-3) B40(0-3) B41(0-3) B44(0-3) B45(0-3) B44(0-3) B45(0-3) B48(0-3) B49(0-3) B48(0-3) B49(0-3) B4C(0-3) B4D(0-3) B4C(0-3) B4D(0-3) + const __m512i rhs_mat_2367ABEF_40_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_40, (_MM_PERM_ENUM)136); //B42(0-3) B43(0-3) B42(0-3) B43(0-3) B46(0-3) B47(0-3) B46(0-3) B47(0-3) B4A(0-3) B4B(0-3) B4A(0-3) B4B(0-3) B4E(0-3) B4F(0-3) B4E(0-3) B4F(0-3) + + const __m512i rhs_mat_014589CD_41_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_41, (_MM_PERM_ENUM)136); //B40(8-11) B41(8-11) B40(8-11) B41(8-11) B44(8-11) B45(8-11) B44(8-11) B45(8-11) B48(8-11) B49(8-11) B48(8-11) B49(8-11) B4C(8-11) B4D(8-11) B4C(8-11) B4D(8-11) + const __m512i rhs_mat_2367ABEF_41_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_41, (_MM_PERM_ENUM)136); //B42(8-11) B43(8-11) B42(8-11) B43(8-11) B46(8-11) B47(8-11) B46(8-11) B47(8-11) B4A(8-11) B4B(8-11) B4A(8-11) B4B(8-11) B4E(8-11) B4F(8-11) B4E(8-11) B4F(8-11) + + const __m512i rhs_mat_014589CD_50_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_50, (_MM_PERM_ENUM)136); //B50(0-3) B51(0-3) B50(0-3) B51(0-3) B54(0-3) B55(0-3) B54(0-3) B55(0-3) B58(0-3) B59(0-3) B58(0-3) B59(0-3) B5C(0-3) B5D(0-3) B5C(0-3) B5D(0-3) + const __m512i rhs_mat_2367ABEF_50_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_50, (_MM_PERM_ENUM)136); //B52(0-3) B53(0-3) B52(0-3) B53(0-3) B56(0-3) B57(0-3) B56(0-3) B57(0-3) B5A(0-3) B5B(0-3) B5A(0-3) B5B(0-3) B5E(0-3) B5F(0-3) B5E(0-3) B5F(0-3) + + const __m512i rhs_mat_014589CD_51_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_51, (_MM_PERM_ENUM)136); //B50(8-11) B51(8-11) B50(8-11) B51(8-11) B54(8-11) B55(8-11) B54(8-11) B55(8-11) B58(8-11) B59(8-11) B58(8-11) B59(8-11) B5C(8-11) B5D(8-11) B5C(8-11) B5D(8-11) + const __m512i rhs_mat_2367ABEF_51_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_51, (_MM_PERM_ENUM)136); //B52(8-11) B53(8-11) B52(8-11) B53(8-11) B56(8-11) B57(8-11) B56(8-11) B57(8-11) B5A(8-11) B5B(8-11) B5A(8-11) B5B(8-11) B5E(8-11) B5F(8-11) B5E(8-11) B5F(8-11) + + const __m512i rhs_mat_014589CD_60_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_60, (_MM_PERM_ENUM)136); //B60(0-3) B61(0-3) B60(0-3) B61(0-3) B64(0-3) B65(0-3) B64(0-3) B65(0-3) B68(0-3) B69(0-3) B68(0-3) B69(0-3) B6C(0-3) B6D(0-3) B6C(0-3) B6D(0-3) + const __m512i rhs_mat_2367ABEF_60_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_60, (_MM_PERM_ENUM)136); //B62(0-3) B63(0-3) B62(0-3) B63(0-3) B66(0-3) B67(0-3) B66(0-3) B67(0-3) B6A(0-3) B6B(0-3) B6A(0-3) B6B(0-3) B6E(0-3) B6F(0-3) B6E(0-3) B6F(0-3) + + const __m512i rhs_mat_014589CD_61_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_61, (_MM_PERM_ENUM)136); //B60(8-11) B61(8-11) B60(8-11) B61(8-11) B64(8-11) B65(8-11) B64(8-11) B65(8-11) B68(8-11) B69(8-11) B68(8-11) B69(8-11) B6C(8-11) B6D(8-11) B6C(8-11) B6D(8-11) + const __m512i rhs_mat_2367ABEF_61_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_61, (_MM_PERM_ENUM)136); //B62(8-11) B63(8-11) B62(8-11) B63(8-11) B66(8-11) B67(8-11) B66(8-11) B67(8-11) B6A(8-11) B6B(8-11) B6A(8-11) B6B(8-11) B6E(8-11) B6F(8-11) B6E(8-11) B6F(8-11) + + const __m512i rhs_mat_014589CD_70_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_70, (_MM_PERM_ENUM)136); //B70(0-3) B71(0-3) B70(0-3) B71(0-3) B74(0-3) B75(0-3) B74(0-3) B75(0-3) B78(0-3) B79(0-3) B78(0-3) B79(0-3) B7C(0-3) B7D(0-3) B7C(0-3) B7D(0-3) + const __m512i rhs_mat_2367ABEF_70_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_70, (_MM_PERM_ENUM)136); //B72(0-3) B73(0-3) B72(0-3) B73(0-3) B76(0-3) B77(0-3) B76(0-3) B77(0-3) B7A(0-3) B7B(0-3) B7A(0-3) B7B(0-3) B7E(0-3) B7F(0-3) B7E(0-3) B7F(0-3) + + const __m512i rhs_mat_014589CD_71_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_71, (_MM_PERM_ENUM)136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) B08(8-11) B09(8-11) B08(8-11) B09(8-11) B0C(8-11) B0D(8-11) B0C(8-11) B0D(8-11) + const __m512i rhs_mat_2367ABEF_71_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_71, (_MM_PERM_ENUM)136); //B72(8-11) B73(8-11) B72(8-11) B73(8-11) B76(8-11) B77(8-11) B76(8-11) B77(8-11) B7A(8-11) B7B(8-11) B7A(8-11) B7B(8-11) B7E(8-11) B7F(8-11) B7E(8-11) B7F(8-11) + + const __m512i rhs_mat_014589CD_00_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_00, (_MM_PERM_ENUM)221); //B00(4-7) B01(4-7) B00(4-7) B01(4-7) B04(4-7) B05(4-7) B04(4-7) B05(4-7) B08(4-7) B09(4-7) B08(4-7) B09(4-7) B0C(4-7) B0D(4-7) B0C(4-7) B0D(4-7) + const __m512i rhs_mat_2367ABEF_00_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_00, (_MM_PERM_ENUM)221); //B02(4-7) B03(4-7) B02(4-7) B03(4-7) B06(4-7) B07(4-7) B06(4-7) B07(4-7) B0A(4-7) B0B(4-7) B0A(4-7) B0B(4-7) B0E(4-7) B0F(4-7) B0E(4-7) B0F(4-7) + + const __m512i rhs_mat_014589CD_01_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_01, (_MM_PERM_ENUM)221); //B00(12-15) B01(12-15) B00(12-15) B01(12-15) B04(12-15) B05(12-15) B04(12-15) B05(12-15) B08(12-15) B09(12-15) B08(12-15) B09(12-15) B0C(12-15) B0D(12-15) B0C(12-15) B0D(12-15) + const __m512i rhs_mat_2367ABEF_01_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_01, (_MM_PERM_ENUM)221); //B02(12-15) B03(12-15) B02(12-15) B03(12-15) B06(12-15) B07(12-15) B06(12-15) B07(12-15) B0A(12-15) B0B(12-15) B0A(12-15) B0B(12-15) B0E(12-15) B0F(12-15) B0E(12-15) B0F(12-15) + + const __m512i rhs_mat_014589CD_10_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_10, (_MM_PERM_ENUM)221); //B10(4-7) B11(4-7) B10(4-7) B11(4-7) B14(4-7) B15(4-7) B14(4-7) B15(4-7) B18(4-7) B19(4-7) B18(4-7) B19(4-7) B1C(4-7) B1D(4-7) B1C(4-7) B1D(4-7) + const __m512i rhs_mat_2367ABEF_10_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_10, (_MM_PERM_ENUM)221); //B12(4-7) B13(4-7) B12(4-7) B13(4-7) B16(4-7) B17(4-7) B16(4-7) B17(4-7) B1A(4-7) B1B(4-7) B1A(4-7) B1B(4-7) B1E(4-7) B1F(4-7) B1E(4-7) B1F(4-7) + + const __m512i rhs_mat_014589CD_11_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_11, (_MM_PERM_ENUM)221); //B10(12-15) B11(12-15) B10(12-15) B11(12-15) B14(12-15) B15(12-15) B14(12-15) B15(12-15) B18(12-15) B19(12-15) B18(12-15) B19(12-15) B1C(12-15) B1D(12-15) B1C(12-15) B1D(12-15) + const __m512i rhs_mat_2367ABEF_11_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_11, (_MM_PERM_ENUM)221); //B12(12-15) B13(12-15) B12(12-15) B13(12-15) B16(12-15) B17(12-15) B16(12-15) B17(12-15) B1A(12-15) B1B(12-15) B1A(12-15) B1B(12-15) B1E(12-15) B1F(12-15) B1E(12-15) B1F(12-15) + + const __m512i rhs_mat_014589CD_20_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_20, (_MM_PERM_ENUM)221); //B20(4-7) B21(4-7) B20(4-7) B21(4-7) B24(4-7) B25(4-7) B24(4-7) B25(4-7) B28(4-7) B29(4-7) B28(4-7) B29(4-7) B2C(4-7) B2D(4-7) B2C(4-7) B2D(4-7) + const __m512i rhs_mat_2367ABEF_20_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_20, (_MM_PERM_ENUM)221); //B22(4-7) B23(4-7) B22(4-7) B23(4-7) B26(4-7) B27(4-7) B26(4-7) B27(4-7) B2A(4-7) B2B(4-7) B2A(4-7) B2B(4-7) B2E(4-7) B2F(4-7) B2E(4-7) B2F(4-7) + + const __m512i rhs_mat_014589CD_21_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_21, (_MM_PERM_ENUM)221); //B20(12-15) B21(12-15) B20(12-15) B21(12-15) B24(12-15) B25(12-15) B24(12-15) B25(12-15) B28(12-15) B29(12-15) B28(12-15) B29(12-15) B2C(12-15) B2D(12-15) B2C(12-15) B2D(12-15) + const __m512i rhs_mat_2367ABEF_21_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_21, (_MM_PERM_ENUM)221); //B22(12-15) B23(12-15) B22(12-15) B23(12-15) B26(12-15) B27(12-15) B26(12-15) B27(12-15) B2A(12-15) B2B(12-15) B2A(12-15) B2B(12-15) B2E(12-15) B2F(12-15) B2E(12-15) B2F(12-15) + + const __m512i rhs_mat_014589CD_30_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_30, (_MM_PERM_ENUM)221); //B30(4-7) B31(4-7) B30(4-7) B31(4-7) B34(4-7) B35(4-7) B34(4-7) B35(4-7) B38(4-7) B39(4-7) B38(4-7) B39(4-7) B3C(4-7) B3D(4-7) B3C(4-7) B3D(4-7) + const __m512i rhs_mat_2367ABEF_30_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_30, (_MM_PERM_ENUM)221); //B32(4-7) B33(4-7) B32(4-7) B33(4-7) B36(4-7) B37(4-7) B36(4-7) B37(4-7) B3A(4-7) B3B(4-7) B3A(4-7) B3B(4-7) B3E(4-7) B3F(4-7) B3E(4-7) B3F(4-7) + + const __m512i rhs_mat_014589CD_31_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_31, (_MM_PERM_ENUM)221); //B30(12-15) B31(12-15) B30(12-15) B31(12-15) B34(12-15) B35(12-15) B34(12-15) B35(12-15) B38(12-15) B39(12-15) B38(12-15) B39(12-15) B3C(12-15) B3D(12-15) B3C(12-15) B3D(12-15) + const __m512i rhs_mat_2367ABEF_31_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_31, (_MM_PERM_ENUM)221); //B32(12-15) B33(12-15) B32(12-15) B33(12-15) B36(12-15) B37(12-15) B36(12-15) B37(12-15) B3A(12-15) B3B(12-15) B3A(12-15) B3B(12-15) B3E(12-15) B3F(12-15) B3E(12-15) B3F(12-15) + + const __m512i rhs_mat_014589CD_40_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_40, (_MM_PERM_ENUM)221); //B40(4-7) B41(4-7) B40(4-7) B41(4-7) B44(4-7) B45(4-7) B44(4-7) B45(4-7) B48(4-7) B49(4-7) B48(4-7) B49(4-7) B4C(4-7) B4D(4-7) B4C(4-7) B4D(4-7) + const __m512i rhs_mat_2367ABEF_40_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_40, (_MM_PERM_ENUM)221); //B42(4-7) B43(4-7) B42(4-7) B43(4-7) B46(4-7) B47(4-7) B46(4-7) B47(4-7) B4A(4-7) B4B(4-7) B4A(4-7) B4B(4-7) B4E(4-7) B4F(4-7) B4E(4-7) B4F(4-7) + + const __m512i rhs_mat_014589CD_41_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_41, (_MM_PERM_ENUM)221); //B40(12-15) B41(12-15) B40(12-15) B41(12-15) B44(12-15) B45(12-15) B44(12-15) B45(12-15) B48(12-15) B49(12-15) B48(12-15) B49(12-15) B4C(12-15) B4D(12-15) B4C(12-15) B4D(12-15) + const __m512i rhs_mat_2367ABEF_41_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_41, (_MM_PERM_ENUM)221); //B42(12-15) B43(12-15) B42(12-15) B43(12-15) B46(12-15) B47(12-15) B46(12-15) B47(12-15) B4A(12-15) B4B(12-15) B4A(12-15) B4B(12-15) B4E(12-15) B4F(12-15) B4E(12-15) B4F(12-15) + + const __m512i rhs_mat_014589CD_50_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_50, (_MM_PERM_ENUM)221); //B50(4-7) B51(4-7) B50(4-7) B51(4-7) B54(4-7) B55(4-7) B54(4-7) B55(4-7) B58(4-7) B59(4-7) B58(4-7) B59(4-7) B5C(4-7) B5D(4-7) B5C(4-7) B5D(4-7) + const __m512i rhs_mat_2367ABEF_50_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_50, (_MM_PERM_ENUM)221); //B52(4-7) B53(4-7) B52(4-7) B53(4-7) B56(4-7) B57(4-7) B56(4-7) B57(4-7) B5A(4-7) B5B(4-7) B5A(4-7) B5B(4-7) B5E(4-7) B5F(4-7) B5E(4-7) B5F(4-7) + + const __m512i rhs_mat_014589CD_51_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_51, (_MM_PERM_ENUM)221); //B50(12-15) B51(12-15) B50(12-15) B51(12-15) B54(12-15) B55(12-15) B54(12-15) B55(12-15) B58(12-15) B59(12-15) B58(12-15) B59(12-15) B5C(12-15) B5D(12-15) B5C(12-15) B5D(12-15) + const __m512i rhs_mat_2367ABEF_51_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_51, (_MM_PERM_ENUM)221); //B52(12-15) B53(12-15) B52(12-15) B53(12-15) B56(12-15) B57(12-15) B56(12-15) B57(12-15) B5A(12-15) B5B(12-15) B5A(12-15) B5B(12-15) B5E(12-15) B5F(12-15) B5E(12-15) B5F(12-15) + + const __m512i rhs_mat_014589CD_60_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_60, (_MM_PERM_ENUM)221); //B60(4-7) B61(4-7) B60(4-7) B61(4-7) B64(4-7) B65(4-7) B64(4-7) B65(4-7) B68(4-7) B69(4-7) B68(4-7) B69(4-7) B6C(4-7) B6D(4-7) B6C(4-7) B6D(4-7) + const __m512i rhs_mat_2367ABEF_60_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_60, (_MM_PERM_ENUM)221); //B62(4-7) B63(4-7) B62(4-7) B63(4-7) B66(4-7) B67(4-7) B66(4-7) B67(4-7) B6A(4-7) B6B(4-7) B6A(4-7) B6B(4-7) B6E(4-7) B6F(4-7) B6E(4-7) B6F(4-7) + + const __m512i rhs_mat_014589CD_61_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_61, (_MM_PERM_ENUM)221); //B60(12-15) B61(12-15) B60(12-15) B61(12-15) B64(12-15) B65(12-15) B64(12-15) B65(12-15) B68(12-15) B69(12-15) B68(12-15) B69(12-15) B6C(12-15) B6D(12-15) B6C(12-15) B6D(12-15) + const __m512i rhs_mat_2367ABEF_61_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_61, (_MM_PERM_ENUM)221); //B62(12-15) B63(12-15) B62(12-15) B63(12-15) B66(12-15) B67(12-15) B66(12-15) B67(12-15) B6A(12-15) B6B(12-15) B6A(12-15) B6B(12-15) B6E(12-15) B6F(12-15) B6E(12-15) B6F(12-15) + + const __m512i rhs_mat_014589CD_70_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_70, (_MM_PERM_ENUM)221); //B70(4-7) B71(4-7) B70(4-7) B71(4-7) B74(4-7) B75(4-7) B74(4-7) B75(4-7) B78(4-7) B79(4-7) B78(4-7) B79(4-7) B7C(4-7) B7D(4-7) B7C(4-7) B7D(4-7) + const __m512i rhs_mat_2367ABEF_70_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_70, (_MM_PERM_ENUM)221); //B72(4-7) B73(4-7) B72(4-7) B73(4-7) B76(4-7) B77(4-7) B76(4-7) B77(4-7) B7A(4-7) B7B(4-7) B7A(4-7) B7B(4-7) B7E(4-7) B7F(4-7) B7E(4-7) B7F(4-7) + + const __m512i rhs_mat_014589CD_71_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_71, (_MM_PERM_ENUM)221); //B70(12-15) B71(12-15) B70(12-15) B71(12-15) B74(12-15) B75(12-15) B74(12-15) B75(12-15) B78(12-15) B79(12-15) B78(12-15) B79(12-15) B7C(12-15) B7D(12-15) B7C(12-15) B7D(12-15) + const __m512i rhs_mat_2367ABEF_71_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_71, (_MM_PERM_ENUM)221); //B72(12-15) B73(12-15) B72(12-15) B73(12-15) B76(12-15) B77(12-15) B76(12-15) B77(12-15) B7A(12-15) B7B(12-15) B7A(12-15) B7B(12-15) B7E(12-15) B7F(12-15) B7E(12-15) B7F(12-15) + + //notation:superblock subblock + //s00 m00 s01 m01 s10 m10 s11 m11 s20 m20 s21 m21 s30 m30 s31 m31 s40 m40 s41 m41 s50 m50 s51 m51 s60 m60 s61 m61 s70 m70 s71 m71 + + const __m128i mins_and_scales_01_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + sb * 64)); + const __m128i mins_and_scales_23_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 48 + sb * 64)); + + const __m128i mins_and_scales_01_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + sb * 64)); + const __m128i mins_and_scales_23_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 48 + sb * 64)); + + // Combine mins and scales for sub-blocks: 0-1, 2-3, 4-5, 6-7 in the sb loop + const __m256i mins_and_scales_01 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_01_0), mins_and_scales_01_1, 1); + const __m256i mins_and_scales_23 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_23_0), mins_and_scales_23_1, 1); + const __m256i mins_and_scales_45 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_45_0), mins_and_scales_45_1, 1); + const __m256i mins_and_scales_67 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_67_0), mins_and_scales_67_1, 1); + + // Extract scales which is lower half from mins_and_scales + const __m256i scales_01 = _mm256_and_si256(mins_and_scales_01, m4b); + const __m256i scales_23 = _mm256_and_si256(mins_and_scales_23, m4b); + const __m256i scales_45 = _mm256_and_si256(mins_and_scales_45, m4b); + const __m256i scales_67 = _mm256_and_si256(mins_and_scales_67, m4b); + + // Extract mins which is upper half from mins_and_scales + const __m512i mins_01 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_01, 4), m4b)); + const __m512i mins_23 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_23, 4), m4b)); + const __m512i mins_45 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_45, 4), m4b)); + const __m512i mins_67 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_67, 4), m4b)); + + const __m512i scales_0 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_01,scalesmask1)); + const __m512i scales_1 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_01,scalesmask2)); + const __m512i scales_2 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_23,scalesmask1)); + const __m512i scales_3 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_23,scalesmask2)); + const __m512i scales_4 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_45,scalesmask1)); + const __m512i scales_5 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_45,scalesmask2)); + const __m512i scales_6 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_67,scalesmask1)); + const __m512i scales_7 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_67,scalesmask2)); + + const __m512i scale_014589CD_0 = _mm512_shuffle_epi32(scales_0, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_0 = _mm512_shuffle_epi32(scales_0, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_1 = _mm512_shuffle_epi32(scales_1, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_1 = _mm512_shuffle_epi32(scales_1, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_2 = _mm512_shuffle_epi32(scales_2, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_2 = _mm512_shuffle_epi32(scales_2, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_3 = _mm512_shuffle_epi32(scales_3, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_3 = _mm512_shuffle_epi32(scales_3, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_4 = _mm512_shuffle_epi32(scales_4, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_4 = _mm512_shuffle_epi32(scales_4, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_5 = _mm512_shuffle_epi32(scales_5, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_5 = _mm512_shuffle_epi32(scales_5, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_6 = _mm512_shuffle_epi32(scales_6, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_6 = _mm512_shuffle_epi32(scales_6, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_7 = _mm512_shuffle_epi32(scales_7, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_7 = _mm512_shuffle_epi32(scales_7, (_MM_PERM_ENUM)238); + + + for (int rp = 0; rp < 4; rp++) { + + // Load the four block_q8_k quantized values interleaved with each other in chunks of eight bytes - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated and stored into a 256 bit vector before again repeating into 512 bit vector + __m256i lhs_mat_ymm_0123_00 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 512 * sb))); + __m256i lhs_mat_ymm_01_00 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_00, lhs_mat_ymm_0123_00, 0); + __m256i lhs_mat_ymm_23_00 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_00, lhs_mat_ymm_0123_00, 17); + __m256i lhs_mat_ymm_0123_01 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 32 + 512 * sb))); + __m256i lhs_mat_ymm_01_01 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_01, lhs_mat_ymm_0123_01, 0); + __m256i lhs_mat_ymm_23_01 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_01, lhs_mat_ymm_0123_01, 17); + __m256i lhs_mat_ymm_0123_10 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 64 + 512 * sb))); + __m256i lhs_mat_ymm_01_10 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_10, lhs_mat_ymm_0123_10, 0); + __m256i lhs_mat_ymm_23_10 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_10, lhs_mat_ymm_0123_10, 17); + __m256i lhs_mat_ymm_0123_11 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 96 + 512 * sb))); + __m256i lhs_mat_ymm_01_11 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_11, lhs_mat_ymm_0123_11, 0); + __m256i lhs_mat_ymm_23_11 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_11, lhs_mat_ymm_0123_11, 17); + __m256i lhs_mat_ymm_0123_20 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 128 + 512 * sb))); + __m256i lhs_mat_ymm_01_20 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_20, lhs_mat_ymm_0123_20, 0); + __m256i lhs_mat_ymm_23_20 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_20, lhs_mat_ymm_0123_20, 17); + __m256i lhs_mat_ymm_0123_21 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 160 + 512 * sb))); + __m256i lhs_mat_ymm_01_21 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_21, lhs_mat_ymm_0123_21, 0); + __m256i lhs_mat_ymm_23_21 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_21, lhs_mat_ymm_0123_21, 17); + __m256i lhs_mat_ymm_0123_30 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 192 + 512 * sb))); + __m256i lhs_mat_ymm_01_30 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_30, lhs_mat_ymm_0123_30, 0); + __m256i lhs_mat_ymm_23_30 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_30, lhs_mat_ymm_0123_30, 17); + __m256i lhs_mat_ymm_0123_31 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 224 + 512 * sb))); + __m256i lhs_mat_ymm_01_31 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_31, lhs_mat_ymm_0123_31, 0); + __m256i lhs_mat_ymm_23_31 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_31, lhs_mat_ymm_0123_31, 17); + + __m256i lhs_mat_ymm_0123_40 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 256 + 512 * sb))); + __m256i lhs_mat_ymm_01_40 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_40, lhs_mat_ymm_0123_40, 0); + __m256i lhs_mat_ymm_23_40 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_40, lhs_mat_ymm_0123_40, 17); + __m256i lhs_mat_ymm_0123_41 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 288 + 512 * sb))); + __m256i lhs_mat_ymm_01_41 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_41, lhs_mat_ymm_0123_41, 0); + __m256i lhs_mat_ymm_23_41 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_41, lhs_mat_ymm_0123_41, 17); + __m256i lhs_mat_ymm_0123_50 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 320 + 512 * sb))); + __m256i lhs_mat_ymm_01_50 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_50, lhs_mat_ymm_0123_50, 0); + __m256i lhs_mat_ymm_23_50 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_50, lhs_mat_ymm_0123_50, 17); + __m256i lhs_mat_ymm_0123_51 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 352 + 512 * sb))); + __m256i lhs_mat_ymm_01_51 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_51, lhs_mat_ymm_0123_51, 0); + __m256i lhs_mat_ymm_23_51 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_51, lhs_mat_ymm_0123_51, 17); + __m256i lhs_mat_ymm_0123_60 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 384 + 512 * sb))); + __m256i lhs_mat_ymm_01_60 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_60, lhs_mat_ymm_0123_60, 0); + __m256i lhs_mat_ymm_23_60 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_60, lhs_mat_ymm_0123_60, 17); + __m256i lhs_mat_ymm_0123_61 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 416 + 512 * sb))); + __m256i lhs_mat_ymm_01_61 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_61, lhs_mat_ymm_0123_61, 0); + __m256i lhs_mat_ymm_23_61 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_61, lhs_mat_ymm_0123_61, 17); + __m256i lhs_mat_ymm_0123_70 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 448 + 512 * sb))); + __m256i lhs_mat_ymm_01_70 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_70, lhs_mat_ymm_0123_70, 0); + __m256i lhs_mat_ymm_23_70 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_70, lhs_mat_ymm_0123_70, 17); + __m256i lhs_mat_ymm_0123_71 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 480 + 512 * sb))); + __m256i lhs_mat_ymm_01_71 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_71, lhs_mat_ymm_0123_71, 0); + __m256i lhs_mat_ymm_23_71 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_71, lhs_mat_ymm_0123_71, 17); + + + __m512i lhs_mat_01_00 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_00), lhs_mat_ymm_01_00, 1); + __m512i lhs_mat_23_00 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_00), lhs_mat_ymm_23_00, 1); + __m512i lhs_mat_01_01 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_01), lhs_mat_ymm_01_01, 1); + __m512i lhs_mat_23_01 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_01), lhs_mat_ymm_23_01, 1); + + __m512i lhs_mat_01_10 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_10), lhs_mat_ymm_01_10, 1); + __m512i lhs_mat_23_10 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_10), lhs_mat_ymm_23_10, 1); + __m512i lhs_mat_01_11 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_11), lhs_mat_ymm_01_11, 1); + __m512i lhs_mat_23_11 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_11), lhs_mat_ymm_23_11, 1); + + __m512i lhs_mat_01_20 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_20), lhs_mat_ymm_01_20, 1); + __m512i lhs_mat_23_20 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_20), lhs_mat_ymm_23_20, 1); + __m512i lhs_mat_01_21 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_21), lhs_mat_ymm_01_21, 1); + __m512i lhs_mat_23_21 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_21), lhs_mat_ymm_23_21, 1); + + __m512i lhs_mat_01_30 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_30), lhs_mat_ymm_01_30, 1); + __m512i lhs_mat_23_30 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_30), lhs_mat_ymm_23_30, 1); + __m512i lhs_mat_01_31 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_31), lhs_mat_ymm_01_31, 1); + __m512i lhs_mat_23_31 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_31), lhs_mat_ymm_23_31, 1); + + __m512i lhs_mat_01_40 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_40), lhs_mat_ymm_01_40, 1); + __m512i lhs_mat_23_40 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_40), lhs_mat_ymm_23_40, 1); + __m512i lhs_mat_01_41 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_41), lhs_mat_ymm_01_41, 1); + __m512i lhs_mat_23_41 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_41), lhs_mat_ymm_23_41, 1); + + __m512i lhs_mat_01_50 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_50), lhs_mat_ymm_01_50, 1); + __m512i lhs_mat_23_50 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_50), lhs_mat_ymm_23_50, 1); + __m512i lhs_mat_01_51 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_51), lhs_mat_ymm_01_51, 1); + __m512i lhs_mat_23_51 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_51), lhs_mat_ymm_23_51, 1); + + __m512i lhs_mat_01_60 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_60), lhs_mat_ymm_01_60, 1); + __m512i lhs_mat_23_60 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_60), lhs_mat_ymm_23_60, 1); + __m512i lhs_mat_01_61 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_61), lhs_mat_ymm_01_61, 1); + __m512i lhs_mat_23_61 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_61), lhs_mat_ymm_23_61, 1); + + __m512i lhs_mat_01_70 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_70), lhs_mat_ymm_01_70, 1); + __m512i lhs_mat_23_70 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_70), lhs_mat_ymm_23_70, 1); + __m512i lhs_mat_01_71 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_71), lhs_mat_ymm_01_71, 1); + __m512i lhs_mat_23_71 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_71), lhs_mat_ymm_23_71, 1); + + // Bsums are loaded for the different Q8_K blocks + __m128i lhs_raw_bsums_01_0123 = _mm_loadu_si128((const __m128i *)((a_ptrs[rp][b].bsums + 32 * sb))); + __m128i lhs_raw_bsums_23_0123 = _mm_loadu_si128((const __m128i *)(a_ptrs[rp][b].bsums + 8 + 32 * sb)); + __m128i lhs_raw_bsums_01_4567 = _mm_loadu_si128((const __m128i *)((a_ptrs[rp][b].bsums + 16 + 32 * sb))); + __m128i lhs_raw_bsums_23_4567 = _mm_loadu_si128((const __m128i *)(a_ptrs[rp][b].bsums + 24 + 32 * sb)); + + __m256i lhs_bsums_ymm_01_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_0123), lhs_raw_bsums_01_0123, 1); + __m512i lhs_bsums_01_0123 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_01_0123), lhs_bsums_ymm_01_0123, 1); + __m256i lhs_bsums_ymm_23_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_0123), lhs_raw_bsums_23_0123, 1); + __m512i lhs_bsums_23_0123 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_23_0123), lhs_bsums_ymm_23_0123, 1); __m256i lhs_bsums_ymm_01_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_4567), lhs_raw_bsums_01_4567, 1); + __m512i lhs_bsums_01_4567 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_01_4567), lhs_bsums_ymm_01_4567, 1); + __m256i lhs_bsums_ymm_23_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_4567), lhs_raw_bsums_23_4567, 1); + __m512i lhs_bsums_23_4567 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_23_4567), lhs_bsums_ymm_23_4567, 1); + + // Shuffle pattern one - left side input + const __m512i lhs_mat_01_00_sp1 = _mm512_shuffle_epi32(lhs_mat_01_00, (_MM_PERM_ENUM)160); //A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) + const __m512i lhs_mat_23_00_sp1 = _mm512_shuffle_epi32(lhs_mat_23_00, (_MM_PERM_ENUM)160); //A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) + + const __m512i lhs_mat_01_01_sp1 = _mm512_shuffle_epi32(lhs_mat_01_01, (_MM_PERM_ENUM)160); //A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) + const __m512i lhs_mat_23_01_sp1 = _mm512_shuffle_epi32(lhs_mat_23_01, (_MM_PERM_ENUM)160); //A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) + + const __m512i lhs_mat_01_10_sp1 = _mm512_shuffle_epi32(lhs_mat_01_10, (_MM_PERM_ENUM)160); //A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) + const __m512i lhs_mat_23_10_sp1 = _mm512_shuffle_epi32(lhs_mat_23_10, (_MM_PERM_ENUM)160); //A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) + + const __m512i lhs_mat_01_11_sp1 = _mm512_shuffle_epi32(lhs_mat_01_11, (_MM_PERM_ENUM)160); //A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) + const __m512i lhs_mat_23_11_sp1 = _mm512_shuffle_epi32(lhs_mat_23_11, (_MM_PERM_ENUM)160); //A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) + + const __m512i lhs_mat_01_20_sp1 = _mm512_shuffle_epi32(lhs_mat_01_20, (_MM_PERM_ENUM)160); //A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) + const __m512i lhs_mat_23_20_sp1 = _mm512_shuffle_epi32(lhs_mat_23_20, (_MM_PERM_ENUM)160); //A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) + + const __m512i lhs_mat_01_21_sp1 = _mm512_shuffle_epi32(lhs_mat_01_21, (_MM_PERM_ENUM)160); //A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) + const __m512i lhs_mat_23_21_sp1 = _mm512_shuffle_epi32(lhs_mat_23_21, (_MM_PERM_ENUM)160); //A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) + + const __m512i lhs_mat_01_30_sp1 = _mm512_shuffle_epi32(lhs_mat_01_30, (_MM_PERM_ENUM)160); //A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) + const __m512i lhs_mat_23_30_sp1 = _mm512_shuffle_epi32(lhs_mat_23_30, (_MM_PERM_ENUM)160); //A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) + + const __m512i lhs_mat_01_31_sp1 = _mm512_shuffle_epi32(lhs_mat_01_31, (_MM_PERM_ENUM)160); //A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) + const __m512i lhs_mat_23_31_sp1 = _mm512_shuffle_epi32(lhs_mat_23_31, (_MM_PERM_ENUM)160); //A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) + + const __m512i lhs_mat_01_40_sp1 = _mm512_shuffle_epi32(lhs_mat_01_40, (_MM_PERM_ENUM)160); //A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) + const __m512i lhs_mat_23_40_sp1 = _mm512_shuffle_epi32(lhs_mat_23_40, (_MM_PERM_ENUM)160); //A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) + + const __m512i lhs_mat_01_41_sp1 = _mm512_shuffle_epi32(lhs_mat_01_41, (_MM_PERM_ENUM)160); //A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) + const __m512i lhs_mat_23_41_sp1 = _mm512_shuffle_epi32(lhs_mat_23_41, (_MM_PERM_ENUM)160); //A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) + + const __m512i lhs_mat_01_50_sp1 = _mm512_shuffle_epi32(lhs_mat_01_50, (_MM_PERM_ENUM)160); //A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) + const __m512i lhs_mat_23_50_sp1 = _mm512_shuffle_epi32(lhs_mat_23_50, (_MM_PERM_ENUM)160); //A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) + + const __m512i lhs_mat_01_51_sp1 = _mm512_shuffle_epi32(lhs_mat_01_51, (_MM_PERM_ENUM)160); //A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) + const __m512i lhs_mat_23_51_sp1 = _mm512_shuffle_epi32(lhs_mat_23_51, (_MM_PERM_ENUM)160); //A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) + + const __m512i lhs_mat_01_60_sp1 = _mm512_shuffle_epi32(lhs_mat_01_60, (_MM_PERM_ENUM)160); //A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) + const __m512i lhs_mat_23_60_sp1 = _mm512_shuffle_epi32(lhs_mat_23_60, (_MM_PERM_ENUM)160); //A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) + + const __m512i lhs_mat_01_61_sp1 = _mm512_shuffle_epi32(lhs_mat_01_61, (_MM_PERM_ENUM)160); //A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) + const __m512i lhs_mat_23_61_sp1 = _mm512_shuffle_epi32(lhs_mat_23_61, (_MM_PERM_ENUM)160); //A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) + + const __m512i lhs_mat_01_70_sp1 = _mm512_shuffle_epi32(lhs_mat_01_70, (_MM_PERM_ENUM)160); //A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) + const __m512i lhs_mat_23_70_sp1 = _mm512_shuffle_epi32(lhs_mat_23_70, (_MM_PERM_ENUM)160); //A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) + + const __m512i lhs_mat_01_71_sp1 = _mm512_shuffle_epi32(lhs_mat_01_71, (_MM_PERM_ENUM)160); //A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) + const __m512i lhs_mat_23_71_sp1 = _mm512_shuffle_epi32(lhs_mat_23_71, (_MM_PERM_ENUM)160); //A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) + + const __m512i lhs_mat_01_00_sp2 = _mm512_shuffle_epi32(lhs_mat_01_00, (_MM_PERM_ENUM)245); //A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) + const __m512i lhs_mat_23_00_sp2 = _mm512_shuffle_epi32(lhs_mat_23_00, (_MM_PERM_ENUM)245); //A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) + + const __m512i lhs_mat_01_01_sp2 = _mm512_shuffle_epi32(lhs_mat_01_01, (_MM_PERM_ENUM)245); //A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) + const __m512i lhs_mat_23_01_sp2 = _mm512_shuffle_epi32(lhs_mat_23_01, (_MM_PERM_ENUM)245); //A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) + + const __m512i lhs_mat_01_10_sp2 = _mm512_shuffle_epi32(lhs_mat_01_10, (_MM_PERM_ENUM)245); //A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) + const __m512i lhs_mat_23_10_sp2 = _mm512_shuffle_epi32(lhs_mat_23_10, (_MM_PERM_ENUM)245); //A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) + + const __m512i lhs_mat_01_11_sp2 = _mm512_shuffle_epi32(lhs_mat_01_11, (_MM_PERM_ENUM)245); //A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) + const __m512i lhs_mat_23_11_sp2 = _mm512_shuffle_epi32(lhs_mat_23_11, (_MM_PERM_ENUM)245); //A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) + + const __m512i lhs_mat_01_20_sp2 = _mm512_shuffle_epi32(lhs_mat_01_20, (_MM_PERM_ENUM)245); //A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) + const __m512i lhs_mat_23_20_sp2 = _mm512_shuffle_epi32(lhs_mat_23_20, (_MM_PERM_ENUM)245); //A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) + + const __m512i lhs_mat_01_21_sp2 = _mm512_shuffle_epi32(lhs_mat_01_21, (_MM_PERM_ENUM)245); //A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) + const __m512i lhs_mat_23_21_sp2 = _mm512_shuffle_epi32(lhs_mat_23_21, (_MM_PERM_ENUM)245); //A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) + + const __m512i lhs_mat_01_30_sp2 = _mm512_shuffle_epi32(lhs_mat_01_30, (_MM_PERM_ENUM)245); //A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) + const __m512i lhs_mat_23_30_sp2 = _mm512_shuffle_epi32(lhs_mat_23_30, (_MM_PERM_ENUM)245); //A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) + + const __m512i lhs_mat_01_31_sp2 = _mm512_shuffle_epi32(lhs_mat_01_31, (_MM_PERM_ENUM)245); //A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) + const __m512i lhs_mat_23_31_sp2 = _mm512_shuffle_epi32(lhs_mat_23_31, (_MM_PERM_ENUM)245); //A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) + + const __m512i lhs_mat_01_40_sp2 = _mm512_shuffle_epi32(lhs_mat_01_40, (_MM_PERM_ENUM)245); //A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) + const __m512i lhs_mat_23_40_sp2 = _mm512_shuffle_epi32(lhs_mat_23_40, (_MM_PERM_ENUM)245); //A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) + + const __m512i lhs_mat_01_41_sp2 = _mm512_shuffle_epi32(lhs_mat_01_41, (_MM_PERM_ENUM)245); //A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) + const __m512i lhs_mat_23_41_sp2 = _mm512_shuffle_epi32(lhs_mat_23_41, (_MM_PERM_ENUM)245); //A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) + + const __m512i lhs_mat_01_50_sp2 = _mm512_shuffle_epi32(lhs_mat_01_50, (_MM_PERM_ENUM)245); //A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) + const __m512i lhs_mat_23_50_sp2 = _mm512_shuffle_epi32(lhs_mat_23_50, (_MM_PERM_ENUM)245); //A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) + + const __m512i lhs_mat_01_51_sp2 = _mm512_shuffle_epi32(lhs_mat_01_51, (_MM_PERM_ENUM)245); //A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) + const __m512i lhs_mat_23_51_sp2 = _mm512_shuffle_epi32(lhs_mat_23_51, (_MM_PERM_ENUM)245); //A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) + + const __m512i lhs_mat_01_60_sp2 = _mm512_shuffle_epi32(lhs_mat_01_60, (_MM_PERM_ENUM)245); //A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) + const __m512i lhs_mat_23_60_sp2 = _mm512_shuffle_epi32(lhs_mat_23_60, (_MM_PERM_ENUM)245); //A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) + + const __m512i lhs_mat_01_61_sp2 = _mm512_shuffle_epi32(lhs_mat_01_61, (_MM_PERM_ENUM)245); //A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) + const __m512i lhs_mat_23_61_sp2 = _mm512_shuffle_epi32(lhs_mat_23_61, (_MM_PERM_ENUM)245); //A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) + + const __m512i lhs_mat_01_70_sp2 = _mm512_shuffle_epi32(lhs_mat_01_70, (_MM_PERM_ENUM)245); //A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) + const __m512i lhs_mat_23_70_sp2 = _mm512_shuffle_epi32(lhs_mat_23_70, (_MM_PERM_ENUM)245); //A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) + + const __m512i lhs_mat_01_71_sp2 = _mm512_shuffle_epi32(lhs_mat_01_71, (_MM_PERM_ENUM)245); //A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) + const __m512i lhs_mat_23_71_sp2 = _mm512_shuffle_epi32(lhs_mat_23_71, (_MM_PERM_ENUM)245); //A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + __m512i iacc_mat_00_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp1, lhs_mat_01_00_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp1, lhs_mat_01_01_sp1)); + __m512i iacc_mat_01_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp1, lhs_mat_01_00_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp1, lhs_mat_01_01_sp1)); + + __m512i iacc_mat_10_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp1, lhs_mat_23_00_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp1, lhs_mat_23_01_sp1)); + __m512i iacc_mat_11_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp1, lhs_mat_23_00_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp1, lhs_mat_23_01_sp1)); + + __m512i iacc_mat_00_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp1, lhs_mat_01_10_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp1, lhs_mat_01_11_sp1)); + __m512i iacc_mat_01_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp1, lhs_mat_01_10_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp1, lhs_mat_01_11_sp1)); + + __m512i iacc_mat_10_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp1, lhs_mat_23_10_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp1, lhs_mat_23_11_sp1)); + __m512i iacc_mat_11_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp1, lhs_mat_23_10_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp1, lhs_mat_23_11_sp1)); + + __m512i iacc_mat_00_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp1, lhs_mat_01_20_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp1, lhs_mat_01_21_sp1)); + __m512i iacc_mat_01_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp1, lhs_mat_01_20_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp1, lhs_mat_01_21_sp1)); + + __m512i iacc_mat_10_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp1, lhs_mat_23_20_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp1, lhs_mat_23_21_sp1)); + __m512i iacc_mat_11_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp1, lhs_mat_23_20_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp1, lhs_mat_23_21_sp1)); + + __m512i iacc_mat_00_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp1, lhs_mat_01_30_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp1, lhs_mat_01_31_sp1)); + __m512i iacc_mat_01_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp1, lhs_mat_01_30_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp1, lhs_mat_01_31_sp1)); + + __m512i iacc_mat_10_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp1, lhs_mat_23_30_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp1, lhs_mat_23_31_sp1)); + __m512i iacc_mat_11_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp1, lhs_mat_23_30_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp1, lhs_mat_23_31_sp1)); + + __m512i iacc_mat_00_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp1, lhs_mat_01_40_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp1, lhs_mat_01_41_sp1)); + __m512i iacc_mat_01_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp1, lhs_mat_01_40_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp1, lhs_mat_01_41_sp1)); + + __m512i iacc_mat_10_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp1, lhs_mat_23_40_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp1, lhs_mat_23_41_sp1)); + __m512i iacc_mat_11_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp1, lhs_mat_23_40_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp1, lhs_mat_23_41_sp1)); + + __m512i iacc_mat_00_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp1, lhs_mat_01_50_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp1, lhs_mat_01_51_sp1)); + __m512i iacc_mat_01_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp1, lhs_mat_01_50_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp1, lhs_mat_01_51_sp1)); + + __m512i iacc_mat_10_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp1, lhs_mat_23_50_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp1, lhs_mat_23_51_sp1)); + __m512i iacc_mat_11_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp1, lhs_mat_23_50_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp1, lhs_mat_23_51_sp1)); + + __m512i iacc_mat_00_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp1, lhs_mat_01_60_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp1, lhs_mat_01_61_sp1)); + __m512i iacc_mat_01_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp1, lhs_mat_01_60_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp1, lhs_mat_01_61_sp1)); + + __m512i iacc_mat_10_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp1, lhs_mat_23_60_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp1, lhs_mat_23_61_sp1)); + __m512i iacc_mat_11_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp1, lhs_mat_23_60_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp1, lhs_mat_23_61_sp1)); + + __m512i iacc_mat_00_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp1, lhs_mat_01_70_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp1, lhs_mat_01_71_sp1)); + __m512i iacc_mat_01_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp1, lhs_mat_01_70_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp1, lhs_mat_01_71_sp1)); + + __m512i iacc_mat_10_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp1, lhs_mat_23_70_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp1, lhs_mat_23_71_sp1)); + __m512i iacc_mat_11_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp1, lhs_mat_23_70_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp1, lhs_mat_23_71_sp1)); + + + __m512i iacc_mat_00_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp2, lhs_mat_01_00_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp2, lhs_mat_01_01_sp2)); + __m512i iacc_mat_01_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp2, lhs_mat_01_00_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp2, lhs_mat_01_01_sp2)); + + __m512i iacc_mat_10_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp2, lhs_mat_23_00_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp2, lhs_mat_23_01_sp2)); + __m512i iacc_mat_11_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp2, lhs_mat_23_00_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp2, lhs_mat_23_01_sp2)); + + __m512i iacc_mat_00_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp2, lhs_mat_01_10_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp2, lhs_mat_01_11_sp2)); + __m512i iacc_mat_01_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp2, lhs_mat_01_10_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp2, lhs_mat_01_11_sp2)); + + __m512i iacc_mat_10_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp2, lhs_mat_23_10_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp2, lhs_mat_23_11_sp2)); + __m512i iacc_mat_11_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp2, lhs_mat_23_10_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp2, lhs_mat_23_11_sp2)); + + __m512i iacc_mat_00_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp2, lhs_mat_01_20_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp2, lhs_mat_01_21_sp2)); + __m512i iacc_mat_01_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp2, lhs_mat_01_20_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp2, lhs_mat_01_21_sp2)); + + __m512i iacc_mat_10_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp2, lhs_mat_23_20_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp2, lhs_mat_23_21_sp2)); + __m512i iacc_mat_11_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp2, lhs_mat_23_20_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp2, lhs_mat_23_21_sp2)); + + __m512i iacc_mat_00_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp2, lhs_mat_01_30_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp2, lhs_mat_01_31_sp2)); + __m512i iacc_mat_01_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp2, lhs_mat_01_30_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp2, lhs_mat_01_31_sp2)); + + __m512i iacc_mat_10_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp2, lhs_mat_23_30_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp2, lhs_mat_23_31_sp2)); + __m512i iacc_mat_11_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp2, lhs_mat_23_30_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp2, lhs_mat_23_31_sp2)); + + __m512i iacc_mat_00_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp2, lhs_mat_01_40_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp2, lhs_mat_01_41_sp2)); + __m512i iacc_mat_01_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp2, lhs_mat_01_40_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp2, lhs_mat_01_41_sp2)); + + __m512i iacc_mat_10_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp2, lhs_mat_23_40_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp2, lhs_mat_23_41_sp2)); + __m512i iacc_mat_11_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp2, lhs_mat_23_40_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp2, lhs_mat_23_41_sp2)); + + __m512i iacc_mat_00_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp2, lhs_mat_01_50_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp2, lhs_mat_01_51_sp2)); + __m512i iacc_mat_01_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp2, lhs_mat_01_50_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp2, lhs_mat_01_51_sp2)); + + __m512i iacc_mat_10_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp2, lhs_mat_23_50_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp2, lhs_mat_23_51_sp2)); + __m512i iacc_mat_11_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp2, lhs_mat_23_50_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp2, lhs_mat_23_51_sp2)); + + __m512i iacc_mat_00_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp2, lhs_mat_01_60_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp2, lhs_mat_01_61_sp2)); + __m512i iacc_mat_01_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp2, lhs_mat_01_60_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp2, lhs_mat_01_61_sp2)); + + __m512i iacc_mat_10_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp2, lhs_mat_23_60_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp2, lhs_mat_23_61_sp2)); + __m512i iacc_mat_11_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp2, lhs_mat_23_60_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp2, lhs_mat_23_61_sp2)); + + __m512i iacc_mat_00_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp2, lhs_mat_01_70_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp2, lhs_mat_01_71_sp2)); + __m512i iacc_mat_01_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp2, lhs_mat_01_70_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp2, lhs_mat_01_71_sp2)); + + __m512i iacc_mat_10_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp2, lhs_mat_23_70_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp2, lhs_mat_23_71_sp2)); + __m512i iacc_mat_11_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp2, lhs_mat_23_70_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp2, lhs_mat_23_71_sp2)); + + // Combine results from both shuffle patterns for each output block + __m512i iacc_mat_00_0 = _mm512_add_epi16(iacc_mat_00_0_sp1, iacc_mat_00_0_sp2); + __m512i iacc_mat_01_0 = _mm512_add_epi16(iacc_mat_01_0_sp1, iacc_mat_01_0_sp2); + __m512i iacc_mat_10_0 = _mm512_add_epi16(iacc_mat_10_0_sp1, iacc_mat_10_0_sp2); + __m512i iacc_mat_11_0 = _mm512_add_epi16(iacc_mat_11_0_sp1, iacc_mat_11_0_sp2); + + __m512i iacc_mat_00_1 = _mm512_add_epi16(iacc_mat_00_1_sp1, iacc_mat_00_1_sp2); + __m512i iacc_mat_01_1 = _mm512_add_epi16(iacc_mat_01_1_sp1, iacc_mat_01_1_sp2); + __m512i iacc_mat_10_1 = _mm512_add_epi16(iacc_mat_10_1_sp1, iacc_mat_10_1_sp2); + __m512i iacc_mat_11_1 = _mm512_add_epi16(iacc_mat_11_1_sp1, iacc_mat_11_1_sp2); + + __m512i iacc_mat_00_2 = _mm512_add_epi16(iacc_mat_00_2_sp1, iacc_mat_00_2_sp2); + __m512i iacc_mat_01_2 = _mm512_add_epi16(iacc_mat_01_2_sp1, iacc_mat_01_2_sp2); + __m512i iacc_mat_10_2 = _mm512_add_epi16(iacc_mat_10_2_sp1, iacc_mat_10_2_sp2); + __m512i iacc_mat_11_2 = _mm512_add_epi16(iacc_mat_11_2_sp1, iacc_mat_11_2_sp2); + + __m512i iacc_mat_00_3 = _mm512_add_epi16(iacc_mat_00_3_sp1, iacc_mat_00_3_sp2); + __m512i iacc_mat_01_3 = _mm512_add_epi16(iacc_mat_01_3_sp1, iacc_mat_01_3_sp2); + __m512i iacc_mat_10_3 = _mm512_add_epi16(iacc_mat_10_3_sp1, iacc_mat_10_3_sp2); + __m512i iacc_mat_11_3 = _mm512_add_epi16(iacc_mat_11_3_sp1, iacc_mat_11_3_sp2); + + __m512i iacc_mat_00_4 = _mm512_add_epi16(iacc_mat_00_4_sp1, iacc_mat_00_4_sp2); + __m512i iacc_mat_01_4 = _mm512_add_epi16(iacc_mat_01_4_sp1, iacc_mat_01_4_sp2); + __m512i iacc_mat_10_4 = _mm512_add_epi16(iacc_mat_10_4_sp1, iacc_mat_10_4_sp2); + __m512i iacc_mat_11_4 = _mm512_add_epi16(iacc_mat_11_4_sp1, iacc_mat_11_4_sp2); + + __m512i iacc_mat_00_5 = _mm512_add_epi16(iacc_mat_00_5_sp1, iacc_mat_00_5_sp2); + __m512i iacc_mat_01_5 = _mm512_add_epi16(iacc_mat_01_5_sp1, iacc_mat_01_5_sp2); + __m512i iacc_mat_10_5 = _mm512_add_epi16(iacc_mat_10_5_sp1, iacc_mat_10_5_sp2); + __m512i iacc_mat_11_5 = _mm512_add_epi16(iacc_mat_11_5_sp1, iacc_mat_11_5_sp2); + + __m512i iacc_mat_00_6 = _mm512_add_epi16(iacc_mat_00_6_sp1, iacc_mat_00_6_sp2); + __m512i iacc_mat_01_6 = _mm512_add_epi16(iacc_mat_01_6_sp1, iacc_mat_01_6_sp2); + __m512i iacc_mat_10_6 = _mm512_add_epi16(iacc_mat_10_6_sp1, iacc_mat_10_6_sp2); + __m512i iacc_mat_11_6 = _mm512_add_epi16(iacc_mat_11_6_sp1, iacc_mat_11_6_sp2); + + __m512i iacc_mat_00_7 = _mm512_add_epi16(iacc_mat_00_7_sp1, iacc_mat_00_7_sp2); + __m512i iacc_mat_01_7 = _mm512_add_epi16(iacc_mat_01_7_sp1, iacc_mat_01_7_sp2); + __m512i iacc_mat_10_7 = _mm512_add_epi16(iacc_mat_10_7_sp1, iacc_mat_10_7_sp2); + __m512i iacc_mat_11_7 = _mm512_add_epi16(iacc_mat_11_7_sp1, iacc_mat_11_7_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + iacc_mat_00_0 = _mm512_madd_epi16(iacc_mat_00_0, scale_014589CD_0); + iacc_mat_01_0 = _mm512_madd_epi16(iacc_mat_01_0, scale_2367ABEF_0); + iacc_mat_10_0 = _mm512_madd_epi16(iacc_mat_10_0, scale_014589CD_0); + iacc_mat_11_0 = _mm512_madd_epi16(iacc_mat_11_0, scale_2367ABEF_0); + + iacc_mat_00_1 = _mm512_madd_epi16(iacc_mat_00_1, scale_014589CD_1); + iacc_mat_01_1 = _mm512_madd_epi16(iacc_mat_01_1, scale_2367ABEF_1); + iacc_mat_10_1 = _mm512_madd_epi16(iacc_mat_10_1, scale_014589CD_1); + iacc_mat_11_1 = _mm512_madd_epi16(iacc_mat_11_1, scale_2367ABEF_1); + + iacc_mat_00_2 = _mm512_madd_epi16(iacc_mat_00_2, scale_014589CD_2); + iacc_mat_01_2 = _mm512_madd_epi16(iacc_mat_01_2, scale_2367ABEF_2); + iacc_mat_10_2 = _mm512_madd_epi16(iacc_mat_10_2, scale_014589CD_2); + iacc_mat_11_2 = _mm512_madd_epi16(iacc_mat_11_2, scale_2367ABEF_2); + + iacc_mat_00_3 = _mm512_madd_epi16(iacc_mat_00_3, scale_014589CD_3); + iacc_mat_01_3 = _mm512_madd_epi16(iacc_mat_01_3, scale_2367ABEF_3); + iacc_mat_10_3 = _mm512_madd_epi16(iacc_mat_10_3, scale_014589CD_3); + iacc_mat_11_3 = _mm512_madd_epi16(iacc_mat_11_3, scale_2367ABEF_3); + + iacc_mat_00_4 = _mm512_madd_epi16(iacc_mat_00_4, scale_014589CD_4); + iacc_mat_01_4 = _mm512_madd_epi16(iacc_mat_01_4, scale_2367ABEF_4); + iacc_mat_10_4 = _mm512_madd_epi16(iacc_mat_10_4, scale_014589CD_4); + iacc_mat_11_4 = _mm512_madd_epi16(iacc_mat_11_4, scale_2367ABEF_4); + + iacc_mat_00_5 = _mm512_madd_epi16(iacc_mat_00_5, scale_014589CD_5); + iacc_mat_01_5 = _mm512_madd_epi16(iacc_mat_01_5, scale_2367ABEF_5); + iacc_mat_10_5 = _mm512_madd_epi16(iacc_mat_10_5, scale_014589CD_5); + iacc_mat_11_5 = _mm512_madd_epi16(iacc_mat_11_5, scale_2367ABEF_5); + + iacc_mat_00_6 = _mm512_madd_epi16(iacc_mat_00_6, scale_014589CD_6); + iacc_mat_01_6 = _mm512_madd_epi16(iacc_mat_01_6, scale_2367ABEF_6); + iacc_mat_10_6 = _mm512_madd_epi16(iacc_mat_10_6, scale_014589CD_6); + iacc_mat_11_6 = _mm512_madd_epi16(iacc_mat_11_6, scale_2367ABEF_6); + + iacc_mat_00_7 = _mm512_madd_epi16(iacc_mat_00_7, scale_014589CD_7); + iacc_mat_01_7 = _mm512_madd_epi16(iacc_mat_01_7, scale_2367ABEF_7); + iacc_mat_10_7 = _mm512_madd_epi16(iacc_mat_10_7, scale_014589CD_7); + iacc_mat_11_7 = _mm512_madd_epi16(iacc_mat_11_7, scale_2367ABEF_7); + + __m512i iacc_mat_00 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_00_0, iacc_mat_00_1), _mm512_add_epi32(iacc_mat_00_2, iacc_mat_00_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_00_4, iacc_mat_00_5), _mm512_add_epi32(iacc_mat_00_6, iacc_mat_00_7))); + __m512i iacc_mat_01 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_01_0, iacc_mat_01_1), _mm512_add_epi32(iacc_mat_01_2, iacc_mat_01_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_01_4, iacc_mat_01_5), _mm512_add_epi32(iacc_mat_01_6, iacc_mat_01_7))); + __m512i iacc_mat_10 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_10_0, iacc_mat_10_1), _mm512_add_epi32(iacc_mat_10_2, iacc_mat_10_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_10_4, iacc_mat_10_5), _mm512_add_epi32(iacc_mat_10_6, iacc_mat_10_7))); + __m512i iacc_mat_11 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_11_0, iacc_mat_11_1), _mm512_add_epi32(iacc_mat_11_2, iacc_mat_11_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_11_4, iacc_mat_11_5), _mm512_add_epi32(iacc_mat_11_6, iacc_mat_11_7))); + + // Straighten out to make 4 row vectors + __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); + __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); + __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); + __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); + + // Load the scale(d) values for all the 4 Q8_k blocks and repeat it across lanes + const __m128 row_scale_f32_sse = _mm_load_ps(a_ptrs[rp][b].d); + const __m256 row_scale_f32_ymm = _mm256_set_m128(row_scale_f32_sse, row_scale_f32_sse); + const __m512 row_scale_f32 = _mm512_insertf32x8(_mm512_castps256_ps512(row_scale_f32_ymm), row_scale_f32_ymm, 1); + + // Multiply with appropiate scales and accumulate (for both d and dmin) below + acc_rows[rp * 4] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); + acc_rows[rp * 4 + 1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); + acc_rows[rp * 4 + 2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); + acc_rows[rp * 4 + 3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); + + // Take two bsums from two Q8_Ks at a time and multiply with corresponding mins values from each Q2_K + __m512i iacc_row_min_0_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)0), mins_01); + __m512i iacc_row_min_1_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)170), mins_01); + __m512i iacc_row_min_2_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)0), mins_01); + __m512i iacc_row_min_3_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)170), mins_01); + + __m512i iacc_row_min_0_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)85), mins_23); + __m512i iacc_row_min_1_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)255), mins_23); + __m512i iacc_row_min_2_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)85), mins_23); + __m512i iacc_row_min_3_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)255), mins_23); + + __m512i iacc_row_min_0_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)0), mins_45); + __m512i iacc_row_min_1_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)170), mins_45); + __m512i iacc_row_min_2_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)0), mins_45); + __m512i iacc_row_min_3_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)170), mins_45); + + __m512i iacc_row_min_0_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)85), mins_67); + __m512i iacc_row_min_1_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)255), mins_67); + __m512i iacc_row_min_2_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)85), mins_67); + __m512i iacc_row_min_3_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)255), mins_67); + + __m512i iacc_row_min_0 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_0_01, iacc_row_min_0_23), _mm512_add_epi32(iacc_row_min_0_45,iacc_row_min_0_67)); + __m512i iacc_row_min_1 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_1_01, iacc_row_min_1_23), _mm512_add_epi32(iacc_row_min_1_45,iacc_row_min_1_67)); + __m512i iacc_row_min_2 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_2_01, iacc_row_min_2_23), _mm512_add_epi32(iacc_row_min_2_45,iacc_row_min_2_67)); + __m512i iacc_row_min_3 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_3_01, iacc_row_min_3_23), _mm512_add_epi32(iacc_row_min_3_45,iacc_row_min_3_67)); + + acc_min_rows[rp * 4] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_0), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_min_rows[rp * 4]); + acc_min_rows[rp * 4 + 1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_1), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_min_rows[rp * 4 + 1]); + acc_min_rows[rp * 4 + 2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_2), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_min_rows[rp * 4 + 2]); + acc_min_rows[rp * 4 + 3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_3), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_min_rows[rp * 4 + 3]); } } } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j] - sum_minf[m][j]; - } + // Store the accumulated values + for (int i = 0; i < 16; i++) { + _mm512_storeu_ps((float * )(s + ((y * 4 + i) * bs + x * 8)), _mm512_sub_ps(acc_rows[i], acc_min_rows[i])); } } } + + for (; y < nr / 4; y ++) { + + const block_q8_Kx4 * a_ptr = a_ptr_start + (y * nb); + + // Take group of eight block_q2_kx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = 0; x < anc / 8; x += 2) { + + const block_q2_Kx8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); + const block_q2_Kx8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); + + // Master FP accumulators + __m512 acc_rows[4]; + for (int i = 0; i < 4; i++) { + acc_rows[i] = _mm512_setzero_ps(); + } + + __m512 acc_min_rows[4]; + for (int i = 0; i < 4; i++) { + acc_min_rows[i] = _mm512_setzero_ps(); + } + // For super block + for (int64_t b = 0; b < nb; b++) { + // Delta values - Load the sixteen scale values from two block_q2_kx8 structures + const __m512 col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); + + // dmin values - Load the sixteen dmin values from two block_q2_kx8 structures + const __m512 col_dmin_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].dmin, b_ptr_1[b].dmin); + + // Loop to iterate over the sixteen sub blocks of a super block - eight sub blocks are processed per iteration + for (int sb = 0; sb < QK_K / 128; sb++) { + + // Load the eight block_q2_k for eight sub blocks quantized values interleaved with each other in chunks of eight bytes - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + sb * 256)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_0123_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_4567_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_0123_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_4567_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 224 + sb * 256)); + + const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + sb * 256)); + const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_89AB_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_89AB_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 224 + sb * 256)); + + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + const __m256i rhs_raw_mat_0145_2 = _mm256_blend_epi32(rhs_raw_mat_0123_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_2, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_2, requiredOrder), rhs_raw_mat_4567_2, 240); + const __m256i rhs_raw_mat_0145_3 = _mm256_blend_epi32(rhs_raw_mat_0123_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_3, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_3, requiredOrder), rhs_raw_mat_4567_3, 240); + + const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); + const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); + const __m256i rhs_raw_mat_89CD_2 = _mm256_blend_epi32(rhs_raw_mat_89AB_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_2, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_2, requiredOrder), rhs_raw_mat_CDEF_2, 240); + const __m256i rhs_raw_mat_89CD_3 = _mm256_blend_epi32(rhs_raw_mat_89AB_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_3, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_3, requiredOrder), rhs_raw_mat_CDEF_3, 240); + + const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); + const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); + const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); + const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); + + const __m512i rhs_raw_mat_014589CD_2 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_2), rhs_raw_mat_89CD_2, 1); + const __m512i rhs_raw_mat_2367ABEF_2 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_2), rhs_raw_mat_ABEF_2, 1); + const __m512i rhs_raw_mat_014589CD_3 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_3), rhs_raw_mat_89CD_3, 1); + const __m512i rhs_raw_mat_2367ABEF_3 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_3), rhs_raw_mat_ABEF_3, 1); + + //2-bit -> 8-bit + const __m512i rhs_mat_014589CD_00 = _mm512_and_si512(rhs_raw_mat_014589CD_0,m3bexpanded); //B00(0-7) B01(0-7) B04(0-7) B05(0-7) B08(0-7) B09(0-7) B0C(0-7) B0D(0-7) + const __m512i rhs_mat_2367ABEF_00 = _mm512_and_si512(rhs_raw_mat_2367ABEF_0,m3bexpanded); //B02(0-7) B03(0-7) B06(0-7) B07(0-7) B0A(0-7) B0B(0-7) B0E(0-7) B0F(0-7) + const __m512i rhs_mat_014589CD_01 = _mm512_and_si512(rhs_raw_mat_014589CD_1,m3bexpanded); //B00(8-15) B01(8-15) B04(8-15) B05(8-15) B08(8-15) B09(8-15) B0C(8-15) B0D(8-15) + const __m512i rhs_mat_2367ABEF_01 = _mm512_and_si512(rhs_raw_mat_2367ABEF_1,m3bexpanded); //B02(8-15) B03(8-15) B06(8-15) B07(8-15) B0A(8-15) B0B(8-15) B0E(8-15) B0F(8-15) + const __m512i rhs_mat_014589CD_10 = _mm512_and_si512(rhs_raw_mat_014589CD_2,m3bexpanded); //B10(0-7) B11(0-7) B14(0-7) B15(0-7) B18(0-7) B19(0-7) B1C(0-7) B1D(0-7) + const __m512i rhs_mat_2367ABEF_10 = _mm512_and_si512(rhs_raw_mat_2367ABEF_2,m3bexpanded); //B12(0-7) B13(0-7) B16(0-7) B17(0-7) B1A(0-7) B1B(0-7) B1E(0-7) B1F(0-7) + const __m512i rhs_mat_014589CD_11 = _mm512_and_si512(rhs_raw_mat_014589CD_3,m3bexpanded); //B10(8-15) B11(8-15) B14(8-15) B15(8-15) B18(8-15) B19(8-15) B1C(8-15) B1D(8-15) + const __m512i rhs_mat_2367ABEF_11 = _mm512_and_si512(rhs_raw_mat_2367ABEF_3,m3bexpanded); //B12(8-15) B13(8-15) B16(8-15) B17(8-15) B1A(8-15) B1B(8-15) B1E(8-15) B1F(8-15) + + const __m512i rhs_mat_014589CD_20 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 2), m3bexpanded); //B20(0-7) B21(0-7) B24(0-7) B25(0-7) B28(0-7) B29(0-7) B2C(0-7) B2D(0-7) + const __m512i rhs_mat_2367ABEF_20 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 2), m3bexpanded); //B22(0-7) B23(0-7) B26(0-7) B27(0-7) B2A(0-7) B2B(0-7) B2E(0-7) B2F(0-7) + + const __m512i rhs_mat_014589CD_21 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 2), m3bexpanded); //B20(8-15) B21(8-15) B24(8-15) B25(8-15) B28(8-15) B29(8-15) B2C(8-15) B2D(8-15) + const __m512i rhs_mat_2367ABEF_21 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 2), m3bexpanded); //B22(8-15) B23(8-15) B26(8-15) B27(8-15) B2A(8-15) B2B(8-15) B2E(8-15) B2F(8-15) + + const __m512i rhs_mat_014589CD_30 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 2), m3bexpanded); //B30(0-7) B31(0-7) B34(0-7) B35(0-7) B38(0-7) B39(0-7) B3C(0-7) B3D(0-7) + const __m512i rhs_mat_2367ABEF_30 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 2), m3bexpanded); //B32(0-7) B33(0-7) B36(0-7) B37(0-7) B3A(0-7) B3B(0-7) B3E(0-7) B3F(0-7) + + const __m512i rhs_mat_014589CD_31 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 2), m3bexpanded); //B30(8-15) B31(8-15) B34(8-15) B35(8-15) B38(8-15) B39(8-15) B3C(8-15) B3D(8-15) + const __m512i rhs_mat_2367ABEF_31 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 2), m3bexpanded); //B32(8-15) B33(8-15) B36(8-15) B37(8-15) B3A(8-15) B3B(8-15) B3E(8-15) B3F(8-15) + + const __m512i rhs_mat_014589CD_40 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m3bexpanded); //B40(0-7) B41(0-7) B44(0-7) B45(0-7) B48(0-7) B49(0-7) B4C(0-7) B4D(0-7) + const __m512i rhs_mat_2367ABEF_40 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m3bexpanded); //B42(0-7) B43(0-7) B46(0-7) B47(0-7) B4A(0-7) B4B(0-7) B4E(0-7) B4F(0-7) + + const __m512i rhs_mat_014589CD_41 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m3bexpanded); //B40(8-15) B41(8-15) B44(8-15) B45(8-15) B48(8-15) B49(8-15) B4C(8-15) B4D(8-15) + const __m512i rhs_mat_2367ABEF_41 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m3bexpanded); //B42(8-15) B43(8-15) B46(8-15) B47(8-15) B4A(8-15) B4B(8-15) B4E(8-15) B4F(8-15) + + const __m512i rhs_mat_014589CD_50 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 4), m3bexpanded); //B50(0-7) B51(0-7) B54(0-7) B55(0-7) B58(0-7) B59(0-7) B5C(0-7) B5D(0-7) + const __m512i rhs_mat_2367ABEF_50 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 4), m3bexpanded); //B52(0-7) B53(0-7) B56(0-7) B57(0-7) B5A(0-7) B5B(0-7) B5E(0-7) B5F(0-7) + + const __m512i rhs_mat_014589CD_51 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 4), m3bexpanded); //B50(8-15) B51(8-15) B54(8-15) B55(8-15) B58(8-15) B59(8-15) B5C(8-15) B5D(8-15) + const __m512i rhs_mat_2367ABEF_51 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 4), m3bexpanded); //B52(8-15) B53(8-15) B56(8-15) B57(8-15) B5A(8-15) B5B(8-15) B5E(8-15) B5F(8-15) + + const __m512i rhs_mat_014589CD_60 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 6), m3bexpanded); //B60(0-7) B61(0-7) B64(0-7) B65(0-7) B68(0-7) B69(0-7) B6C(0-7) B6D(0-7) + const __m512i rhs_mat_2367ABEF_60 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 6), m3bexpanded); //B62(0-7) B63(0-7) B66(0-7) B67(0-7) B6A(0-7) B6B(0-7) B6E(0-7) B6F(0-7) + + const __m512i rhs_mat_014589CD_61 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 6), m3bexpanded); //B60(8-15) B61(8-15) B64(8-15) B65(8-15) B68(8-15) B69(8-15) B6C(8-15) B6D(8-15) + const __m512i rhs_mat_2367ABEF_61 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 6), m3bexpanded); //B62(8-15) B63(8-15) B66(8-15) B67(8-15) B6A(8-15) B6B(8-15) B6E(8-15) B6F(8-15) + + const __m512i rhs_mat_014589CD_70 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 6), m3bexpanded); //B70(0-7) B71(0-7) B74(0-7) B75(0-7) B78(0-7) B79(0-7) B7C(0-7) B7D(0-7) + const __m512i rhs_mat_2367ABEF_70 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 6), m3bexpanded); //B72(0-7) B73(0-7) B76(0-7) B77(0-7) B7A(0-7) B7B(0-7) B7E(0-7) B7F(0-7) + + const __m512i rhs_mat_014589CD_71 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 6), m3bexpanded); //B70(8-15) B71(8-15) B74(8-15) B75(8-15) B78(8-15) B79(8-15) B7C(8-15) B7D(8-15) + const __m512i rhs_mat_2367ABEF_71 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 6), m3bexpanded); //B72(8-15) B73(8-15) B76(8-15) B77(8-15) B7A(8-15) B7B(8-15) B7E(8-15) B7F(8-15) + + const __m512i rhs_mat_014589CD_00_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_00, (_MM_PERM_ENUM)136); //B00(0-3) B01(0-3) B00(0-3) B01(0-3) B04(0-3) B05(0-3) B04(0-3) B05(0-3) B08(0-3) B09(0-3) B08(0-3) B09(0-3) B0C(0-3) B0D(0-3) B0C(0-3) B0D(0-3) + const __m512i rhs_mat_2367ABEF_00_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_00, (_MM_PERM_ENUM)136); //B02(0-3) B03(0-3) B02(0-3) B03(0-3) B06(0-3) B07(0-3) B06(0-3) B07(0-3) B0A(0-3) B0B(0-3) B0A(0-3) B0B(0-3) B0E(0-3) B0F(0-3) B0E(0-3) B0F(0-3) + + const __m512i rhs_mat_014589CD_01_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_01, (_MM_PERM_ENUM)136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) B08(8-11) B09(8-11) B08(8-11) B09(8-11) B0C(8-11) B0D(8-11) B0C(8-11) B0D(8-11) + const __m512i rhs_mat_2367ABEF_01_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_01, (_MM_PERM_ENUM)136); //B02(8-11) B03(8-11) B02(8-11) B03(8-11) B06(8-11) B07(8-11) B06(8-11) B07(8-11) B0A(8-11) B0B(8-11) B0A(8-11) B0B(8-11) B0E(8-11) B0F(8-11) B0E(8-11) B0F(8-11) + + const __m512i rhs_mat_014589CD_10_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_10, (_MM_PERM_ENUM)136); //B10(0-3) B11(0-3) B10(0-3) B11(0-3) B14(0-3) B15(0-3) B14(0-3) B15(0-3) B18(0-3) B19(0-3) B18(0-3) B19(0-3) B1C(0-3) B1D(0-3) B1C(0-3) B1D(0-3) + const __m512i rhs_mat_2367ABEF_10_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_10, (_MM_PERM_ENUM)136); //B12(0-3) B13(0-3) B12(0-3) B13(0-3) B16(0-3) B17(0-3) B16(0-3) B17(0-3) B1A(0-3) B1B(0-3) B1A(0-3) B1B(0-3) B1E(0-3) B1F(0-3) B1E(0-3) B1F(0-3) + + const __m512i rhs_mat_014589CD_11_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_11, (_MM_PERM_ENUM)136); //B10(8-11) B11(8-11) B10(8-11) B11(8-11) B14(8-11) B15(8-11) B14(8-11) B15(8-11) B18(8-11) B19(8-11) B18(8-11) B19(8-11) B1C(8-11) B1D(8-11) B1C(8-11) B1D(8-11) + const __m512i rhs_mat_2367ABEF_11_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_11, (_MM_PERM_ENUM)136); //B12(8-11) B13(8-11) B12(8-11) B13(8-11) B16(8-11) B17(8-11) B16(8-11) B17(8-11) B1A(8-11) B1B(8-11) B1A(8-11) B1B(8-11) B1E(8-11) B1F(8-11) B1E(8-11) B1F(8-11) + + const __m512i rhs_mat_014589CD_20_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_20, (_MM_PERM_ENUM)136); //B20(0-3) B21(0-3) B20(0-3) B21(0-3) B24(0-3) B25(0-3) B24(0-3) B25(0-3) B28(0-3) B29(0-3) B28(0-3) B29(0-3) B2C(0-3) B2D(0-3) B2C(0-3) B2D(0-3) + const __m512i rhs_mat_2367ABEF_20_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_20, (_MM_PERM_ENUM)136); //B22(0-3) B23(0-3) B22(0-3) B23(0-3) B26(0-3) B27(0-3) B26(0-3) B27(0-3) B2A(0-3) B2B(0-3) B2A(0-3) B2B(0-3) B2E(0-3) B2F(0-3) B2E(0-3) B2F(0-3) + + const __m512i rhs_mat_014589CD_21_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_21, (_MM_PERM_ENUM)136); //B20(8-11) B21(8-11) B20(8-11) B21(8-11) B24(8-11) B25(8-11) B24(8-11) B25(8-11) B28(8-11) B29(8-11) B28(8-11) B29(8-11) B2C(8-11) B2D(8-11) B2C(8-11) B2D(8-11) + const __m512i rhs_mat_2367ABEF_21_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_21, (_MM_PERM_ENUM)136); //B22(8-11) B23(8-11) B22(8-11) B23(8-11) B26(8-11) B27(8-11) B26(8-11) B27(8-11) B2A(8-11) B2B(8-11) B2A(8-11) B2B(8-11) B2E(8-11) B2F(8-11) B2E(8-11) B2F(8-11) + const __m512i rhs_mat_014589CD_30_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_30, (_MM_PERM_ENUM)136); ///B30(0-3) B31(0-3) B30(0-3) B31(0-3) B34(0-3) B35(0-3) B34(0-3) B35(0-3) B38(0-3) B39(0-3) B38(0-3) B39(0-3) B3C(0-3) B3D(0-3) B3C(0-3) B3D(0-3) + const __m512i rhs_mat_2367ABEF_30_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_30, (_MM_PERM_ENUM)136); //B32(0-3) B33(0-3) B32(0-3) B33(0-3) B36(0-3) B37(0-3) B36(0-3) B37(0-3) B3A(0-3) B3B(0-3) B3A(0-3) B3B(0-3) B3E(0-3) B3F(0-3) B3E(0-3) B3F(0-3) + + const __m512i rhs_mat_014589CD_31_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_31, (_MM_PERM_ENUM)136); //B30(8-11) B31(8-11) B30(8-11) B31(8-11) B34(8-11) B35(8-11) B34(8-11) B35(8-11) B38(8-11) B39(8-11) B38(8-11) B39(8-11) B3C(8-11) B3D(8-11) B3C(8-11) B3D(8-11) + const __m512i rhs_mat_2367ABEF_31_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_31, (_MM_PERM_ENUM)136); //B32(8-11) B33(8-11) B32(8-11) B33(8-11) B36(8-11) B37(8-11) B36(8-11) B37(8-11) B3A(8-11) B3B(8-11) B3A(8-11) B3B(8-11) B3E(8-11) B3F(8-11) B3E(8-11) B3F(8-11) + + const __m512i rhs_mat_014589CD_40_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_40, (_MM_PERM_ENUM)136); //B40(0-3) B41(0-3) B40(0-3) B41(0-3) B44(0-3) B45(0-3) B44(0-3) B45(0-3) B48(0-3) B49(0-3) B48(0-3) B49(0-3) B4C(0-3) B4D(0-3) B4C(0-3) B4D(0-3) + const __m512i rhs_mat_2367ABEF_40_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_40, (_MM_PERM_ENUM)136); //B42(0-3) B43(0-3) B42(0-3) B43(0-3) B46(0-3) B47(0-3) B46(0-3) B47(0-3) B4A(0-3) B4B(0-3) B4A(0-3) B4B(0-3) B4E(0-3) B4F(0-3) B4E(0-3) B4F(0-3) + + const __m512i rhs_mat_014589CD_41_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_41, (_MM_PERM_ENUM)136); //B40(8-11) B41(8-11) B40(8-11) B41(8-11) B44(8-11) B45(8-11) B44(8-11) B45(8-11) B48(8-11) B49(8-11) B48(8-11) B49(8-11) B4C(8-11) B4D(8-11) B4C(8-11) B4D(8-11) + const __m512i rhs_mat_2367ABEF_41_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_41, (_MM_PERM_ENUM)136); //B42(8-11) B43(8-11) B42(8-11) B43(8-11) B46(8-11) B47(8-11) B46(8-11) B47(8-11) B4A(8-11) B4B(8-11) B4A(8-11) B4B(8-11) B4E(8-11) B4F(8-11) B4E(8-11) B4F(8-11) + + const __m512i rhs_mat_014589CD_50_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_50, (_MM_PERM_ENUM)136); //B50(0-3) B51(0-3) B50(0-3) B51(0-3) B54(0-3) B55(0-3) B54(0-3) B55(0-3) B58(0-3) B59(0-3) B58(0-3) B59(0-3) B5C(0-3) B5D(0-3) B5C(0-3) B5D(0-3) + const __m512i rhs_mat_2367ABEF_50_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_50, (_MM_PERM_ENUM)136); //B52(0-3) B53(0-3) B52(0-3) B53(0-3) B56(0-3) B57(0-3) B56(0-3) B57(0-3) B5A(0-3) B5B(0-3) B5A(0-3) B5B(0-3) B5E(0-3) B5F(0-3) B5E(0-3) B5F(0-3) + + const __m512i rhs_mat_014589CD_51_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_51, (_MM_PERM_ENUM)136); //B50(8-11) B51(8-11) B50(8-11) B51(8-11) B54(8-11) B55(8-11) B54(8-11) B55(8-11) B58(8-11) B59(8-11) B58(8-11) B59(8-11) B5C(8-11) B5D(8-11) B5C(8-11) B5D(8-11) + const __m512i rhs_mat_2367ABEF_51_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_51, (_MM_PERM_ENUM)136); //B52(8-11) B53(8-11) B52(8-11) B53(8-11) B56(8-11) B57(8-11) B56(8-11) B57(8-11) B5A(8-11) B5B(8-11) B5A(8-11) B5B(8-11) B5E(8-11) B5F(8-11) B5E(8-11) B5F(8-11) + + const __m512i rhs_mat_014589CD_60_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_60, (_MM_PERM_ENUM)136); //B60(0-3) B61(0-3) B60(0-3) B61(0-3) B64(0-3) B65(0-3) B64(0-3) B65(0-3) B68(0-3) B69(0-3) B68(0-3) B69(0-3) B6C(0-3) B6D(0-3) B6C(0-3) B6D(0-3) + const __m512i rhs_mat_2367ABEF_60_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_60, (_MM_PERM_ENUM)136); //B62(0-3) B63(0-3) B62(0-3) B63(0-3) B66(0-3) B67(0-3) B66(0-3) B67(0-3) B6A(0-3) B6B(0-3) B6A(0-3) B6B(0-3) B6E(0-3) B6F(0-3) B6E(0-3) B6F(0-3) + + const __m512i rhs_mat_014589CD_61_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_61, (_MM_PERM_ENUM)136); //B60(8-11) B61(8-11) B60(8-11) B61(8-11) B64(8-11) B65(8-11) B64(8-11) B65(8-11) B68(8-11) B69(8-11) B68(8-11) B69(8-11) B6C(8-11) B6D(8-11) B6C(8-11) B6D(8-11) + const __m512i rhs_mat_2367ABEF_61_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_61, (_MM_PERM_ENUM)136); //B62(8-11) B63(8-11) B62(8-11) B63(8-11) B66(8-11) B67(8-11) B66(8-11) B67(8-11) B6A(8-11) B6B(8-11) B6A(8-11) B6B(8-11) B6E(8-11) B6F(8-11) B6E(8-11) B6F(8-11) + + const __m512i rhs_mat_014589CD_70_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_70, (_MM_PERM_ENUM)136); //B70(0-3) B71(0-3) B70(0-3) B71(0-3) B74(0-3) B75(0-3) B74(0-3) B75(0-3) B78(0-3) B79(0-3) B78(0-3) B79(0-3) B7C(0-3) B7D(0-3) B7C(0-3) B7D(0-3) + const __m512i rhs_mat_2367ABEF_70_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_70, (_MM_PERM_ENUM)136); //B72(0-3) B73(0-3) B72(0-3) B73(0-3) B76(0-3) B77(0-3) B76(0-3) B77(0-3) B7A(0-3) B7B(0-3) B7A(0-3) B7B(0-3) B7E(0-3) B7F(0-3) B7E(0-3) B7F(0-3) + + const __m512i rhs_mat_014589CD_71_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_71, (_MM_PERM_ENUM)136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) B08(8-11) B09(8-11) B08(8-11) B09(8-11) B0C(8-11) B0D(8-11) B0C(8-11) B0D(8-11) + const __m512i rhs_mat_2367ABEF_71_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_71, (_MM_PERM_ENUM)136); //B72(8-11) B73(8-11) B72(8-11) B73(8-11) B76(8-11) B77(8-11) B76(8-11) B77(8-11) B7A(8-11) B7B(8-11) B7A(8-11) B7B(8-11) B7E(8-11) B7F(8-11) B7E(8-11) B7F(8-11) + + const __m512i rhs_mat_014589CD_00_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_00, (_MM_PERM_ENUM)221); //B00(4-7) B01(4-7) B00(4-7) B01(4-7) B04(4-7) B05(4-7) B04(4-7) B05(4-7) B08(4-7) B09(4-7) B08(4-7) B09(4-7) B0C(4-7) B0D(4-7) B0C(4-7) B0D(4-7) + const __m512i rhs_mat_2367ABEF_00_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_00, (_MM_PERM_ENUM)221); //B02(4-7) B03(4-7) B02(4-7) B03(4-7) B06(4-7) B07(4-7) B06(4-7) B07(4-7) B0A(4-7) B0B(4-7) B0A(4-7) B0B(4-7) B0E(4-7) B0F(4-7) B0E(4-7) B0F(4-7) + + const __m512i rhs_mat_014589CD_01_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_01, (_MM_PERM_ENUM)221); //B00(12-15) B01(12-15) B00(12-15) B01(12-15) B04(12-15) B05(12-15) B04(12-15) B05(12-15) B08(12-15) B09(12-15) B08(12-15) B09(12-15) B0C(12-15) B0D(12-15) B0C(12-15) B0D(12-15) + const __m512i rhs_mat_2367ABEF_01_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_01, (_MM_PERM_ENUM)221); //B02(12-15) B03(12-15) B02(12-15) B03(12-15) B06(12-15) B07(12-15) B06(12-15) B07(12-15) B0A(12-15) B0B(12-15) B0A(12-15) B0B(12-15) B0E(12-15) B0F(12-15) B0E(12-15) B0F(12-15) + + const __m512i rhs_mat_014589CD_10_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_10, (_MM_PERM_ENUM)221); //B10(4-7) B11(4-7) B10(4-7) B11(4-7) B14(4-7) B15(4-7) B14(4-7) B15(4-7) B18(4-7) B19(4-7) B18(4-7) B19(4-7) B1C(4-7) B1D(4-7) B1C(4-7) B1D(4-7) + const __m512i rhs_mat_2367ABEF_10_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_10, (_MM_PERM_ENUM)221); //B12(4-7) B13(4-7) B12(4-7) B13(4-7) B16(4-7) B17(4-7) B16(4-7) B17(4-7) B1A(4-7) B1B(4-7) B1A(4-7) B1B(4-7) B1E(4-7) B1F(4-7) B1E(4-7) B1F(4-7) + + const __m512i rhs_mat_014589CD_11_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_11, (_MM_PERM_ENUM)221); //B10(12-15) B11(12-15) B10(12-15) B11(12-15) B14(12-15) B15(12-15) B14(12-15) B15(12-15) B18(12-15) B19(12-15) B18(12-15) B19(12-15) B1C(12-15) B1D(12-15) B1C(12-15) B1D(12-15) + const __m512i rhs_mat_2367ABEF_11_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_11, (_MM_PERM_ENUM)221); //B12(12-15) B13(12-15) B12(12-15) B13(12-15) B16(12-15) B17(12-15) B16(12-15) B17(12-15) B1A(12-15) B1B(12-15) B1A(12-15) B1B(12-15) B1E(12-15) B1F(12-15) B1E(12-15) B1F(12-15) + + const __m512i rhs_mat_014589CD_20_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_20, (_MM_PERM_ENUM)221); //B20(4-7) B21(4-7) B20(4-7) B21(4-7) B24(4-7) B25(4-7) B24(4-7) B25(4-7) B28(4-7) B29(4-7) B28(4-7) B29(4-7) B2C(4-7) B2D(4-7) B2C(4-7) B2D(4-7) + const __m512i rhs_mat_2367ABEF_20_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_20, (_MM_PERM_ENUM)221); //B22(4-7) B23(4-7) B22(4-7) B23(4-7) B26(4-7) B27(4-7) B26(4-7) B27(4-7) B2A(4-7) B2B(4-7) B2A(4-7) B2B(4-7) B2E(4-7) B2F(4-7) B2E(4-7) B2F(4-7) + + const __m512i rhs_mat_014589CD_21_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_21, (_MM_PERM_ENUM)221); //B20(12-15) B21(12-15) B20(12-15) B21(12-15) B24(12-15) B25(12-15) B24(12-15) B25(12-15) B28(12-15) B29(12-15) B28(12-15) B29(12-15) B2C(12-15) B2D(12-15) B2C(12-15) B2D(12-15) + const __m512i rhs_mat_2367ABEF_21_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_21, (_MM_PERM_ENUM)221); //B22(12-15) B23(12-15) B22(12-15) B23(12-15) B26(12-15) B27(12-15) B26(12-15) B27(12-15) B2A(12-15) B2B(12-15) B2A(12-15) B2B(12-15) B2E(12-15) B2F(12-15) B2E(12-15) B2F(12-15) + + const __m512i rhs_mat_014589CD_30_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_30, (_MM_PERM_ENUM)221); //B30(4-7) B31(4-7) B30(4-7) B31(4-7) B34(4-7) B35(4-7) B34(4-7) B35(4-7) B38(4-7) B39(4-7) B38(4-7) B39(4-7) B3C(4-7) B3D(4-7) B3C(4-7) B3D(4-7) + const __m512i rhs_mat_2367ABEF_30_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_30, (_MM_PERM_ENUM)221); //B32(4-7) B33(4-7) B32(4-7) B33(4-7) B36(4-7) B37(4-7) B36(4-7) B37(4-7) B3A(4-7) B3B(4-7) B3A(4-7) B3B(4-7) B3E(4-7) B3F(4-7) B3E(4-7) B3F(4-7) + + const __m512i rhs_mat_014589CD_31_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_31, (_MM_PERM_ENUM)221); //B30(12-15) B31(12-15) B30(12-15) B31(12-15) B34(12-15) B35(12-15) B34(12-15) B35(12-15) B38(12-15) B39(12-15) B38(12-15) B39(12-15) B3C(12-15) B3D(12-15) B3C(12-15) B3D(12-15) + const __m512i rhs_mat_2367ABEF_31_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_31, (_MM_PERM_ENUM)221); //B32(12-15) B33(12-15) B32(12-15) B33(12-15) B36(12-15) B37(12-15) B36(12-15) B37(12-15) B3A(12-15) B3B(12-15) B3A(12-15) B3B(12-15) B3E(12-15) B3F(12-15) B3E(12-15) B3F(12-15) + + const __m512i rhs_mat_014589CD_40_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_40, (_MM_PERM_ENUM)221); //B40(4-7) B41(4-7) B40(4-7) B41(4-7) B44(4-7) B45(4-7) B44(4-7) B45(4-7) B48(4-7) B49(4-7) B48(4-7) B49(4-7) B4C(4-7) B4D(4-7) B4C(4-7) B4D(4-7) + const __m512i rhs_mat_2367ABEF_40_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_40, (_MM_PERM_ENUM)221); //B42(4-7) B43(4-7) B42(4-7) B43(4-7) B46(4-7) B47(4-7) B46(4-7) B47(4-7) B4A(4-7) B4B(4-7) B4A(4-7) B4B(4-7) B4E(4-7) B4F(4-7) B4E(4-7) B4F(4-7) + + const __m512i rhs_mat_014589CD_41_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_41, (_MM_PERM_ENUM)221); //B40(12-15) B41(12-15) B40(12-15) B41(12-15) B44(12-15) B45(12-15) B44(12-15) B45(12-15) B48(12-15) B49(12-15) B48(12-15) B49(12-15) B4C(12-15) B4D(12-15) B4C(12-15) B4D(12-15) + const __m512i rhs_mat_2367ABEF_41_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_41, (_MM_PERM_ENUM)221); //B42(12-15) B43(12-15) B42(12-15) B43(12-15) B46(12-15) B47(12-15) B46(12-15) B47(12-15) B4A(12-15) B4B(12-15) B4A(12-15) B4B(12-15) B4E(12-15) B4F(12-15) B4E(12-15) B4F(12-15) + + const __m512i rhs_mat_014589CD_50_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_50, (_MM_PERM_ENUM)221); //B50(4-7) B51(4-7) B50(4-7) B51(4-7) B54(4-7) B55(4-7) B54(4-7) B55(4-7) B58(4-7) B59(4-7) B58(4-7) B59(4-7) B5C(4-7) B5D(4-7) B5C(4-7) B5D(4-7) + const __m512i rhs_mat_2367ABEF_50_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_50, (_MM_PERM_ENUM)221); //B52(4-7) B53(4-7) B52(4-7) B53(4-7) B56(4-7) B57(4-7) B56(4-7) B57(4-7) B5A(4-7) B5B(4-7) B5A(4-7) B5B(4-7) B5E(4-7) B5F(4-7) B5E(4-7) B5F(4-7) + + const __m512i rhs_mat_014589CD_51_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_51, (_MM_PERM_ENUM)221); //B50(12-15) B51(12-15) B50(12-15) B51(12-15) B54(12-15) B55(12-15) B54(12-15) B55(12-15) B58(12-15) B59(12-15) B58(12-15) B59(12-15) B5C(12-15) B5D(12-15) B5C(12-15) B5D(12-15) + const __m512i rhs_mat_2367ABEF_51_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_51, (_MM_PERM_ENUM)221); //B52(12-15) B53(12-15) B52(12-15) B53(12-15) B56(12-15) B57(12-15) B56(12-15) B57(12-15) B5A(12-15) B5B(12-15) B5A(12-15) B5B(12-15) B5E(12-15) B5F(12-15) B5E(12-15) B5F(12-15) + + const __m512i rhs_mat_014589CD_60_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_60, (_MM_PERM_ENUM)221); //B60(4-7) B61(4-7) B60(4-7) B61(4-7) B64(4-7) B65(4-7) B64(4-7) B65(4-7) B68(4-7) B69(4-7) B68(4-7) B69(4-7) B6C(4-7) B6D(4-7) B6C(4-7) B6D(4-7) + const __m512i rhs_mat_2367ABEF_60_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_60, (_MM_PERM_ENUM)221); //B62(4-7) B63(4-7) B62(4-7) B63(4-7) B66(4-7) B67(4-7) B66(4-7) B67(4-7) B6A(4-7) B6B(4-7) B6A(4-7) B6B(4-7) B6E(4-7) B6F(4-7) B6E(4-7) B6F(4-7) + + const __m512i rhs_mat_014589CD_61_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_61, (_MM_PERM_ENUM)221); //B60(12-15) B61(12-15) B60(12-15) B61(12-15) B64(12-15) B65(12-15) B64(12-15) B65(12-15) B68(12-15) B69(12-15) B68(12-15) B69(12-15) B6C(12-15) B6D(12-15) B6C(12-15) B6D(12-15) + const __m512i rhs_mat_2367ABEF_61_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_61, (_MM_PERM_ENUM)221); //B62(12-15) B63(12-15) B62(12-15) B63(12-15) B66(12-15) B67(12-15) B66(12-15) B67(12-15) B6A(12-15) B6B(12-15) B6A(12-15) B6B(12-15) B6E(12-15) B6F(12-15) B6E(12-15) B6F(12-15) + + const __m512i rhs_mat_014589CD_70_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_70, (_MM_PERM_ENUM)221); //B70(4-7) B71(4-7) B70(4-7) B71(4-7) B74(4-7) B75(4-7) B74(4-7) B75(4-7) B78(4-7) B79(4-7) B78(4-7) B79(4-7) B7C(4-7) B7D(4-7) B7C(4-7) B7D(4-7) + const __m512i rhs_mat_2367ABEF_70_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_70, (_MM_PERM_ENUM)221); //B72(4-7) B73(4-7) B72(4-7) B73(4-7) B76(4-7) B77(4-7) B76(4-7) B77(4-7) B7A(4-7) B7B(4-7) B7A(4-7) B7B(4-7) B7E(4-7) B7F(4-7) B7E(4-7) B7F(4-7) + + const __m512i rhs_mat_014589CD_71_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_71, (_MM_PERM_ENUM)221); //B70(12-15) B71(12-15) B70(12-15) B71(12-15) B74(12-15) B75(12-15) B74(12-15) B75(12-15) B78(12-15) B79(12-15) B78(12-15) B79(12-15) B7C(12-15) B7D(12-15) B7C(12-15) B7D(12-15) + const __m512i rhs_mat_2367ABEF_71_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_71, (_MM_PERM_ENUM)221); //B72(12-15) B73(12-15) B72(12-15) B73(12-15) B76(12-15) B77(12-15) B76(12-15) B77(12-15) B7A(12-15) B7B(12-15) B7A(12-15) B7B(12-15) B7E(12-15) B7F(12-15) B7E(12-15) B7F(12-15) + + //notation:superblock subblock + //s00 m00 s01 m01 s10 m10 s11 m11 s20 m20 s21 m21 s30 m30 s31 m31 s40 m40 s41 m41 s50 m50 s51 m51 s60 m60 s61 m61 s70 m70 s71 m71 + + const __m128i mins_and_scales_01_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + sb * 64)); + const __m128i mins_and_scales_23_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 48 + sb * 64)); + + const __m128i mins_and_scales_01_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + sb * 64)); + const __m128i mins_and_scales_23_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 48 + sb * 64)); + + // Combine mins and scales for sub-blocks: 0-1, 2-3, 4-5, 6-7 in the sb loop + const __m256i mins_and_scales_01 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_01_0), mins_and_scales_01_1, 1); + const __m256i mins_and_scales_23 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_23_0), mins_and_scales_23_1, 1); + const __m256i mins_and_scales_45 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_45_0), mins_and_scales_45_1, 1); + const __m256i mins_and_scales_67 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_67_0), mins_and_scales_67_1, 1); + + // Extract scales which is lower half from mins_and_scales + const __m256i scales_01 = _mm256_and_si256(mins_and_scales_01, m4b); + const __m256i scales_23 = _mm256_and_si256(mins_and_scales_23, m4b); + const __m256i scales_45 = _mm256_and_si256(mins_and_scales_45, m4b); + const __m256i scales_67 = _mm256_and_si256(mins_and_scales_67, m4b); + + // Extract mins which is upper half from mins_and_scales + const __m512i mins_01 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_01, 4), m4b)); + const __m512i mins_23 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_23, 4), m4b)); + const __m512i mins_45 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_45, 4), m4b)); + const __m512i mins_67 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_67, 4), m4b)); + + const __m512i scales_0 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_01, scalesmask1)); + const __m512i scales_1 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_01, scalesmask2)); + const __m512i scales_2 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_23, scalesmask1)); + const __m512i scales_3 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_23, scalesmask2)); + const __m512i scales_4 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_45, scalesmask1)); + const __m512i scales_5 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_45, scalesmask2)); + const __m512i scales_6 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_67, scalesmask1)); + const __m512i scales_7 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_67, scalesmask2)); + + const __m512i scale_014589CD_0 = _mm512_shuffle_epi32(scales_0, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_0 = _mm512_shuffle_epi32(scales_0, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_1 = _mm512_shuffle_epi32(scales_1, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_1 = _mm512_shuffle_epi32(scales_1, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_2 = _mm512_shuffle_epi32(scales_2, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_2 = _mm512_shuffle_epi32(scales_2, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_3 = _mm512_shuffle_epi32(scales_3, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_3 = _mm512_shuffle_epi32(scales_3, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_4 = _mm512_shuffle_epi32(scales_4, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_4 = _mm512_shuffle_epi32(scales_4, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_5 = _mm512_shuffle_epi32(scales_5, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_5 = _mm512_shuffle_epi32(scales_5, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_6 = _mm512_shuffle_epi32(scales_6, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_6 = _mm512_shuffle_epi32(scales_6, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_7 = _mm512_shuffle_epi32(scales_7, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_7 = _mm512_shuffle_epi32(scales_7, (_MM_PERM_ENUM)238); + + // Load the four block_q8_k quantized values interleaved with each other in chunks of eight bytes - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated into a 256 bit vector + __m256i lhs_mat_ymm_0123_00 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 512 * sb))); + __m256i lhs_mat_ymm_01_00 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_00, lhs_mat_ymm_0123_00, 0); + __m256i lhs_mat_ymm_23_00 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_00, lhs_mat_ymm_0123_00, 17); + __m256i lhs_mat_ymm_0123_01 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 32 + 512 * sb))); + __m256i lhs_mat_ymm_01_01 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_01, lhs_mat_ymm_0123_01, 0); + __m256i lhs_mat_ymm_23_01 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_01, lhs_mat_ymm_0123_01, 17); + __m256i lhs_mat_ymm_0123_10 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 64 + 512 * sb))); + __m256i lhs_mat_ymm_01_10 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_10, lhs_mat_ymm_0123_10, 0); + __m256i lhs_mat_ymm_23_10 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_10, lhs_mat_ymm_0123_10, 17); + __m256i lhs_mat_ymm_0123_11 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 96 + 512 * sb))); + __m256i lhs_mat_ymm_01_11 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_11, lhs_mat_ymm_0123_11, 0); + __m256i lhs_mat_ymm_23_11 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_11, lhs_mat_ymm_0123_11, 17); + __m256i lhs_mat_ymm_0123_20 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 128 + 512 * sb))); + __m256i lhs_mat_ymm_01_20 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_20, lhs_mat_ymm_0123_20, 0); + __m256i lhs_mat_ymm_23_20 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_20, lhs_mat_ymm_0123_20, 17); + __m256i lhs_mat_ymm_0123_21 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 160 + 512 * sb))); + __m256i lhs_mat_ymm_01_21 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_21, lhs_mat_ymm_0123_21, 0); + __m256i lhs_mat_ymm_23_21 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_21, lhs_mat_ymm_0123_21, 17); + __m256i lhs_mat_ymm_0123_30 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 192 + 512 * sb))); + __m256i lhs_mat_ymm_01_30 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_30, lhs_mat_ymm_0123_30, 0); + __m256i lhs_mat_ymm_23_30 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_30, lhs_mat_ymm_0123_30, 17); + __m256i lhs_mat_ymm_0123_31 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 224 + 512 * sb))); + __m256i lhs_mat_ymm_01_31 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_31, lhs_mat_ymm_0123_31, 0); + __m256i lhs_mat_ymm_23_31 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_31, lhs_mat_ymm_0123_31, 17); + + __m256i lhs_mat_ymm_0123_40 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 256 + 512 * sb))); + __m256i lhs_mat_ymm_01_40 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_40, lhs_mat_ymm_0123_40, 0); + __m256i lhs_mat_ymm_23_40 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_40, lhs_mat_ymm_0123_40, 17); + __m256i lhs_mat_ymm_0123_41 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 288 + 512 * sb))); + __m256i lhs_mat_ymm_01_41 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_41, lhs_mat_ymm_0123_41, 0); + __m256i lhs_mat_ymm_23_41 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_41, lhs_mat_ymm_0123_41, 17); + __m256i lhs_mat_ymm_0123_50 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 320 + 512 * sb))); + __m256i lhs_mat_ymm_01_50 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_50, lhs_mat_ymm_0123_50, 0); + __m256i lhs_mat_ymm_23_50 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_50, lhs_mat_ymm_0123_50, 17); + __m256i lhs_mat_ymm_0123_51 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 352 + 512 * sb))); + __m256i lhs_mat_ymm_01_51 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_51, lhs_mat_ymm_0123_51, 0); + __m256i lhs_mat_ymm_23_51 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_51, lhs_mat_ymm_0123_51, 17); + __m256i lhs_mat_ymm_0123_60 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 384 + 512 * sb))); + __m256i lhs_mat_ymm_01_60 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_60, lhs_mat_ymm_0123_60, 0); + __m256i lhs_mat_ymm_23_60 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_60, lhs_mat_ymm_0123_60, 17); + __m256i lhs_mat_ymm_0123_61 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 416 + 512 * sb))); + __m256i lhs_mat_ymm_01_61 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_61, lhs_mat_ymm_0123_61, 0); + __m256i lhs_mat_ymm_23_61 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_61, lhs_mat_ymm_0123_61, 17); + __m256i lhs_mat_ymm_0123_70 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 448 + 512 * sb))); + __m256i lhs_mat_ymm_01_70 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_70, lhs_mat_ymm_0123_70, 0); + __m256i lhs_mat_ymm_23_70 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_70, lhs_mat_ymm_0123_70, 17); + __m256i lhs_mat_ymm_0123_71 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 480 + 512 * sb))); + __m256i lhs_mat_ymm_01_71 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_71, lhs_mat_ymm_0123_71, 0); + __m256i lhs_mat_ymm_23_71 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_71, lhs_mat_ymm_0123_71, 17); + + __m512i lhs_mat_01_00 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_00), lhs_mat_ymm_01_00, 1); + __m512i lhs_mat_23_00 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_00), lhs_mat_ymm_23_00, 1); + __m512i lhs_mat_01_01 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_01), lhs_mat_ymm_01_01, 1); + __m512i lhs_mat_23_01 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_01), lhs_mat_ymm_23_01, 1); + + __m512i lhs_mat_01_10 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_10), lhs_mat_ymm_01_10, 1); + __m512i lhs_mat_23_10 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_10), lhs_mat_ymm_23_10, 1); + __m512i lhs_mat_01_11 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_11), lhs_mat_ymm_01_11, 1); + __m512i lhs_mat_23_11 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_11), lhs_mat_ymm_23_11, 1); + + __m512i lhs_mat_01_20 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_20), lhs_mat_ymm_01_20, 1); + __m512i lhs_mat_23_20 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_20), lhs_mat_ymm_23_20, 1); + __m512i lhs_mat_01_21 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_21), lhs_mat_ymm_01_21, 1); + __m512i lhs_mat_23_21 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_21), lhs_mat_ymm_23_21, 1); + + __m512i lhs_mat_01_30 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_30), lhs_mat_ymm_01_30, 1); + __m512i lhs_mat_23_30 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_30), lhs_mat_ymm_23_30, 1); + __m512i lhs_mat_01_31 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_31), lhs_mat_ymm_01_31, 1); + __m512i lhs_mat_23_31 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_31), lhs_mat_ymm_23_31, 1); + + __m512i lhs_mat_01_40 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_40), lhs_mat_ymm_01_40, 1); + __m512i lhs_mat_23_40 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_40), lhs_mat_ymm_23_40, 1); + __m512i lhs_mat_01_41 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_41), lhs_mat_ymm_01_41, 1); + __m512i lhs_mat_23_41 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_41), lhs_mat_ymm_23_41, 1); + + __m512i lhs_mat_01_50 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_50), lhs_mat_ymm_01_50, 1); + __m512i lhs_mat_23_50 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_50), lhs_mat_ymm_23_50, 1); + __m512i lhs_mat_01_51 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_51), lhs_mat_ymm_01_51, 1); + __m512i lhs_mat_23_51 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_51), lhs_mat_ymm_23_51, 1); + + __m512i lhs_mat_01_60 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_60), lhs_mat_ymm_01_60, 1); + __m512i lhs_mat_23_60 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_60), lhs_mat_ymm_23_60, 1); + __m512i lhs_mat_01_61 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_61), lhs_mat_ymm_01_61, 1); + __m512i lhs_mat_23_61 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_61), lhs_mat_ymm_23_61, 1); + + __m512i lhs_mat_01_70 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_70), lhs_mat_ymm_01_70, 1); + __m512i lhs_mat_23_70 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_70), lhs_mat_ymm_23_70, 1); + __m512i lhs_mat_01_71 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_71), lhs_mat_ymm_01_71, 1); + __m512i lhs_mat_23_71 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_71), lhs_mat_ymm_23_71, 1); + + // Bsums are loaded for the different Q8_K blocks + __m128i lhs_raw_bsums_01_0123 = _mm_loadu_si128((const __m128i *)((a_ptr[b].bsums + 32 * sb))); + __m128i lhs_raw_bsums_23_0123 = _mm_loadu_si128((const __m128i *)(a_ptr[b].bsums + 8 + 32 * sb)); + __m128i lhs_raw_bsums_01_4567 = _mm_loadu_si128((const __m128i *)((a_ptr[b].bsums + 16 + 32 * sb))); + __m128i lhs_raw_bsums_23_4567 = _mm_loadu_si128((const __m128i *)(a_ptr[b].bsums + 24 + 32 * sb)); + + __m256i lhs_bsums_ymm_01_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_0123), lhs_raw_bsums_01_0123, 1); + __m512i lhs_bsums_01_0123 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_01_0123), lhs_bsums_ymm_01_0123, 1); + __m256i lhs_bsums_ymm_23_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_0123), lhs_raw_bsums_23_0123, 1); + __m512i lhs_bsums_23_0123 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_23_0123), lhs_bsums_ymm_23_0123, 1); + __m256i lhs_bsums_ymm_01_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_4567), lhs_raw_bsums_01_4567, 1); + __m512i lhs_bsums_01_4567 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_01_4567), lhs_bsums_ymm_01_4567, 1); + __m256i lhs_bsums_ymm_23_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_4567), lhs_raw_bsums_23_4567, 1); + __m512i lhs_bsums_23_4567 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_23_4567), lhs_bsums_ymm_23_4567, 1); + + // Shuffle pattern one - left side input + const __m512i lhs_mat_01_00_sp1 = _mm512_shuffle_epi32(lhs_mat_01_00, (_MM_PERM_ENUM)160); //A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) + const __m512i lhs_mat_23_00_sp1 = _mm512_shuffle_epi32(lhs_mat_23_00, (_MM_PERM_ENUM)160); //A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) + + const __m512i lhs_mat_01_01_sp1 = _mm512_shuffle_epi32(lhs_mat_01_01, (_MM_PERM_ENUM)160); //A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) + const __m512i lhs_mat_23_01_sp1 = _mm512_shuffle_epi32(lhs_mat_23_01, (_MM_PERM_ENUM)160); //A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) + + const __m512i lhs_mat_01_10_sp1 = _mm512_shuffle_epi32(lhs_mat_01_10, (_MM_PERM_ENUM)160); //A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) + const __m512i lhs_mat_23_10_sp1 = _mm512_shuffle_epi32(lhs_mat_23_10, (_MM_PERM_ENUM)160); //A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) + + const __m512i lhs_mat_01_11_sp1 = _mm512_shuffle_epi32(lhs_mat_01_11, (_MM_PERM_ENUM)160); //A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) + const __m512i lhs_mat_23_11_sp1 = _mm512_shuffle_epi32(lhs_mat_23_11, (_MM_PERM_ENUM)160); //A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) + + const __m512i lhs_mat_01_20_sp1 = _mm512_shuffle_epi32(lhs_mat_01_20, (_MM_PERM_ENUM)160); //A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) + const __m512i lhs_mat_23_20_sp1 = _mm512_shuffle_epi32(lhs_mat_23_20, (_MM_PERM_ENUM)160); //A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) + + const __m512i lhs_mat_01_21_sp1 = _mm512_shuffle_epi32(lhs_mat_01_21, (_MM_PERM_ENUM)160); //A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) + const __m512i lhs_mat_23_21_sp1 = _mm512_shuffle_epi32(lhs_mat_23_21, (_MM_PERM_ENUM)160); //A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) + + const __m512i lhs_mat_01_30_sp1 = _mm512_shuffle_epi32(lhs_mat_01_30, (_MM_PERM_ENUM)160); //A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) + const __m512i lhs_mat_23_30_sp1 = _mm512_shuffle_epi32(lhs_mat_23_30, (_MM_PERM_ENUM)160); //A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) + + const __m512i lhs_mat_01_31_sp1 = _mm512_shuffle_epi32(lhs_mat_01_31, (_MM_PERM_ENUM)160); //A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) + const __m512i lhs_mat_23_31_sp1 = _mm512_shuffle_epi32(lhs_mat_23_31, (_MM_PERM_ENUM)160); //A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) + + const __m512i lhs_mat_01_40_sp1 = _mm512_shuffle_epi32(lhs_mat_01_40, (_MM_PERM_ENUM)160); //A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) + const __m512i lhs_mat_23_40_sp1 = _mm512_shuffle_epi32(lhs_mat_23_40, (_MM_PERM_ENUM)160); //A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) + + const __m512i lhs_mat_01_41_sp1 = _mm512_shuffle_epi32(lhs_mat_01_41, (_MM_PERM_ENUM)160); //A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) + const __m512i lhs_mat_23_41_sp1 = _mm512_shuffle_epi32(lhs_mat_23_41, (_MM_PERM_ENUM)160); //A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) + + const __m512i lhs_mat_01_50_sp1 = _mm512_shuffle_epi32(lhs_mat_01_50, (_MM_PERM_ENUM)160); //A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) + const __m512i lhs_mat_23_50_sp1 = _mm512_shuffle_epi32(lhs_mat_23_50, (_MM_PERM_ENUM)160); //A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) + + const __m512i lhs_mat_01_51_sp1 = _mm512_shuffle_epi32(lhs_mat_01_51, (_MM_PERM_ENUM)160); //A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) + const __m512i lhs_mat_23_51_sp1 = _mm512_shuffle_epi32(lhs_mat_23_51, (_MM_PERM_ENUM)160); //A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) + + const __m512i lhs_mat_01_60_sp1 = _mm512_shuffle_epi32(lhs_mat_01_60, (_MM_PERM_ENUM)160); //A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) + const __m512i lhs_mat_23_60_sp1 = _mm512_shuffle_epi32(lhs_mat_23_60, (_MM_PERM_ENUM)160); //A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) + + const __m512i lhs_mat_01_61_sp1 = _mm512_shuffle_epi32(lhs_mat_01_61, (_MM_PERM_ENUM)160); //A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) + const __m512i lhs_mat_23_61_sp1 = _mm512_shuffle_epi32(lhs_mat_23_61, (_MM_PERM_ENUM)160); //A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) + + const __m512i lhs_mat_01_70_sp1 = _mm512_shuffle_epi32(lhs_mat_01_70, (_MM_PERM_ENUM)160); //A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) + const __m512i lhs_mat_23_70_sp1 = _mm512_shuffle_epi32(lhs_mat_23_70, (_MM_PERM_ENUM)160); //A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) + + const __m512i lhs_mat_01_71_sp1 = _mm512_shuffle_epi32(lhs_mat_01_71, (_MM_PERM_ENUM)160); //A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) + const __m512i lhs_mat_23_71_sp1 = _mm512_shuffle_epi32(lhs_mat_23_71, (_MM_PERM_ENUM)160); //A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) + + const __m512i lhs_mat_01_00_sp2 = _mm512_shuffle_epi32(lhs_mat_01_00, (_MM_PERM_ENUM)245); //A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) + const __m512i lhs_mat_23_00_sp2 = _mm512_shuffle_epi32(lhs_mat_23_00, (_MM_PERM_ENUM)245); //A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) + + const __m512i lhs_mat_01_01_sp2 = _mm512_shuffle_epi32(lhs_mat_01_01, (_MM_PERM_ENUM)245); //A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) + const __m512i lhs_mat_23_01_sp2 = _mm512_shuffle_epi32(lhs_mat_23_01, (_MM_PERM_ENUM)245); //A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) + + const __m512i lhs_mat_01_10_sp2 = _mm512_shuffle_epi32(lhs_mat_01_10, (_MM_PERM_ENUM)245); //A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) + const __m512i lhs_mat_23_10_sp2 = _mm512_shuffle_epi32(lhs_mat_23_10, (_MM_PERM_ENUM)245); //A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) + + const __m512i lhs_mat_01_11_sp2 = _mm512_shuffle_epi32(lhs_mat_01_11, (_MM_PERM_ENUM)245); //A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) + const __m512i lhs_mat_23_11_sp2 = _mm512_shuffle_epi32(lhs_mat_23_11, (_MM_PERM_ENUM)245); //A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) + + const __m512i lhs_mat_01_20_sp2 = _mm512_shuffle_epi32(lhs_mat_01_20, (_MM_PERM_ENUM)245); //A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) + const __m512i lhs_mat_23_20_sp2 = _mm512_shuffle_epi32(lhs_mat_23_20, (_MM_PERM_ENUM)245); //A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) + + const __m512i lhs_mat_01_21_sp2 = _mm512_shuffle_epi32(lhs_mat_01_21, (_MM_PERM_ENUM)245); //A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) + const __m512i lhs_mat_23_21_sp2 = _mm512_shuffle_epi32(lhs_mat_23_21, (_MM_PERM_ENUM)245); //A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) + + const __m512i lhs_mat_01_30_sp2 = _mm512_shuffle_epi32(lhs_mat_01_30, (_MM_PERM_ENUM)245); //A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) + const __m512i lhs_mat_23_30_sp2 = _mm512_shuffle_epi32(lhs_mat_23_30, (_MM_PERM_ENUM)245); //A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) + + const __m512i lhs_mat_01_31_sp2 = _mm512_shuffle_epi32(lhs_mat_01_31, (_MM_PERM_ENUM)245); //A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) + const __m512i lhs_mat_23_31_sp2 = _mm512_shuffle_epi32(lhs_mat_23_31, (_MM_PERM_ENUM)245); //A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) + + const __m512i lhs_mat_01_40_sp2 = _mm512_shuffle_epi32(lhs_mat_01_40, (_MM_PERM_ENUM)245); //A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) + const __m512i lhs_mat_23_40_sp2 = _mm512_shuffle_epi32(lhs_mat_23_40, (_MM_PERM_ENUM)245); //A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) + + const __m512i lhs_mat_01_41_sp2 = _mm512_shuffle_epi32(lhs_mat_01_41, (_MM_PERM_ENUM)245); //A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) + const __m512i lhs_mat_23_41_sp2 = _mm512_shuffle_epi32(lhs_mat_23_41, (_MM_PERM_ENUM)245); //A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) + + const __m512i lhs_mat_01_50_sp2 = _mm512_shuffle_epi32(lhs_mat_01_50, (_MM_PERM_ENUM)245); //A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) + const __m512i lhs_mat_23_50_sp2 = _mm512_shuffle_epi32(lhs_mat_23_50, (_MM_PERM_ENUM)245); //A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) + + const __m512i lhs_mat_01_51_sp2 = _mm512_shuffle_epi32(lhs_mat_01_51, (_MM_PERM_ENUM)245); //A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) + const __m512i lhs_mat_23_51_sp2 = _mm512_shuffle_epi32(lhs_mat_23_51, (_MM_PERM_ENUM)245); //A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) + + const __m512i lhs_mat_01_60_sp2 = _mm512_shuffle_epi32(lhs_mat_01_60, (_MM_PERM_ENUM)245); //A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) + const __m512i lhs_mat_23_60_sp2 = _mm512_shuffle_epi32(lhs_mat_23_60, (_MM_PERM_ENUM)245); //A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) + + const __m512i lhs_mat_01_61_sp2 = _mm512_shuffle_epi32(lhs_mat_01_61, (_MM_PERM_ENUM)245); //A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) + const __m512i lhs_mat_23_61_sp2 = _mm512_shuffle_epi32(lhs_mat_23_61, (_MM_PERM_ENUM)245); //A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) + + const __m512i lhs_mat_01_70_sp2 = _mm512_shuffle_epi32(lhs_mat_01_70, (_MM_PERM_ENUM)245); //A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) + const __m512i lhs_mat_23_70_sp2 = _mm512_shuffle_epi32(lhs_mat_23_70, (_MM_PERM_ENUM)245); //A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) + + const __m512i lhs_mat_01_71_sp2 = _mm512_shuffle_epi32(lhs_mat_01_71, (_MM_PERM_ENUM)245); //A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) + const __m512i lhs_mat_23_71_sp2 = _mm512_shuffle_epi32(lhs_mat_23_71, (_MM_PERM_ENUM)245); //A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + __m512i iacc_mat_00_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp1, lhs_mat_01_00_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp1, lhs_mat_01_01_sp1)); + __m512i iacc_mat_01_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp1, lhs_mat_01_00_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp1, lhs_mat_01_01_sp1)); + + __m512i iacc_mat_10_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp1, lhs_mat_23_00_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp1, lhs_mat_23_01_sp1)); + __m512i iacc_mat_11_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp1, lhs_mat_23_00_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp1, lhs_mat_23_01_sp1)); + + __m512i iacc_mat_00_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp1, lhs_mat_01_10_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp1, lhs_mat_01_11_sp1)); + __m512i iacc_mat_01_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp1, lhs_mat_01_10_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp1, lhs_mat_01_11_sp1)); + + __m512i iacc_mat_10_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp1, lhs_mat_23_10_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp1, lhs_mat_23_11_sp1)); + __m512i iacc_mat_11_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp1, lhs_mat_23_10_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp1, lhs_mat_23_11_sp1)); + + __m512i iacc_mat_00_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp1, lhs_mat_01_20_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp1, lhs_mat_01_21_sp1)); + __m512i iacc_mat_01_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp1, lhs_mat_01_20_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp1, lhs_mat_01_21_sp1)); + + __m512i iacc_mat_10_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp1, lhs_mat_23_20_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp1, lhs_mat_23_21_sp1)); + __m512i iacc_mat_11_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp1, lhs_mat_23_20_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp1, lhs_mat_23_21_sp1)); + + __m512i iacc_mat_00_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp1, lhs_mat_01_30_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp1, lhs_mat_01_31_sp1)); + __m512i iacc_mat_01_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp1, lhs_mat_01_30_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp1, lhs_mat_01_31_sp1)); + + __m512i iacc_mat_10_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp1, lhs_mat_23_30_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp1, lhs_mat_23_31_sp1)); + __m512i iacc_mat_11_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp1, lhs_mat_23_30_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp1, lhs_mat_23_31_sp1)); + + __m512i iacc_mat_00_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp1, lhs_mat_01_40_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp1, lhs_mat_01_41_sp1)); + __m512i iacc_mat_01_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp1, lhs_mat_01_40_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp1, lhs_mat_01_41_sp1)); + + __m512i iacc_mat_10_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp1, lhs_mat_23_40_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp1, lhs_mat_23_41_sp1)); + __m512i iacc_mat_11_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp1, lhs_mat_23_40_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp1, lhs_mat_23_41_sp1)); + + __m512i iacc_mat_00_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp1, lhs_mat_01_50_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp1, lhs_mat_01_51_sp1)); + __m512i iacc_mat_01_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp1, lhs_mat_01_50_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp1, lhs_mat_01_51_sp1)); + + __m512i iacc_mat_10_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp1, lhs_mat_23_50_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp1, lhs_mat_23_51_sp1)); + __m512i iacc_mat_11_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp1, lhs_mat_23_50_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp1, lhs_mat_23_51_sp1)); + + __m512i iacc_mat_00_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp1, lhs_mat_01_60_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp1, lhs_mat_01_61_sp1)); + __m512i iacc_mat_01_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp1, lhs_mat_01_60_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp1, lhs_mat_01_61_sp1)); + + __m512i iacc_mat_10_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp1, lhs_mat_23_60_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp1, lhs_mat_23_61_sp1)); + __m512i iacc_mat_11_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp1, lhs_mat_23_60_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp1, lhs_mat_23_61_sp1)); + + __m512i iacc_mat_00_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp1, lhs_mat_01_70_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp1, lhs_mat_01_71_sp1)); + __m512i iacc_mat_01_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp1, lhs_mat_01_70_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp1, lhs_mat_01_71_sp1)); + + __m512i iacc_mat_10_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp1, lhs_mat_23_70_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp1, lhs_mat_23_71_sp1)); + __m512i iacc_mat_11_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp1, lhs_mat_23_70_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp1, lhs_mat_23_71_sp1)); + + + __m512i iacc_mat_00_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp2, lhs_mat_01_00_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp2, lhs_mat_01_01_sp2)); + __m512i iacc_mat_01_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp2, lhs_mat_01_00_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp2, lhs_mat_01_01_sp2)); + + __m512i iacc_mat_10_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp2, lhs_mat_23_00_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp2, lhs_mat_23_01_sp2)); + __m512i iacc_mat_11_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp2, lhs_mat_23_00_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp2, lhs_mat_23_01_sp2)); + + __m512i iacc_mat_00_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp2, lhs_mat_01_10_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp2, lhs_mat_01_11_sp2)); + __m512i iacc_mat_01_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp2, lhs_mat_01_10_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp2, lhs_mat_01_11_sp2)); + + __m512i iacc_mat_10_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp2, lhs_mat_23_10_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp2, lhs_mat_23_11_sp2)); + __m512i iacc_mat_11_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp2, lhs_mat_23_10_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp2, lhs_mat_23_11_sp2)); + + __m512i iacc_mat_00_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp2, lhs_mat_01_20_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp2, lhs_mat_01_21_sp2)); + __m512i iacc_mat_01_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp2, lhs_mat_01_20_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp2, lhs_mat_01_21_sp2)); + + __m512i iacc_mat_10_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp2, lhs_mat_23_20_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp2, lhs_mat_23_21_sp2)); + __m512i iacc_mat_11_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp2, lhs_mat_23_20_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp2, lhs_mat_23_21_sp2)); + + __m512i iacc_mat_00_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp2, lhs_mat_01_30_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp2, lhs_mat_01_31_sp2)); + __m512i iacc_mat_01_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp2, lhs_mat_01_30_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp2, lhs_mat_01_31_sp2)); + + __m512i iacc_mat_10_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp2, lhs_mat_23_30_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp2, lhs_mat_23_31_sp2)); + __m512i iacc_mat_11_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp2, lhs_mat_23_30_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp2, lhs_mat_23_31_sp2)); + + __m512i iacc_mat_00_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp2, lhs_mat_01_40_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp2, lhs_mat_01_41_sp2)); + __m512i iacc_mat_01_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp2, lhs_mat_01_40_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp2, lhs_mat_01_41_sp2)); + + __m512i iacc_mat_10_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp2, lhs_mat_23_40_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp2, lhs_mat_23_41_sp2)); + __m512i iacc_mat_11_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp2, lhs_mat_23_40_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp2, lhs_mat_23_41_sp2)); + + __m512i iacc_mat_00_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp2, lhs_mat_01_50_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp2, lhs_mat_01_51_sp2)); + __m512i iacc_mat_01_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp2, lhs_mat_01_50_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp2, lhs_mat_01_51_sp2)); + + __m512i iacc_mat_10_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp2, lhs_mat_23_50_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp2, lhs_mat_23_51_sp2)); + __m512i iacc_mat_11_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp2, lhs_mat_23_50_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp2, lhs_mat_23_51_sp2)); + + __m512i iacc_mat_00_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp2, lhs_mat_01_60_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp2, lhs_mat_01_61_sp2)); + __m512i iacc_mat_01_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp2, lhs_mat_01_60_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp2, lhs_mat_01_61_sp2)); + + __m512i iacc_mat_10_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp2, lhs_mat_23_60_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp2, lhs_mat_23_61_sp2)); + __m512i iacc_mat_11_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp2, lhs_mat_23_60_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp2, lhs_mat_23_61_sp2)); + + __m512i iacc_mat_00_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp2, lhs_mat_01_70_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp2, lhs_mat_01_71_sp2)); + __m512i iacc_mat_01_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp2, lhs_mat_01_70_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp2, lhs_mat_01_71_sp2)); + + __m512i iacc_mat_10_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp2, lhs_mat_23_70_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp2, lhs_mat_23_71_sp2)); + __m512i iacc_mat_11_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp2, lhs_mat_23_70_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp2, lhs_mat_23_71_sp2)); + + // Combine results from both shuffle patterns for each output block + __m512i iacc_mat_00_0 = _mm512_add_epi16(iacc_mat_00_0_sp1, iacc_mat_00_0_sp2); + __m512i iacc_mat_01_0 = _mm512_add_epi16(iacc_mat_01_0_sp1, iacc_mat_01_0_sp2); + __m512i iacc_mat_10_0 = _mm512_add_epi16(iacc_mat_10_0_sp1, iacc_mat_10_0_sp2); + __m512i iacc_mat_11_0 = _mm512_add_epi16(iacc_mat_11_0_sp1, iacc_mat_11_0_sp2); + + __m512i iacc_mat_00_1 = _mm512_add_epi16(iacc_mat_00_1_sp1, iacc_mat_00_1_sp2); + __m512i iacc_mat_01_1 = _mm512_add_epi16(iacc_mat_01_1_sp1, iacc_mat_01_1_sp2); + __m512i iacc_mat_10_1 = _mm512_add_epi16(iacc_mat_10_1_sp1, iacc_mat_10_1_sp2); + __m512i iacc_mat_11_1 = _mm512_add_epi16(iacc_mat_11_1_sp1, iacc_mat_11_1_sp2); + + __m512i iacc_mat_00_2 = _mm512_add_epi16(iacc_mat_00_2_sp1, iacc_mat_00_2_sp2); + __m512i iacc_mat_01_2 = _mm512_add_epi16(iacc_mat_01_2_sp1, iacc_mat_01_2_sp2); + __m512i iacc_mat_10_2 = _mm512_add_epi16(iacc_mat_10_2_sp1, iacc_mat_10_2_sp2); + __m512i iacc_mat_11_2 = _mm512_add_epi16(iacc_mat_11_2_sp1, iacc_mat_11_2_sp2); + + __m512i iacc_mat_00_3 = _mm512_add_epi16(iacc_mat_00_3_sp1, iacc_mat_00_3_sp2); + __m512i iacc_mat_01_3 = _mm512_add_epi16(iacc_mat_01_3_sp1, iacc_mat_01_3_sp2); + __m512i iacc_mat_10_3 = _mm512_add_epi16(iacc_mat_10_3_sp1, iacc_mat_10_3_sp2); + __m512i iacc_mat_11_3 = _mm512_add_epi16(iacc_mat_11_3_sp1, iacc_mat_11_3_sp2); + + __m512i iacc_mat_00_4 = _mm512_add_epi16(iacc_mat_00_4_sp1, iacc_mat_00_4_sp2); + __m512i iacc_mat_01_4 = _mm512_add_epi16(iacc_mat_01_4_sp1, iacc_mat_01_4_sp2); + __m512i iacc_mat_10_4 = _mm512_add_epi16(iacc_mat_10_4_sp1, iacc_mat_10_4_sp2); + __m512i iacc_mat_11_4 = _mm512_add_epi16(iacc_mat_11_4_sp1, iacc_mat_11_4_sp2); + + __m512i iacc_mat_00_5 = _mm512_add_epi16(iacc_mat_00_5_sp1, iacc_mat_00_5_sp2); + __m512i iacc_mat_01_5 = _mm512_add_epi16(iacc_mat_01_5_sp1, iacc_mat_01_5_sp2); + __m512i iacc_mat_10_5 = _mm512_add_epi16(iacc_mat_10_5_sp1, iacc_mat_10_5_sp2); + __m512i iacc_mat_11_5 = _mm512_add_epi16(iacc_mat_11_5_sp1, iacc_mat_11_5_sp2); + + __m512i iacc_mat_00_6 = _mm512_add_epi16(iacc_mat_00_6_sp1, iacc_mat_00_6_sp2); + __m512i iacc_mat_01_6 = _mm512_add_epi16(iacc_mat_01_6_sp1, iacc_mat_01_6_sp2); + __m512i iacc_mat_10_6 = _mm512_add_epi16(iacc_mat_10_6_sp1, iacc_mat_10_6_sp2); + __m512i iacc_mat_11_6 = _mm512_add_epi16(iacc_mat_11_6_sp1, iacc_mat_11_6_sp2); + + __m512i iacc_mat_00_7 = _mm512_add_epi16(iacc_mat_00_7_sp1, iacc_mat_00_7_sp2); + __m512i iacc_mat_01_7 = _mm512_add_epi16(iacc_mat_01_7_sp1, iacc_mat_01_7_sp2); + __m512i iacc_mat_10_7 = _mm512_add_epi16(iacc_mat_10_7_sp1, iacc_mat_10_7_sp2); + __m512i iacc_mat_11_7 = _mm512_add_epi16(iacc_mat_11_7_sp1, iacc_mat_11_7_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + iacc_mat_00_0 = _mm512_madd_epi16(iacc_mat_00_0, scale_014589CD_0); + iacc_mat_01_0 = _mm512_madd_epi16(iacc_mat_01_0, scale_2367ABEF_0); + iacc_mat_10_0 = _mm512_madd_epi16(iacc_mat_10_0, scale_014589CD_0); + iacc_mat_11_0 = _mm512_madd_epi16(iacc_mat_11_0, scale_2367ABEF_0); + + iacc_mat_00_1 = _mm512_madd_epi16(iacc_mat_00_1, scale_014589CD_1); + iacc_mat_01_1 = _mm512_madd_epi16(iacc_mat_01_1, scale_2367ABEF_1); + iacc_mat_10_1 = _mm512_madd_epi16(iacc_mat_10_1, scale_014589CD_1); + iacc_mat_11_1 = _mm512_madd_epi16(iacc_mat_11_1, scale_2367ABEF_1); + + iacc_mat_00_2 = _mm512_madd_epi16(iacc_mat_00_2, scale_014589CD_2); + iacc_mat_01_2 = _mm512_madd_epi16(iacc_mat_01_2, scale_2367ABEF_2); + iacc_mat_10_2 = _mm512_madd_epi16(iacc_mat_10_2, scale_014589CD_2); + iacc_mat_11_2 = _mm512_madd_epi16(iacc_mat_11_2, scale_2367ABEF_2); + + iacc_mat_00_3 = _mm512_madd_epi16(iacc_mat_00_3, scale_014589CD_3); + iacc_mat_01_3 = _mm512_madd_epi16(iacc_mat_01_3, scale_2367ABEF_3); + iacc_mat_10_3 = _mm512_madd_epi16(iacc_mat_10_3, scale_014589CD_3); + iacc_mat_11_3 = _mm512_madd_epi16(iacc_mat_11_3, scale_2367ABEF_3); + + iacc_mat_00_4 = _mm512_madd_epi16(iacc_mat_00_4, scale_014589CD_4); + iacc_mat_01_4 = _mm512_madd_epi16(iacc_mat_01_4, scale_2367ABEF_4); + iacc_mat_10_4 = _mm512_madd_epi16(iacc_mat_10_4, scale_014589CD_4); + iacc_mat_11_4 = _mm512_madd_epi16(iacc_mat_11_4, scale_2367ABEF_4); + + iacc_mat_00_5 = _mm512_madd_epi16(iacc_mat_00_5, scale_014589CD_5); + iacc_mat_01_5 = _mm512_madd_epi16(iacc_mat_01_5, scale_2367ABEF_5); + iacc_mat_10_5 = _mm512_madd_epi16(iacc_mat_10_5, scale_014589CD_5); + iacc_mat_11_5 = _mm512_madd_epi16(iacc_mat_11_5, scale_2367ABEF_5); + + iacc_mat_00_6 = _mm512_madd_epi16(iacc_mat_00_6, scale_014589CD_6); + iacc_mat_01_6 = _mm512_madd_epi16(iacc_mat_01_6, scale_2367ABEF_6); + iacc_mat_10_6 = _mm512_madd_epi16(iacc_mat_10_6, scale_014589CD_6); + iacc_mat_11_6 = _mm512_madd_epi16(iacc_mat_11_6, scale_2367ABEF_6); + + iacc_mat_00_7 = _mm512_madd_epi16(iacc_mat_00_7, scale_014589CD_7); + iacc_mat_01_7 = _mm512_madd_epi16(iacc_mat_01_7, scale_2367ABEF_7); + iacc_mat_10_7 = _mm512_madd_epi16(iacc_mat_10_7, scale_014589CD_7); + iacc_mat_11_7 = _mm512_madd_epi16(iacc_mat_11_7, scale_2367ABEF_7); + + __m512i iacc_mat_00 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_00_0, iacc_mat_00_1), _mm512_add_epi32(iacc_mat_00_2, iacc_mat_00_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_00_4, iacc_mat_00_5), _mm512_add_epi32(iacc_mat_00_6, iacc_mat_00_7))); + __m512i iacc_mat_01 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_01_0, iacc_mat_01_1), _mm512_add_epi32(iacc_mat_01_2, iacc_mat_01_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_01_4, iacc_mat_01_5), _mm512_add_epi32(iacc_mat_01_6, iacc_mat_01_7))); + __m512i iacc_mat_10 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_10_0, iacc_mat_10_1), _mm512_add_epi32(iacc_mat_10_2, iacc_mat_10_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_10_4, iacc_mat_10_5), _mm512_add_epi32(iacc_mat_10_6, iacc_mat_10_7))); + __m512i iacc_mat_11 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_11_0, iacc_mat_11_1), _mm512_add_epi32(iacc_mat_11_2, iacc_mat_11_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_11_4, iacc_mat_11_5), _mm512_add_epi32(iacc_mat_11_6, iacc_mat_11_7))); + + // Straighten out to make 4 row vectors + __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); + __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); + __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); + __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); + + // Load the scale(d) values for all the 4 Q8_k blocks and repeat it across lanes + const __m128 row_scale_f32_sse = _mm_load_ps(a_ptr[b].d); + const __m256 row_scale_f32_ymm = _mm256_set_m128(row_scale_f32_sse, row_scale_f32_sse); + const __m512 row_scale_f32 = _mm512_insertf32x8(_mm512_castps256_ps512(row_scale_f32_ymm), row_scale_f32_ymm, 1); + + // Multiply with appropiate scales and accumulate (for both d and dmin) below + acc_rows[0] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); + acc_rows[1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); + acc_rows[2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); + acc_rows[3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); + + // Take two bsums from two Q8_Ks at a time and multiply with corresponding mins values from each Q2_K + __m512i iacc_row_min_0_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)0), mins_01); + __m512i iacc_row_min_1_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)170), mins_01); + __m512i iacc_row_min_2_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)0), mins_01); + __m512i iacc_row_min_3_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)170), mins_01); + + __m512i iacc_row_min_0_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)85), mins_23); + __m512i iacc_row_min_1_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)255), mins_23); + __m512i iacc_row_min_2_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)85), mins_23); + __m512i iacc_row_min_3_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)255), mins_23); + + __m512i iacc_row_min_0_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)0), mins_45); + __m512i iacc_row_min_1_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)170), mins_45); + __m512i iacc_row_min_2_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)0), mins_45); + __m512i iacc_row_min_3_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)170), mins_45); + + __m512i iacc_row_min_0_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)85), mins_67); + __m512i iacc_row_min_1_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)255), mins_67); + __m512i iacc_row_min_2_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)85), mins_67); + __m512i iacc_row_min_3_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)255), mins_67); + + __m512i iacc_row_min_0 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_0_01, iacc_row_min_0_23), _mm512_add_epi32(iacc_row_min_0_45,iacc_row_min_0_67)); + __m512i iacc_row_min_1 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_1_01, iacc_row_min_1_23), _mm512_add_epi32(iacc_row_min_1_45,iacc_row_min_1_67)); + __m512i iacc_row_min_2 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_2_01, iacc_row_min_2_23), _mm512_add_epi32(iacc_row_min_2_45,iacc_row_min_2_67)); + __m512i iacc_row_min_3 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_3_01, iacc_row_min_3_23), _mm512_add_epi32(iacc_row_min_3_45,iacc_row_min_3_67)); + + acc_min_rows[0] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_0), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_min_rows[0]); + acc_min_rows[1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_1), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_min_rows[1]); + acc_min_rows[2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_2), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_min_rows[2]); + acc_min_rows[3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_3), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_min_rows[3]); + } + } + // Store accumlated values + for (int i = 0; i < 4; i++) { + _mm512_storeu_ps((float * )(s + ((y * 4 + i) * bs + x * 8)), _mm512_sub_ps(acc_rows[i], acc_min_rows[i])); + } + } + } + + if (anc != nc) { + xstart = anc/8; + y = 0; + } + +#endif //AVX512F + + // Take group of four block_q8_Kx4 structures at each pass of the loop and perform dot product operation + for (; y < anr / 4; y += 4) { + + const block_q8_Kx4 * a_ptrs[4]; + + a_ptrs[0] = a_ptr_start + (y * nb); + for (int i = 0; i < 3; ++i) { + a_ptrs[i + 1] = a_ptrs[i] + nb; + } + + // Take group of eight block_q2_kx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = xstart; x < nc / 8; x++) { + + const block_q2_Kx8 * b_ptr = b_ptr_start + (x * b_nb); + + // Master FP accumulators + __m256 acc_rows[16]; + for (int i = 0; i < 16; i++) { + acc_rows[i] = _mm256_setzero_ps(); + } + + __m256 acc_min_rows[16]; + for (int i = 0; i < 16; i++) { + acc_min_rows[i] = _mm256_setzero_ps(); + } + + // For super block + for (int64_t b = 0; b < nb; b++) { + // Delta values - Load the eight scale values of block_q2_kx8 + const __m256 col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); + + // dmin values - Load the eight dmin values of block_q2_kx8 + const __m256 col_dmin_f32 = GGML_F32Cx8_LOAD(b_ptr[b].dmin); + + // Loop to iterate over the sixteen sub blocks of a super block - eight sub blocks are processed per iteration + for (int sb = 0; sb < QK_K / 128; sb++) { + + // Load the eight block_q2_K for eight sub blocks quantized values interleaved with each other in chunks of eight bytes - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + sb * 256)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_0123_2 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_4567_2 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_0123_3 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_4567_3 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 224 + sb * 256)); + + // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of values + //superblock sub block which part of sub block + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + const __m256i rhs_raw_mat_0145_2 = _mm256_blend_epi32(rhs_raw_mat_0123_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_2, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_2, requiredOrder), rhs_raw_mat_4567_2, 240); + + const __m256i rhs_raw_mat_0145_3 = _mm256_blend_epi32(rhs_raw_mat_0123_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_3, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_3, requiredOrder), rhs_raw_mat_4567_3, 240); + + // 2-bit -> 8-bit + // First sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_00 = _mm256_and_si256(rhs_raw_mat_0145_0, m3b); //B00(0-7) B01(0-7) B04(0-7) B05(0-7) + const __m256i rhs_mat_2367_00 = _mm256_and_si256(rhs_raw_mat_2367_0, m3b); //B02(0-7) B03(0-7) B06(0-7) B07(0-7) + + const __m256i rhs_mat_0145_01 = _mm256_and_si256(rhs_raw_mat_0145_1, m3b); //B00(8-15) B01(8-15) B04(8-15) B05(8-15) + const __m256i rhs_mat_2367_01 = _mm256_and_si256(rhs_raw_mat_2367_1, m3b); //B02(8-15) B03(8-15) B06(8-15) B07(8-15) + + // Second sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_10 = _mm256_and_si256(rhs_raw_mat_0145_2, m3b); //B10(0-7) B11(0-7) B14(0-7) B15(0-7) + const __m256i rhs_mat_2367_10 = _mm256_and_si256(rhs_raw_mat_2367_2, m3b); //B12(0-7) B13(0-7) B16(0-7) B17(0-7) + + const __m256i rhs_mat_0145_11 = _mm256_and_si256(rhs_raw_mat_0145_3, m3b); //B10(8-15) B11(8-15) B14(8-15) B15(8-15) + const __m256i rhs_mat_2367_11 = _mm256_and_si256(rhs_raw_mat_2367_3, m3b); //B12(8-15) B13(8-15) B16(8-15) B17(8-15) + + // Third sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 2), m3b); //B20(0-7) B21(0-7) B24(0-7) B25(0-7) + const __m256i rhs_mat_2367_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 2), m3b); //B22(0-7) B23(0-7) B26(0-7) B27(0-7) + + const __m256i rhs_mat_0145_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 2), m3b); //B20(8-15) B21(8-15) B24(8-15) B25(8-15) + const __m256i rhs_mat_2367_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 2), m3b); //B22(8-15) B23(8-15) B26(8-15) B27(8-15) + + // Fourth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 2), m3b); //B30(0-7) B31(0-7) B34(0-7) B35(0-7) + const __m256i rhs_mat_2367_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 2), m3b); //B32(0-7) B33(0-7) B36(0-7) B37(0-7) + + const __m256i rhs_mat_0145_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 2), m3b); //B30(8-15) B31(8-15) B34(8-15) B35(8-15) + const __m256i rhs_mat_2367_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 2), m3b); //B32(8-15) B33(8-15) B36(8-15) B37(8-15) + + // Fifth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m3b); //B40(0-7) B41(0-7) B44(0-7) B45(0-7) + const __m256i rhs_mat_2367_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m3b); //B42(0-7) B43(0-7) B46(0-7) B47(0-7) + + const __m256i rhs_mat_0145_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m3b); //B40(8-15) B41(8-15) B44(8-15) B45(8-15) + const __m256i rhs_mat_2367_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m3b); //B42(8-15) B43(8-15) B46(8-15) B47(8-15) + + // Sixth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 4), m3b); //B50(0-7) B51(0-7) B54(0-7) B55(0-7) + const __m256i rhs_mat_2367_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 4), m3b); //B52(0-7) B53(0-7) B56(0-7) B57(0-7) + + const __m256i rhs_mat_0145_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 4), m3b); //B50(8-15) B51(8-15) B54(8-15) B55(8-15) + const __m256i rhs_mat_2367_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 4), m3b); //B52(8-15) B53(8-15) B56(8-15) B57(8-15) + + // Seventh sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 6), m3b); //B60(0-7) B61(0-7) B64(0-7) B65(0-7) + const __m256i rhs_mat_2367_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 6), m3b); //B62(0-7) B63(0-7) B66(0-7) B67(0-7) + + const __m256i rhs_mat_0145_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 6), m3b); //B60(8-15) B61(8-15) B64(8-15) B65(8-15) + const __m256i rhs_mat_2367_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 6), m3b); //B62(8-15) B63(8-15) B66(8-15) B67(8-15) + + // Eighth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 6), m3b); //B70(0-7) B71(0-7) B74(0-7) B75(0-7) + const __m256i rhs_mat_2367_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 6), m3b); //B72(0-7) B73(0-7) B76(0-7) B77(0-7) + + const __m256i rhs_mat_0145_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 6), m3b); //B70(8-15) B71(8-15) B74(8-15) B75(8-15) + const __m256i rhs_mat_2367_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 6), m3b); //B72(8-15) B73(8-15) B76(8-15) B77(8-15) + + // Shuffle pattern one - right side input + const __m256i rhs_mat_0145_00_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_00, 136); //B00(0-3) B01(0-3) B00(0-3) B01(0-3) B04(0-3) B05(0-3) B04(0-3) B05(0-3) + const __m256i rhs_mat_2367_00_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_00, 136); //B02(0-3) B03(0-3) B02(0-3) B03(0-3) B06(0-3) B07(0-3) B06(0-3) B07(0-3) + + const __m256i rhs_mat_0145_01_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_01, 136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) + const __m256i rhs_mat_2367_01_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_01, 136); //B02(8-11) B03(8-11) B02(8-11) B03(8-11) B06(8-11) B07(8-11) B06(8-11) B07(8-11) + + const __m256i rhs_mat_0145_10_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_10, 136); //B10(0-3) B11(0-3) B10(0-3) B11(0-3) B14(0-3) B15(0-3) B14(0-3) B15(0-3) + const __m256i rhs_mat_2367_10_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_10, 136); //B12(0-3) B13(0-3) B12(0-3) B13(0-3) B16(0-3) B17(0-3) B16(0-3) B17(0-3) + + const __m256i rhs_mat_0145_11_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_11, 136); //B10(8-11) B11(8-11) B10(8-11) B11(8-11) B14(8-11) B15(8-11) B14(8-11) B15(8-11) + const __m256i rhs_mat_2367_11_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_11, 136); //B12(8-11) B13(8-11) B12(8-11) B13(8-11) B16(8-11) B17(8-11) B16(8-11) B17(8-11) + + const __m256i rhs_mat_0145_20_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_20, 136); //B20(0-3) B21(0-3) B20(0-3) B21(0-3) B24(0-3) B25(0-3) B24(0-3) B25(0-3) + const __m256i rhs_mat_2367_20_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_20, 136); //B22(0-3) B23(0-3) B22(0-3) B23(0-3) B26(0-3) B27(0-3) B26(0-3) B27(0-3) + + const __m256i rhs_mat_0145_21_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_21, 136); //B20(8-11) B21(8-11) B20(8-11) B21(8-11) B24(8-11) B25(8-11) B24(8-11) B25(8-11) + const __m256i rhs_mat_2367_21_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_21, 136); //B22(8-11) B23(8-11) B22(8-11) B23(8-11) B26(8-11) B27(8-11) B26(8-11) B27(8-11) + + const __m256i rhs_mat_0145_30_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_30, 136); //B30(0-3) B31(0-3) B30(0-3) B31(0-3) B34(0-3) B35(0-3) B34(0-3) B35(0-3) + const __m256i rhs_mat_2367_30_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_30, 136); //B32(0-3) B33(0-3) B32(0-3) B33(0-3) B36(0-3) B37(0-3) B36(0-3) B37(0-3) + + const __m256i rhs_mat_0145_31_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_31, 136); //B30(8-11) B31(8-11) B30(8-11) B31(8-11) B34(8-11) B35(8-11) B34(8-11) B35(8-11 + const __m256i rhs_mat_2367_31_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_31, 136); //B32(8-11) B33(8-11) B32(8-11) B33(8-11) B36(8-11) B37(8-11) B36(8-11) B37(8-11) + + const __m256i rhs_mat_0145_40_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_40, 136); //B40(0-3) B41(0-3) B40(0-3) B41(0-3) B44(0-3) B45(0-3) B44(0-3) B45(0-3) + const __m256i rhs_mat_2367_40_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_40, 136); //B42(0-3) B43(0-3) B42(0-3) B43(0-3) B46(0-3) B47(0-3) B46(0-3) B47(0-3) + + const __m256i rhs_mat_0145_41_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_41, 136); //B40(8-11) B41(8-11) B40(8-11) B41(8-11) B44(8-11) B45(8-11) B44(8-11) B45(8-11) + const __m256i rhs_mat_2367_41_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_41, 136); //B42(8-11) B43(8-11) B42(8-11) B43(8-11) B46(8-11) B47(8-11) B46(8-11) B47(8-11) + + const __m256i rhs_mat_0145_50_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_50, 136); //B50(0-3) B51(0-3) B50(0-3) B51(0-3) B54(0-3) B55(0-3) B54(0-3) B55(0-3) + const __m256i rhs_mat_2367_50_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_50, 136); //B52(0-3) B53(0-3) B52(0-3) B53(0-3) B56(0-3) B57(0-3) B56(0-3) B57(0-3) + + const __m256i rhs_mat_0145_51_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_51, 136); //B50(8-11) B51(8-11) B50(8-11) B51(8-11) B54(8-11) B55(8-11) B54(8-11) B55(8-11) + const __m256i rhs_mat_2367_51_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_51, 136); //B52(8-11) B53(8-11) B52(8-11) B53(8-11) B56(8-11) B57(8-11) B56(8-11) B57(8-11) + + const __m256i rhs_mat_0145_60_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_60, 136); //B60(0-3) B61(0-3) B60(0-3) B61(0-3) B64(0-3) B65(0-3) B64(0-3) B65(0-3) + const __m256i rhs_mat_2367_60_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_60, 136); //B62(0-3) B63(0-3) B62(0-3) B63(0-3) B66(0-3) B67(0-3) B66(0-3) B67(0-3) + + const __m256i rhs_mat_0145_61_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_61, 136); //B60(8-11) B61(8-11) B60(8-11) B61(8-11) B64(8-11) B65(8-11) B64(8-11) B65(8-11) + const __m256i rhs_mat_2367_61_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_61, 136); //B62(8-11) B63(8-11) B62(8-11) B63(8-11) B66(8-11) B67(8-11) B66(8-11) B67(8-11) + + const __m256i rhs_mat_0145_70_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_70, 136); //B70(0-3) B71(0-3) B70(0-3) B71(0-3) B74(0-3) B75(0-3) B74(0-3) B75(0-3) + const __m256i rhs_mat_2367_70_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_70, 136); //B72(0-3) B73(0-3) B72(0-3) B73(0-3) B76(0-3) B77(0-3) B76(0-3) B77(0-3) + + const __m256i rhs_mat_0145_71_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_71, 136); //B70(8-11) B71(8-11) B70(8-11) B71(8-11) B74(8-11) B75(8-11) B74(8-11) B75(8-11) + const __m256i rhs_mat_2367_71_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_71, 136); //B72(8-11) B73(8-11) B72(8-11) B73(8-11) B76(8-11) B77(8-11) B76(8-11) B77(8-11) + + + // Shuffle pattern two - right side input + const __m256i rhs_mat_0145_00_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_00, 221); //B00(4-7) B01(4-7) B00(4-7) B01(4-7) B04(4-7) B05(4-7) B04(4-7) B05(4-7) + const __m256i rhs_mat_2367_00_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_00, 221); //B02(4-7) B03(4-7) B02(4-7) B03(4-7) B06(4-7) B07(4-7) B06(4-7) B07(4-7) + + const __m256i rhs_mat_0145_01_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_01, 221); //B00(12-15) B01(12-15) B00(12-15) B01(12-15) B04(12-15) B05(12-15) B04(12-15) B05(12-15) + const __m256i rhs_mat_2367_01_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_01, 221); //B02(12-15) B03(12-15) B02(12-15) B03(12-15) B06(12-15) B07(12-15) B06(12-15) B07(12-15) + + const __m256i rhs_mat_0145_10_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_10, 221); //B10(4-7) B11(4-7) B10(4-7) B11(4-7) B14(4-7) B15(4-7) B14(4-7) B15(4-7) + const __m256i rhs_mat_2367_10_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_10, 221); //B12(4-7) B13(4-7) B12(4-7) B13(4-7) B16(4-7) B17(4-7) B16(4-7) B17(4-7) + + const __m256i rhs_mat_0145_11_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_11, 221); //B10(12-15) B11(12-15) B10(12-15) B11(12-15) B14(12-15) B15(12-15) B14(12-15) B15(12-15) + const __m256i rhs_mat_2367_11_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_11, 221); //B12(12-15) B13(12-15) B12(12-15) B13(12-15) B16(12-15) B17(12-15) B16(12-15) B17(12-15) + + const __m256i rhs_mat_0145_20_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_20, 221); //B20(4-7) B21(4-7) B20(4-7) B21(4-7) B24(4-7) B25(4-7) B24(4-7) B25(4-7) + const __m256i rhs_mat_2367_20_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_20, 221); //B22(4-7) B23(4-7) B22(4-7) B23(4-7) B26(4-7) B27(4-7) B26(4-7) B27(4-7) + + const __m256i rhs_mat_0145_21_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_21, 221); //B20(12-15) B21(12-15) B20(12-15) B21(12-15) B24(12-15) B25(12-15) B24(12-15) B25(12-15) + const __m256i rhs_mat_2367_21_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_21, 221); //B22(12-15) B23(12-15) B22(12-15) B23(12-15) B26(12-15) B27(12-15) B26(12-15) B27(12-15) + + const __m256i rhs_mat_0145_30_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_30, 221); //B30(4-7) B31(4-7) B30(4-7) B31(4-7) B34(4-7) B35(4-7) B34(4-7) B35(4-7) + const __m256i rhs_mat_2367_30_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_30, 221); //B32(4-7) B33(4-7) B32(4-7) B33(4-7) B36(4-7) B37(4-7) B36(4-7) B37(4-7) + + const __m256i rhs_mat_0145_31_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_31, 221); //B30(12-15) B31(12-15) B30(12-15) B31(12-15) B34(12-15) B35(12-15) B34(12-15) B35(12-15) + const __m256i rhs_mat_2367_31_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_31, 221); //B32(12-15) B33(12-15) B32(12-15) B33(12-15) B36(12-15) B37(12-15) B36(12-15) B37(12-15) + + const __m256i rhs_mat_0145_40_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_40, 221); //B40(4-7) B41(4-7) B40(4-7) B41(4-7) B44(4-7) B45(4-7) B44(4-7) B45(4-7) + const __m256i rhs_mat_2367_40_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_40, 221); //B42(4-7) B43(4-7) B42(4-7) B43(4-7) B46(4-7) B47(4-7) B46(4-7) B47(4-7) + + const __m256i rhs_mat_0145_41_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_41, 221); //B40(12-15) B41(12-15) B40(12-15) B41(12-15) B44(12-15) B45(12-15) B44(12-15) B45(12-15) + const __m256i rhs_mat_2367_41_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_41, 221); //B42(12-15) B43(12-15) B42(12-15) B43(12-15) B46(12-15) B47(12-15) B46(12-15) B47(12-15) + + const __m256i rhs_mat_0145_50_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_50, 221); //B50(4-7) B51(4-7) B50(4-7) B51(4-7) B54(4-7) B55(4-7) B54(4-7) B55(4-7) + const __m256i rhs_mat_2367_50_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_50, 221); //B52(4-7) B53(4-7) B52(4-7) B53(4-7) B56(4-7) B57(4-7) B56(4-7) B57(4-7) + + const __m256i rhs_mat_0145_51_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_51, 221); //B50(12-15) B51(12-15) B50(12-15) B51(12-15) B54(12-15) B55(12-15) B54(12-15) B55(12-15) + const __m256i rhs_mat_2367_51_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_51, 221); //B52(12-15) B53(12-15) B52(12-15) B53(12-15) B56(12-15) B57(12-15) B56(12-15) B57(12-15) + + const __m256i rhs_mat_0145_60_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_60, 221); //B60(4-7) B61(4-7) B60(4-7) B61(4-7) B64(4-7) B65(4-7) B64(4-7) B65(4-7) + const __m256i rhs_mat_2367_60_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_60, 221); //B62(4-7) B63(4-7) B62(4-7) B63(4-7) B66(4-7) B67(4-7) B66(4-7) B67(4-7) + + const __m256i rhs_mat_0145_61_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_61, 221); //B60(12-15) B61(12-15) B60(12-15) B61(12-15) B64(12-15) B65(12-15) B64(12-15) B65(12-15) + const __m256i rhs_mat_2367_61_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_61, 221); //B62(12-15) B63(12-15) B62(12-15) B63(12-15) B66(12-15) B67(12-15) B66(12-15) B67(12-15) + + const __m256i rhs_mat_0145_70_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_70, 221); //B70(4-7) B71(4-7) B70(4-7) B71(4-7) B74(4-7) B75(4-7) B74(4-7) B75(4-7) + const __m256i rhs_mat_2367_70_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_70, 221); //B72(4-7) B73(4-7) B72(4-7) B73(4-7) B76(4-7) B77(4-7) B76(4-7) B77(4-7) + + const __m256i rhs_mat_0145_71_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_71, 221); //B70(12-15) B71(12-15) B70(12-15) B71(12-15) B74(12-15) B75(12-15) B74(12-15) B75(12-15) + const __m256i rhs_mat_2367_71_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_71, 221); //B72(12-15) B73(12-15) B72(12-15) B73(12-15) B76(12-15) B77(12-15) B76(12-15) B77(12-15) + + //Scales and Mins of corresponding sub blocks from different Q2_K structures are stored together + //s00 m00 s01 m01 s10 m10 s11 m11 s20 m20 s21 m21 s30 m30 s31 m31 s40 m40 s41 m41 s50 m50 s51 m51 s60 m60 s61 m61 s70 m70 s71 m71 + + // Combine mins and scales for sub-blocks: 0-1, 2-3, 4-5, 6-7 in the sb loop + const __m128i mins_and_scales_01 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + sb * 64)); + const __m128i mins_and_scales_23 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 48 + sb * 64)); + + // Extract scales which is lower half from mins_and_scales + const __m128i scales_01 = _mm_and_si128(mins_and_scales_01, m4b_sse); + const __m128i scales_23 = _mm_and_si128(mins_and_scales_23, m4b_sse); + const __m128i scales_45 = _mm_and_si128(mins_and_scales_45, m4b_sse); + const __m128i scales_67 = _mm_and_si128(mins_and_scales_67, m4b_sse); + + // Extract mins which is upper half from mins_and_scales + const __m256i mins_01 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_01, 4), m4b_sse)); + const __m256i mins_23 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_23, 4), m4b_sse)); + const __m256i mins_45 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_45, 4), m4b_sse)); + const __m256i mins_67 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_67, 4), m4b_sse)); + + const __m256i scales_0 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_01, scalesmask1_sse)); + const __m256i scales_1 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_01, scalesmask2_sse)); + + const __m256i scales_2 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_23, scalesmask1_sse)); + const __m256i scales_3 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_23, scalesmask2_sse)); + + const __m256i scales_4 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_45, scalesmask1_sse)); + const __m256i scales_5 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_45, scalesmask2_sse)); + + const __m256i scales_6 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_67, scalesmask1_sse)); + const __m256i scales_7 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_67, scalesmask2_sse)); + + const __m256i scale_0145_0 = _mm256_shuffle_epi32(scales_0, 68); + const __m256i scale_2367_0 = _mm256_shuffle_epi32(scales_0, 238); + + const __m256i scale_0145_1 = _mm256_shuffle_epi32(scales_1, 68); + const __m256i scale_2367_1 = _mm256_shuffle_epi32(scales_1, 238); + + const __m256i scale_0145_2 = _mm256_shuffle_epi32(scales_2, 68); + const __m256i scale_2367_2 = _mm256_shuffle_epi32(scales_2, 238); + + const __m256i scale_0145_3 = _mm256_shuffle_epi32(scales_3, 68); + const __m256i scale_2367_3 = _mm256_shuffle_epi32(scales_3, 238); + + const __m256i scale_0145_4 = _mm256_shuffle_epi32(scales_4, 68); + const __m256i scale_2367_4 = _mm256_shuffle_epi32(scales_4, 238); + + const __m256i scale_0145_5 = _mm256_shuffle_epi32(scales_5, 68); + const __m256i scale_2367_5 = _mm256_shuffle_epi32(scales_5, 238); + + const __m256i scale_0145_6 = _mm256_shuffle_epi32(scales_6, 68); + const __m256i scale_2367_6 = _mm256_shuffle_epi32(scales_6, 238); + + const __m256i scale_0145_7 = _mm256_shuffle_epi32(scales_7, 68); + const __m256i scale_2367_7 = _mm256_shuffle_epi32(scales_7, 238); + + + for (int rp = 0; rp < 4; rp++) { + + // Load the four block_q8_k quantized values interleaved with each other in chunks of eight bytes - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated into a 256 bit vector + __m256i lhs_mat_0123_00 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 512 * sb))); + __m256i lhs_mat_01_00 = _mm256_permute2f128_si256(lhs_mat_0123_00, lhs_mat_0123_00, 0); + __m256i lhs_mat_23_00 = _mm256_permute2f128_si256(lhs_mat_0123_00, lhs_mat_0123_00, 17); + __m256i lhs_mat_0123_01 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 32 + 512 * sb))); + __m256i lhs_mat_01_01 = _mm256_permute2f128_si256(lhs_mat_0123_01, lhs_mat_0123_01, 0); + __m256i lhs_mat_23_01 = _mm256_permute2f128_si256(lhs_mat_0123_01, lhs_mat_0123_01, 17); + __m256i lhs_mat_0123_10 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 64 + 512 * sb))); + __m256i lhs_mat_01_10 = _mm256_permute2f128_si256(lhs_mat_0123_10, lhs_mat_0123_10, 0); + __m256i lhs_mat_23_10 = _mm256_permute2f128_si256(lhs_mat_0123_10, lhs_mat_0123_10, 17); + __m256i lhs_mat_0123_11 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 96 + 512 * sb))); + __m256i lhs_mat_01_11 = _mm256_permute2f128_si256(lhs_mat_0123_11, lhs_mat_0123_11, 0); + __m256i lhs_mat_23_11 = _mm256_permute2f128_si256(lhs_mat_0123_11, lhs_mat_0123_11, 17); + __m256i lhs_mat_0123_20 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 128 + 512 * sb))); + __m256i lhs_mat_01_20 = _mm256_permute2f128_si256(lhs_mat_0123_20, lhs_mat_0123_20, 0); + __m256i lhs_mat_23_20 = _mm256_permute2f128_si256(lhs_mat_0123_20, lhs_mat_0123_20, 17); + __m256i lhs_mat_0123_21 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 160 + 512 * sb))); + __m256i lhs_mat_01_21 = _mm256_permute2f128_si256(lhs_mat_0123_21, lhs_mat_0123_21, 0); + __m256i lhs_mat_23_21 = _mm256_permute2f128_si256(lhs_mat_0123_21, lhs_mat_0123_21, 17); + __m256i lhs_mat_0123_30 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 192 + 512 * sb))); + __m256i lhs_mat_01_30 = _mm256_permute2f128_si256(lhs_mat_0123_30, lhs_mat_0123_30, 0); + __m256i lhs_mat_23_30 = _mm256_permute2f128_si256(lhs_mat_0123_30, lhs_mat_0123_30, 17); + __m256i lhs_mat_0123_31 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 224 + 512 * sb))); + __m256i lhs_mat_01_31 = _mm256_permute2f128_si256(lhs_mat_0123_31, lhs_mat_0123_31, 0); + __m256i lhs_mat_23_31 = _mm256_permute2f128_si256(lhs_mat_0123_31, lhs_mat_0123_31, 17); + + __m256i lhs_mat_0123_40 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 256 + 512 * sb))); + __m256i lhs_mat_01_40 = _mm256_permute2f128_si256(lhs_mat_0123_40, lhs_mat_0123_40, 0); + __m256i lhs_mat_23_40 = _mm256_permute2f128_si256(lhs_mat_0123_40, lhs_mat_0123_40, 17); + __m256i lhs_mat_0123_41 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 288 + 512 * sb))); + __m256i lhs_mat_01_41 = _mm256_permute2f128_si256(lhs_mat_0123_41, lhs_mat_0123_41, 0); + __m256i lhs_mat_23_41 = _mm256_permute2f128_si256(lhs_mat_0123_41, lhs_mat_0123_41, 17); + __m256i lhs_mat_0123_50 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 320 + 512 * sb))); + __m256i lhs_mat_01_50 = _mm256_permute2f128_si256(lhs_mat_0123_50, lhs_mat_0123_50, 0); + __m256i lhs_mat_23_50 = _mm256_permute2f128_si256(lhs_mat_0123_50, lhs_mat_0123_50, 17); + __m256i lhs_mat_0123_51 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 352 + 512 * sb))); + __m256i lhs_mat_01_51 = _mm256_permute2f128_si256(lhs_mat_0123_51, lhs_mat_0123_51, 0); + __m256i lhs_mat_23_51 = _mm256_permute2f128_si256(lhs_mat_0123_51, lhs_mat_0123_51, 17); + __m256i lhs_mat_0123_60 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 384 + 512 * sb))); + __m256i lhs_mat_01_60 = _mm256_permute2f128_si256(lhs_mat_0123_60, lhs_mat_0123_60, 0); + __m256i lhs_mat_23_60 = _mm256_permute2f128_si256(lhs_mat_0123_60, lhs_mat_0123_60, 17); + __m256i lhs_mat_0123_61 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 416 + 512 * sb))); + __m256i lhs_mat_01_61 = _mm256_permute2f128_si256(lhs_mat_0123_61, lhs_mat_0123_61, 0); + __m256i lhs_mat_23_61 = _mm256_permute2f128_si256(lhs_mat_0123_61, lhs_mat_0123_61, 17); + __m256i lhs_mat_0123_70 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 448 + 512 * sb))); + __m256i lhs_mat_01_70 = _mm256_permute2f128_si256(lhs_mat_0123_70, lhs_mat_0123_70, 0); + __m256i lhs_mat_23_70 = _mm256_permute2f128_si256(lhs_mat_0123_70, lhs_mat_0123_70, 17); + __m256i lhs_mat_0123_71 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 480 + 512 * sb))); + __m256i lhs_mat_01_71 = _mm256_permute2f128_si256(lhs_mat_0123_71, lhs_mat_0123_71, 0); + __m256i lhs_mat_23_71 = _mm256_permute2f128_si256(lhs_mat_0123_71, lhs_mat_0123_71, 17); + + // Bsums are loaded for the different Q8_K blocks + __m128i lhs_raw_bsums_01_0123 = _mm_loadu_si128((const __m128i *)((a_ptrs[rp][b].bsums + 32 * sb))); + __m128i lhs_raw_bsums_23_0123 = _mm_loadu_si128((const __m128i *)(a_ptrs[rp][b].bsums + 8 + 32 * sb)); + __m128i lhs_raw_bsums_01_4567 = _mm_loadu_si128((const __m128i *)((a_ptrs[rp][b].bsums + 16 + 32 * sb))); + __m128i lhs_raw_bsums_23_4567 = _mm_loadu_si128((const __m128i *)(a_ptrs[rp][b].bsums + 24 + 32 * sb)); + + // Shuffle pattern one - left side input + const __m256i lhs_mat_01_00_sp1 = _mm256_shuffle_epi32(lhs_mat_01_00, 160); //A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) + const __m256i lhs_mat_23_00_sp1 = _mm256_shuffle_epi32(lhs_mat_23_00, 160); //A02(0-3) A03(0-3) A02(0-3) A03(0-3) A02(0-3) A03(0-3) A02(0-3) A03(0-3) + + const __m256i lhs_mat_01_01_sp1 = _mm256_shuffle_epi32(lhs_mat_01_01, 160); //A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) + const __m256i lhs_mat_23_01_sp1 = _mm256_shuffle_epi32(lhs_mat_23_01, 160); //A02(8-11) A03(8-11) A02(8-11) A03(8-11) A02(8-11) A03(8-11) A02(8-11) A03(8-11) + + const __m256i lhs_mat_01_10_sp1 = _mm256_shuffle_epi32(lhs_mat_01_10, 160); //A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) + const __m256i lhs_mat_23_10_sp1 = _mm256_shuffle_epi32(lhs_mat_23_10, 160); //A12(0-3) A13(0-3) A12(0-3) A13(0-3) A12(0-3) A13(0-3) A12(0-3) A13(0-3) + + const __m256i lhs_mat_01_11_sp1 = _mm256_shuffle_epi32(lhs_mat_01_11, 160); //A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) + const __m256i lhs_mat_23_11_sp1 = _mm256_shuffle_epi32(lhs_mat_23_11, 160); //A12(8-11) A13(8-11) A12(8-11) A13(8-11) A12(8-11) A13(8-11) A12(8-11) A13(8-11) + + const __m256i lhs_mat_01_20_sp1 = _mm256_shuffle_epi32(lhs_mat_01_20, 160); //A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) + const __m256i lhs_mat_23_20_sp1 = _mm256_shuffle_epi32(lhs_mat_23_20, 160); //A22(0-3) A23(0-3) A22(0-3) A23(0-3) A22(0-3) A23(0-3) A22(0-3) A23(0-3) + + const __m256i lhs_mat_01_21_sp1 = _mm256_shuffle_epi32(lhs_mat_01_21, 160); //A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) + const __m256i lhs_mat_23_21_sp1 = _mm256_shuffle_epi32(lhs_mat_23_21, 160); //A22(8-11) A23(8-11) A22(8-11) A23(8-11) A22(8-11) A23(8-11) A22(8-11) A23(8-11) + + const __m256i lhs_mat_01_30_sp1 = _mm256_shuffle_epi32(lhs_mat_01_30, 160); //A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) + const __m256i lhs_mat_23_30_sp1 = _mm256_shuffle_epi32(lhs_mat_23_30, 160); //A32(0-3) A33(0-3) A32(0-3) A33(0-3) A32(0-3) A33(0-3) A32(0-3) A33(0-3) + + const __m256i lhs_mat_01_31_sp1 = _mm256_shuffle_epi32(lhs_mat_01_31, 160); //A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) + const __m256i lhs_mat_23_31_sp1 = _mm256_shuffle_epi32(lhs_mat_23_31, 160); //A32(8-11) A33(8-11) A32(8-11) A33(8-11) A32(8-11) A33(8-11) A32(8-11) A33(8-11) + + const __m256i lhs_mat_01_40_sp1 = _mm256_shuffle_epi32(lhs_mat_01_40, 160); //A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) + const __m256i lhs_mat_23_40_sp1 = _mm256_shuffle_epi32(lhs_mat_23_40, 160); //A42(0-3) A43(0-3) A42(0-3) A43(0-3) A42(0-3) A43(0-3) A42(0-3) A43(0-3) + + const __m256i lhs_mat_01_41_sp1 = _mm256_shuffle_epi32(lhs_mat_01_41, 160); //A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) + const __m256i lhs_mat_23_41_sp1 = _mm256_shuffle_epi32(lhs_mat_23_41, 160); //A42(8-11) A43(8-11) A42(8-11) A43(8-11) A42(8-11) A43(8-11) A42(8-11) A43(8-11) + + const __m256i lhs_mat_01_50_sp1 = _mm256_shuffle_epi32(lhs_mat_01_50, 160); //A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) + const __m256i lhs_mat_23_50_sp1 = _mm256_shuffle_epi32(lhs_mat_23_50, 160); //A52(0-3) A53(0-3) A52(0-3) A53(0-3) A52(0-3) A53(0-3) A52(0-3) A53(0-3) + + const __m256i lhs_mat_01_51_sp1 = _mm256_shuffle_epi32(lhs_mat_01_51, 160); //A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) + const __m256i lhs_mat_23_51_sp1 = _mm256_shuffle_epi32(lhs_mat_23_51, 160); //A52(8-11) A53(8-11) A52(8-11) A53(8-11) A52(8-11) A53(8-11) A52(8-11) A53(8-11) + + const __m256i lhs_mat_01_60_sp1 = _mm256_shuffle_epi32(lhs_mat_01_60, 160); //A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) + const __m256i lhs_mat_23_60_sp1 = _mm256_shuffle_epi32(lhs_mat_23_60, 160); //A62(0-3) A63(0-3) A62(0-3) A63(0-3) A62(0-3) A63(0-3) A62(0-3) A63(0-3) + + const __m256i lhs_mat_01_61_sp1 = _mm256_shuffle_epi32(lhs_mat_01_61, 160); //A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) + const __m256i lhs_mat_23_61_sp1 = _mm256_shuffle_epi32(lhs_mat_23_61, 160); //A62(8-11) A63(8-11) A62(8-11) A63(8-11) A62(8-11) A63(8-11) A62(8-11) A63(8-11) + + const __m256i lhs_mat_01_70_sp1 = _mm256_shuffle_epi32(lhs_mat_01_70, 160); //A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) + const __m256i lhs_mat_23_70_sp1 = _mm256_shuffle_epi32(lhs_mat_23_70, 160); //A72(0-3) A73(0-3) A72(0-3) A73(0-3) A72(0-3) A73(0-3) A72(0-3) A73(0-3) + + const __m256i lhs_mat_01_71_sp1 = _mm256_shuffle_epi32(lhs_mat_01_71, 160); //A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) + const __m256i lhs_mat_23_71_sp1 = _mm256_shuffle_epi32(lhs_mat_23_71, 160); //A72(8-11) A73(8-11) A72(8-11) A73(8-11) A72(8-11) A73(8-11) A72(8-11) A73(8-11) + + // Shuffle pattern two- left side input + const __m256i lhs_mat_01_00_sp2 = _mm256_shuffle_epi32(lhs_mat_01_00, 245); //A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) + const __m256i lhs_mat_23_00_sp2 = _mm256_shuffle_epi32(lhs_mat_23_00, 245); //A02(4-7) A03(4-7) A02(4-7) A03(4-7) A02(4-7) A03(4-7) A02(4-7) A03(4-7) + + const __m256i lhs_mat_01_01_sp2 = _mm256_shuffle_epi32(lhs_mat_01_01, 245); //A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) + const __m256i lhs_mat_23_01_sp2 = _mm256_shuffle_epi32(lhs_mat_23_01, 245); //A02(12-15) A03(12-15) A02(12-15) A03(12-15) A02(12-15) A03(12-15) A02(12-15) A03(12-15) + + const __m256i lhs_mat_01_10_sp2 = _mm256_shuffle_epi32(lhs_mat_01_10, 245); //A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) + const __m256i lhs_mat_23_10_sp2 = _mm256_shuffle_epi32(lhs_mat_23_10, 245); //A12(4-7) A13(4-7) A12(4-7) A13(4-7) A12(4-7) A13(4-7) A12(4-7) A13(4-7) + + const __m256i lhs_mat_01_11_sp2 = _mm256_shuffle_epi32(lhs_mat_01_11, 245); //A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) + const __m256i lhs_mat_23_11_sp2 = _mm256_shuffle_epi32(lhs_mat_23_11, 245); //A12(12-15) A13(12-15) A12(12-15) A13(12-15) A12(12-15) A13(12-15) A12(12-15) A13(12-15) + + const __m256i lhs_mat_01_20_sp2 = _mm256_shuffle_epi32(lhs_mat_01_20, 245); //A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) + const __m256i lhs_mat_23_20_sp2 = _mm256_shuffle_epi32(lhs_mat_23_20, 245); //A22(4-7) A23(4-7) A22(4-7) A23(4-7) A22(4-7) A23(4-7) A22(4-7) A23(4-7) + + const __m256i lhs_mat_01_21_sp2 = _mm256_shuffle_epi32(lhs_mat_01_21, 245); //A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) + const __m256i lhs_mat_23_21_sp2 = _mm256_shuffle_epi32(lhs_mat_23_21, 245); //A22(12-15) A23(12-15) A22(12-15) A23(12-15) A22(12-15) A23(12-15) A22(12-15) A23(12-15) + + const __m256i lhs_mat_01_30_sp2 = _mm256_shuffle_epi32(lhs_mat_01_30, 245); //A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) + const __m256i lhs_mat_23_30_sp2 = _mm256_shuffle_epi32(lhs_mat_23_30, 245); //A32(4-7) A33(4-7) A32(4-7) A33(4-7) A32(4-7) A33(4-7) A32(4-7) A33(4-7) + + const __m256i lhs_mat_01_31_sp2 = _mm256_shuffle_epi32(lhs_mat_01_31, 245); //A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) + const __m256i lhs_mat_23_31_sp2 = _mm256_shuffle_epi32(lhs_mat_23_31, 245); //A32(12-15) A33(12-15) A32(12-15) A33(12-15) A32(12-15) A33(12-15) A32(12-15) A33(12-15) + + const __m256i lhs_mat_01_40_sp2 = _mm256_shuffle_epi32(lhs_mat_01_40, 245); //A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) + const __m256i lhs_mat_23_40_sp2 = _mm256_shuffle_epi32(lhs_mat_23_40, 245); //A42(4-7) A43(4-7) A42(4-7) A43(4-7) A42(4-7) A43(4-7) A42(4-7) A43(4-7) + + const __m256i lhs_mat_01_41_sp2 = _mm256_shuffle_epi32(lhs_mat_01_41, 245); //A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) + const __m256i lhs_mat_23_41_sp2 = _mm256_shuffle_epi32(lhs_mat_23_41, 245); //A42(12-15) A43(12-15) A42(12-15) A43(12-15) A42(12-15) A43(12-15) A42(12-15) A43(12-15) + + const __m256i lhs_mat_01_50_sp2 = _mm256_shuffle_epi32(lhs_mat_01_50, 245); //A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) + const __m256i lhs_mat_23_50_sp2 = _mm256_shuffle_epi32(lhs_mat_23_50, 245); //A52(4-7) A53(4-7) A52(4-7) A53(4-7) A52(4-7) A53(4-7) A52(4-7) A53(4-7) + + const __m256i lhs_mat_01_51_sp2 = _mm256_shuffle_epi32(lhs_mat_01_51, 245); //A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) + const __m256i lhs_mat_23_51_sp2 = _mm256_shuffle_epi32(lhs_mat_23_51, 245); //A52(12-15) A53(12-15) A52(12-15) A53(12-15) A52(12-15) A53(12-15) A52(12-15) A53(12-15) + + const __m256i lhs_mat_01_60_sp2 = _mm256_shuffle_epi32(lhs_mat_01_60, 245); //A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) + const __m256i lhs_mat_23_60_sp2 = _mm256_shuffle_epi32(lhs_mat_23_60, 245); //A62(4-7) A63(4-7) A62(4-7) A63(4-7) A62(4-7) A63(4-7) A62(4-7) A63(4-7) + + const __m256i lhs_mat_01_61_sp2 = _mm256_shuffle_epi32(lhs_mat_01_61, 245); //A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) + const __m256i lhs_mat_23_61_sp2 = _mm256_shuffle_epi32(lhs_mat_23_61, 245); //A62(12-15) A63(12-15) A62(12-15) A63(12-15) A62(12-15) A63(12-15) A62(12-15) A63(12-15) + + const __m256i lhs_mat_01_70_sp2 = _mm256_shuffle_epi32(lhs_mat_01_70, 245); //A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) + const __m256i lhs_mat_23_70_sp2 = _mm256_shuffle_epi32(lhs_mat_23_70, 245); //A72(4-7) A73(4-7) A72(4-7) A73(4-7) A72(4-7) A73(4-7) A72(4-7) A73(4-7) + + const __m256i lhs_mat_01_71_sp2 = _mm256_shuffle_epi32(lhs_mat_01_71, 245); //A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) + const __m256i lhs_mat_23_71_sp2 = _mm256_shuffle_epi32(lhs_mat_23_71, 245); //A72(12-15) A73(12-15) A72(12-15) A73(12-15) A72(12-15) A73(12-15) A72(12-15) A73(12-15) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + __m256i iacc_mat_00_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp1, lhs_mat_01_00_sp1),_mm256_maddubs_epi16(rhs_mat_0145_01_sp1, lhs_mat_01_01_sp1)); + __m256i iacc_mat_01_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp1, lhs_mat_01_00_sp1),_mm256_maddubs_epi16(rhs_mat_2367_01_sp1, lhs_mat_01_01_sp1)); + + __m256i iacc_mat_10_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp1, lhs_mat_23_00_sp1),_mm256_maddubs_epi16(rhs_mat_0145_01_sp1, lhs_mat_23_01_sp1)); + __m256i iacc_mat_11_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp1, lhs_mat_23_00_sp1),_mm256_maddubs_epi16(rhs_mat_2367_01_sp1, lhs_mat_23_01_sp1)); + + __m256i iacc_mat_00_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp1, lhs_mat_01_10_sp1),_mm256_maddubs_epi16(rhs_mat_0145_11_sp1, lhs_mat_01_11_sp1)); + __m256i iacc_mat_01_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp1, lhs_mat_01_10_sp1),_mm256_maddubs_epi16(rhs_mat_2367_11_sp1, lhs_mat_01_11_sp1)); + + __m256i iacc_mat_10_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp1, lhs_mat_23_10_sp1),_mm256_maddubs_epi16(rhs_mat_0145_11_sp1, lhs_mat_23_11_sp1)); + __m256i iacc_mat_11_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp1, lhs_mat_23_10_sp1),_mm256_maddubs_epi16(rhs_mat_2367_11_sp1, lhs_mat_23_11_sp1)); + + __m256i iacc_mat_00_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp1, lhs_mat_01_20_sp1),_mm256_maddubs_epi16(rhs_mat_0145_21_sp1, lhs_mat_01_21_sp1)); + __m256i iacc_mat_01_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp1, lhs_mat_01_20_sp1),_mm256_maddubs_epi16(rhs_mat_2367_21_sp1, lhs_mat_01_21_sp1)); + + __m256i iacc_mat_10_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp1, lhs_mat_23_20_sp1),_mm256_maddubs_epi16(rhs_mat_0145_21_sp1, lhs_mat_23_21_sp1)); + __m256i iacc_mat_11_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp1, lhs_mat_23_20_sp1),_mm256_maddubs_epi16(rhs_mat_2367_21_sp1, lhs_mat_23_21_sp1)); + + __m256i iacc_mat_00_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp1, lhs_mat_01_30_sp1),_mm256_maddubs_epi16(rhs_mat_0145_31_sp1, lhs_mat_01_31_sp1)); + __m256i iacc_mat_01_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp1, lhs_mat_01_30_sp1),_mm256_maddubs_epi16(rhs_mat_2367_31_sp1, lhs_mat_01_31_sp1)); + + __m256i iacc_mat_10_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp1, lhs_mat_23_30_sp1),_mm256_maddubs_epi16(rhs_mat_0145_31_sp1, lhs_mat_23_31_sp1)); + __m256i iacc_mat_11_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp1, lhs_mat_23_30_sp1),_mm256_maddubs_epi16(rhs_mat_2367_31_sp1, lhs_mat_23_31_sp1)); + + __m256i iacc_mat_00_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp1, lhs_mat_01_40_sp1),_mm256_maddubs_epi16(rhs_mat_0145_41_sp1, lhs_mat_01_41_sp1)); + __m256i iacc_mat_01_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp1, lhs_mat_01_40_sp1),_mm256_maddubs_epi16(rhs_mat_2367_41_sp1, lhs_mat_01_41_sp1)); + + __m256i iacc_mat_10_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp1, lhs_mat_23_40_sp1),_mm256_maddubs_epi16(rhs_mat_0145_41_sp1, lhs_mat_23_41_sp1)); + __m256i iacc_mat_11_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp1, lhs_mat_23_40_sp1),_mm256_maddubs_epi16(rhs_mat_2367_41_sp1, lhs_mat_23_41_sp1)); + + __m256i iacc_mat_00_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp1, lhs_mat_01_50_sp1),_mm256_maddubs_epi16(rhs_mat_0145_51_sp1, lhs_mat_01_51_sp1)); + __m256i iacc_mat_01_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp1, lhs_mat_01_50_sp1),_mm256_maddubs_epi16(rhs_mat_2367_51_sp1, lhs_mat_01_51_sp1)); + + __m256i iacc_mat_10_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp1, lhs_mat_23_50_sp1),_mm256_maddubs_epi16(rhs_mat_0145_51_sp1, lhs_mat_23_51_sp1)); + __m256i iacc_mat_11_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp1, lhs_mat_23_50_sp1),_mm256_maddubs_epi16(rhs_mat_2367_51_sp1, lhs_mat_23_51_sp1)); + + __m256i iacc_mat_00_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp1, lhs_mat_01_60_sp1),_mm256_maddubs_epi16(rhs_mat_0145_61_sp1, lhs_mat_01_61_sp1)); + __m256i iacc_mat_01_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp1, lhs_mat_01_60_sp1),_mm256_maddubs_epi16(rhs_mat_2367_61_sp1, lhs_mat_01_61_sp1)); + + __m256i iacc_mat_10_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp1, lhs_mat_23_60_sp1),_mm256_maddubs_epi16(rhs_mat_0145_61_sp1, lhs_mat_23_61_sp1)); + __m256i iacc_mat_11_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp1, lhs_mat_23_60_sp1),_mm256_maddubs_epi16(rhs_mat_2367_61_sp1, lhs_mat_23_61_sp1)); + + __m256i iacc_mat_00_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp1, lhs_mat_01_70_sp1),_mm256_maddubs_epi16(rhs_mat_0145_71_sp1, lhs_mat_01_71_sp1)); + __m256i iacc_mat_01_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp1, lhs_mat_01_70_sp1),_mm256_maddubs_epi16(rhs_mat_2367_71_sp1, lhs_mat_01_71_sp1)); + + __m256i iacc_mat_10_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp1, lhs_mat_23_70_sp1),_mm256_maddubs_epi16(rhs_mat_0145_71_sp1, lhs_mat_23_71_sp1)); + __m256i iacc_mat_11_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp1, lhs_mat_23_70_sp1),_mm256_maddubs_epi16(rhs_mat_2367_71_sp1, lhs_mat_23_71_sp1)); + + + __m256i iacc_mat_00_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp2, lhs_mat_01_00_sp2),_mm256_maddubs_epi16(rhs_mat_0145_01_sp2, lhs_mat_01_01_sp2)); + __m256i iacc_mat_01_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp2, lhs_mat_01_00_sp2),_mm256_maddubs_epi16(rhs_mat_2367_01_sp2, lhs_mat_01_01_sp2)); + + __m256i iacc_mat_10_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp2, lhs_mat_23_00_sp2),_mm256_maddubs_epi16(rhs_mat_0145_01_sp2, lhs_mat_23_01_sp2)); + __m256i iacc_mat_11_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp2, lhs_mat_23_00_sp2),_mm256_maddubs_epi16(rhs_mat_2367_01_sp2, lhs_mat_23_01_sp2)); + + __m256i iacc_mat_00_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp2, lhs_mat_01_10_sp2),_mm256_maddubs_epi16(rhs_mat_0145_11_sp2, lhs_mat_01_11_sp2)); + __m256i iacc_mat_01_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp2, lhs_mat_01_10_sp2),_mm256_maddubs_epi16(rhs_mat_2367_11_sp2, lhs_mat_01_11_sp2)); + + __m256i iacc_mat_10_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp2, lhs_mat_23_10_sp2),_mm256_maddubs_epi16(rhs_mat_0145_11_sp2, lhs_mat_23_11_sp2)); + __m256i iacc_mat_11_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp2, lhs_mat_23_10_sp2),_mm256_maddubs_epi16(rhs_mat_2367_11_sp2, lhs_mat_23_11_sp2)); + + __m256i iacc_mat_00_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp2, lhs_mat_01_20_sp2),_mm256_maddubs_epi16(rhs_mat_0145_21_sp2, lhs_mat_01_21_sp2)); + __m256i iacc_mat_01_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp2, lhs_mat_01_20_sp2),_mm256_maddubs_epi16(rhs_mat_2367_21_sp2, lhs_mat_01_21_sp2)); + + __m256i iacc_mat_10_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp2, lhs_mat_23_20_sp2),_mm256_maddubs_epi16(rhs_mat_0145_21_sp2, lhs_mat_23_21_sp2)); + __m256i iacc_mat_11_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp2, lhs_mat_23_20_sp2),_mm256_maddubs_epi16(rhs_mat_2367_21_sp2, lhs_mat_23_21_sp2)); + + __m256i iacc_mat_00_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp2, lhs_mat_01_30_sp2),_mm256_maddubs_epi16(rhs_mat_0145_31_sp2, lhs_mat_01_31_sp2)); + __m256i iacc_mat_01_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp2, lhs_mat_01_30_sp2),_mm256_maddubs_epi16(rhs_mat_2367_31_sp2, lhs_mat_01_31_sp2)); + + __m256i iacc_mat_10_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp2, lhs_mat_23_30_sp2),_mm256_maddubs_epi16(rhs_mat_0145_31_sp2, lhs_mat_23_31_sp2)); + __m256i iacc_mat_11_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp2, lhs_mat_23_30_sp2),_mm256_maddubs_epi16(rhs_mat_2367_31_sp2, lhs_mat_23_31_sp2)); + + __m256i iacc_mat_00_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp2, lhs_mat_01_40_sp2),_mm256_maddubs_epi16(rhs_mat_0145_41_sp2, lhs_mat_01_41_sp2)); + __m256i iacc_mat_01_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp2, lhs_mat_01_40_sp2),_mm256_maddubs_epi16(rhs_mat_2367_41_sp2, lhs_mat_01_41_sp2)); + + __m256i iacc_mat_10_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp2, lhs_mat_23_40_sp2),_mm256_maddubs_epi16(rhs_mat_0145_41_sp2, lhs_mat_23_41_sp2)); + __m256i iacc_mat_11_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp2, lhs_mat_23_40_sp2),_mm256_maddubs_epi16(rhs_mat_2367_41_sp2, lhs_mat_23_41_sp2)); + + __m256i iacc_mat_00_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp2, lhs_mat_01_50_sp2),_mm256_maddubs_epi16(rhs_mat_0145_51_sp2, lhs_mat_01_51_sp2)); + __m256i iacc_mat_01_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp2, lhs_mat_01_50_sp2),_mm256_maddubs_epi16(rhs_mat_2367_51_sp2, lhs_mat_01_51_sp2)); + + __m256i iacc_mat_10_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp2, lhs_mat_23_50_sp2),_mm256_maddubs_epi16(rhs_mat_0145_51_sp2, lhs_mat_23_51_sp2)); + __m256i iacc_mat_11_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp2, lhs_mat_23_50_sp2),_mm256_maddubs_epi16(rhs_mat_2367_51_sp2, lhs_mat_23_51_sp2)); + + __m256i iacc_mat_00_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp2, lhs_mat_01_60_sp2),_mm256_maddubs_epi16(rhs_mat_0145_61_sp2, lhs_mat_01_61_sp2)); + __m256i iacc_mat_01_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp2, lhs_mat_01_60_sp2),_mm256_maddubs_epi16(rhs_mat_2367_61_sp2, lhs_mat_01_61_sp2)); + + __m256i iacc_mat_10_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp2, lhs_mat_23_60_sp2),_mm256_maddubs_epi16(rhs_mat_0145_61_sp2, lhs_mat_23_61_sp2)); + __m256i iacc_mat_11_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp2, lhs_mat_23_60_sp2),_mm256_maddubs_epi16(rhs_mat_2367_61_sp2, lhs_mat_23_61_sp2)); + + __m256i iacc_mat_00_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp2, lhs_mat_01_70_sp2),_mm256_maddubs_epi16(rhs_mat_0145_71_sp2, lhs_mat_01_71_sp2)); + __m256i iacc_mat_01_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp2, lhs_mat_01_70_sp2),_mm256_maddubs_epi16(rhs_mat_2367_71_sp2, lhs_mat_01_71_sp2)); + + __m256i iacc_mat_10_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp2, lhs_mat_23_70_sp2),_mm256_maddubs_epi16(rhs_mat_0145_71_sp2, lhs_mat_23_71_sp2)); + __m256i iacc_mat_11_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp2, lhs_mat_23_70_sp2),_mm256_maddubs_epi16(rhs_mat_2367_71_sp2, lhs_mat_23_71_sp2)); + + // Combine results from both shuffle patterns for each output block + __m256i iacc_mat_00_0 = _mm256_add_epi16(iacc_mat_00_0_sp1, iacc_mat_00_0_sp2); + __m256i iacc_mat_01_0 = _mm256_add_epi16(iacc_mat_01_0_sp1, iacc_mat_01_0_sp2); + __m256i iacc_mat_10_0 = _mm256_add_epi16(iacc_mat_10_0_sp1, iacc_mat_10_0_sp2); + __m256i iacc_mat_11_0 = _mm256_add_epi16(iacc_mat_11_0_sp1, iacc_mat_11_0_sp2); + + __m256i iacc_mat_00_1 = _mm256_add_epi16(iacc_mat_00_1_sp1, iacc_mat_00_1_sp2); + __m256i iacc_mat_01_1 = _mm256_add_epi16(iacc_mat_01_1_sp1, iacc_mat_01_1_sp2); + __m256i iacc_mat_10_1 = _mm256_add_epi16(iacc_mat_10_1_sp1, iacc_mat_10_1_sp2); + __m256i iacc_mat_11_1 = _mm256_add_epi16(iacc_mat_11_1_sp1, iacc_mat_11_1_sp2); + + __m256i iacc_mat_00_2 = _mm256_add_epi16(iacc_mat_00_2_sp1, iacc_mat_00_2_sp2); + __m256i iacc_mat_01_2 = _mm256_add_epi16(iacc_mat_01_2_sp1, iacc_mat_01_2_sp2); + __m256i iacc_mat_10_2 = _mm256_add_epi16(iacc_mat_10_2_sp1, iacc_mat_10_2_sp2); + __m256i iacc_mat_11_2 = _mm256_add_epi16(iacc_mat_11_2_sp1, iacc_mat_11_2_sp2); + + __m256i iacc_mat_00_3 = _mm256_add_epi16(iacc_mat_00_3_sp1, iacc_mat_00_3_sp2); + __m256i iacc_mat_01_3 = _mm256_add_epi16(iacc_mat_01_3_sp1, iacc_mat_01_3_sp2); + __m256i iacc_mat_10_3 = _mm256_add_epi16(iacc_mat_10_3_sp1, iacc_mat_10_3_sp2); + __m256i iacc_mat_11_3 = _mm256_add_epi16(iacc_mat_11_3_sp1, iacc_mat_11_3_sp2); + + __m256i iacc_mat_00_4 = _mm256_add_epi16(iacc_mat_00_4_sp1, iacc_mat_00_4_sp2); + __m256i iacc_mat_01_4 = _mm256_add_epi16(iacc_mat_01_4_sp1, iacc_mat_01_4_sp2); + __m256i iacc_mat_10_4 = _mm256_add_epi16(iacc_mat_10_4_sp1, iacc_mat_10_4_sp2); + __m256i iacc_mat_11_4 = _mm256_add_epi16(iacc_mat_11_4_sp1, iacc_mat_11_4_sp2); + + __m256i iacc_mat_00_5 = _mm256_add_epi16(iacc_mat_00_5_sp1, iacc_mat_00_5_sp2); + __m256i iacc_mat_01_5 = _mm256_add_epi16(iacc_mat_01_5_sp1, iacc_mat_01_5_sp2); + __m256i iacc_mat_10_5 = _mm256_add_epi16(iacc_mat_10_5_sp1, iacc_mat_10_5_sp2); + __m256i iacc_mat_11_5 = _mm256_add_epi16(iacc_mat_11_5_sp1, iacc_mat_11_5_sp2); + + __m256i iacc_mat_00_6 = _mm256_add_epi16(iacc_mat_00_6_sp1, iacc_mat_00_6_sp2); + __m256i iacc_mat_01_6 = _mm256_add_epi16(iacc_mat_01_6_sp1, iacc_mat_01_6_sp2); + __m256i iacc_mat_10_6 = _mm256_add_epi16(iacc_mat_10_6_sp1, iacc_mat_10_6_sp2); + __m256i iacc_mat_11_6 = _mm256_add_epi16(iacc_mat_11_6_sp1, iacc_mat_11_6_sp2); + + __m256i iacc_mat_00_7 = _mm256_add_epi16(iacc_mat_00_7_sp1, iacc_mat_00_7_sp2); + __m256i iacc_mat_01_7 = _mm256_add_epi16(iacc_mat_01_7_sp1, iacc_mat_01_7_sp2); + __m256i iacc_mat_10_7 = _mm256_add_epi16(iacc_mat_10_7_sp1, iacc_mat_10_7_sp2); + __m256i iacc_mat_11_7 = _mm256_add_epi16(iacc_mat_11_7_sp1, iacc_mat_11_7_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + iacc_mat_00_0 = _mm256_madd_epi16(iacc_mat_00_0, scale_0145_0); + iacc_mat_01_0 = _mm256_madd_epi16(iacc_mat_01_0, scale_2367_0); + iacc_mat_10_0 = _mm256_madd_epi16(iacc_mat_10_0, scale_0145_0); + iacc_mat_11_0 = _mm256_madd_epi16(iacc_mat_11_0, scale_2367_0); + + iacc_mat_00_1 = _mm256_madd_epi16(iacc_mat_00_1, scale_0145_1); + iacc_mat_01_1 = _mm256_madd_epi16(iacc_mat_01_1, scale_2367_1); + iacc_mat_10_1 = _mm256_madd_epi16(iacc_mat_10_1, scale_0145_1); + iacc_mat_11_1 = _mm256_madd_epi16(iacc_mat_11_1, scale_2367_1); + + iacc_mat_00_2 = _mm256_madd_epi16(iacc_mat_00_2, scale_0145_2); + iacc_mat_01_2 = _mm256_madd_epi16(iacc_mat_01_2, scale_2367_2); + iacc_mat_10_2 = _mm256_madd_epi16(iacc_mat_10_2, scale_0145_2); + iacc_mat_11_2 = _mm256_madd_epi16(iacc_mat_11_2, scale_2367_2); + + iacc_mat_00_3 = _mm256_madd_epi16(iacc_mat_00_3, scale_0145_3); + iacc_mat_01_3 = _mm256_madd_epi16(iacc_mat_01_3, scale_2367_3); + iacc_mat_10_3 = _mm256_madd_epi16(iacc_mat_10_3, scale_0145_3); + iacc_mat_11_3 = _mm256_madd_epi16(iacc_mat_11_3, scale_2367_3); + + iacc_mat_00_4 = _mm256_madd_epi16(iacc_mat_00_4, scale_0145_4); + iacc_mat_01_4 = _mm256_madd_epi16(iacc_mat_01_4, scale_2367_4); + iacc_mat_10_4 = _mm256_madd_epi16(iacc_mat_10_4, scale_0145_4); + iacc_mat_11_4 = _mm256_madd_epi16(iacc_mat_11_4, scale_2367_4); + + iacc_mat_00_5 = _mm256_madd_epi16(iacc_mat_00_5, scale_0145_5); + iacc_mat_01_5 = _mm256_madd_epi16(iacc_mat_01_5, scale_2367_5); + iacc_mat_10_5 = _mm256_madd_epi16(iacc_mat_10_5, scale_0145_5); + iacc_mat_11_5 = _mm256_madd_epi16(iacc_mat_11_5, scale_2367_5); + + iacc_mat_00_6 = _mm256_madd_epi16(iacc_mat_00_6, scale_0145_6); + iacc_mat_01_6 = _mm256_madd_epi16(iacc_mat_01_6, scale_2367_6); + iacc_mat_10_6 = _mm256_madd_epi16(iacc_mat_10_6, scale_0145_6); + iacc_mat_11_6 = _mm256_madd_epi16(iacc_mat_11_6, scale_2367_6); + + iacc_mat_00_7 = _mm256_madd_epi16(iacc_mat_00_7, scale_0145_7); + iacc_mat_01_7 = _mm256_madd_epi16(iacc_mat_01_7, scale_2367_7); + iacc_mat_10_7 = _mm256_madd_epi16(iacc_mat_10_7, scale_0145_7); + iacc_mat_11_7 = _mm256_madd_epi16(iacc_mat_11_7, scale_2367_7); + + __m256i iacc_mat_00 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_00_0, iacc_mat_00_1), _mm256_add_epi32(iacc_mat_00_2, iacc_mat_00_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_00_4, iacc_mat_00_5), _mm256_add_epi32(iacc_mat_00_6, iacc_mat_00_7))); + __m256i iacc_mat_01 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_01_0, iacc_mat_01_1), _mm256_add_epi32(iacc_mat_01_2, iacc_mat_01_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_01_4, iacc_mat_01_5), _mm256_add_epi32(iacc_mat_01_6, iacc_mat_01_7))); + __m256i iacc_mat_10 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_10_0, iacc_mat_10_1), _mm256_add_epi32(iacc_mat_10_2, iacc_mat_10_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_10_4, iacc_mat_10_5), _mm256_add_epi32(iacc_mat_10_6, iacc_mat_10_7))); + __m256i iacc_mat_11 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_11_0, iacc_mat_11_1), _mm256_add_epi32(iacc_mat_11_2, iacc_mat_11_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_11_4, iacc_mat_11_5), _mm256_add_epi32(iacc_mat_11_6, iacc_mat_11_7))); + + // Straighten out to make 4 row vectors + __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); + __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); + __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); + __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); + + // Load the scale(d) values for all the 4 Q8_k blocks and repeat it across lanes + const __m128 row_scale_f32_sse = _mm_load_ps(a_ptrs[rp][b].d); + const __m256 row_scale_f32 = _mm256_set_m128(row_scale_f32_sse, row_scale_f32_sse); + + // Multiply with appropiate scales and accumulate (for both d and dmin) below + acc_rows[rp * 4] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); + acc_rows[rp * 4 + 1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); + acc_rows[rp * 4 + 2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); + acc_rows[rp * 4 + 3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); + + __m256i lhs_bsums_01_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_0123), lhs_raw_bsums_01_0123, 1); + __m256i lhs_bsums_23_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_0123), lhs_raw_bsums_23_0123, 1); + __m256i lhs_bsums_01_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_4567), lhs_raw_bsums_01_4567, 1); + __m256i lhs_bsums_23_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_4567), lhs_raw_bsums_23_4567, 1); + + // Take two bsums from two Q8_Ks at a time and multiply with corresponding mins values from each Q2_K + __m256i iacc_row_min_0_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 0), mins_01); + __m256i iacc_row_min_1_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 170), mins_01); + __m256i iacc_row_min_2_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 0), mins_01); + __m256i iacc_row_min_3_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 170), mins_01); + + __m256i iacc_row_min_0_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 85), mins_23); + __m256i iacc_row_min_1_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 255), mins_23); + __m256i iacc_row_min_2_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 85), mins_23); + __m256i iacc_row_min_3_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 255), mins_23); + + __m256i iacc_row_min_0_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 0), mins_45); + __m256i iacc_row_min_1_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 170), mins_45); + __m256i iacc_row_min_2_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 0), mins_45); + __m256i iacc_row_min_3_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 170), mins_45); + + __m256i iacc_row_min_0_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 85), mins_67); + __m256i iacc_row_min_1_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 255), mins_67); + __m256i iacc_row_min_2_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 85), mins_67); + __m256i iacc_row_min_3_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 255), mins_67); + + __m256i iacc_row_min_0 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_0_01, iacc_row_min_0_23), _mm256_add_epi32(iacc_row_min_0_45,iacc_row_min_0_67)); + __m256i iacc_row_min_1 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_1_01, iacc_row_min_1_23), _mm256_add_epi32(iacc_row_min_1_45,iacc_row_min_1_67)); + __m256i iacc_row_min_2 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_2_01, iacc_row_min_2_23), _mm256_add_epi32(iacc_row_min_2_45,iacc_row_min_2_67)); + __m256i iacc_row_min_3 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_3_01, iacc_row_min_3_23), _mm256_add_epi32(iacc_row_min_3_45,iacc_row_min_3_67)); + + acc_min_rows[rp * 4] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_0), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_min_rows[rp * 4]); + acc_min_rows[rp * 4 + 1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_1), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_min_rows[rp * 4 + 1]); + acc_min_rows[rp * 4 + 2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_2), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_min_rows[rp * 4 + 2]); + acc_min_rows[rp * 4 + 3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_3), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_min_rows[rp * 4 + 3]); + + } + } + } + // Store the accumulated values + for (int i = 0; i < 16; i++) { + _mm256_storeu_ps((float * )(s + ((y * 4 + i) * bs + x * 8)), _mm256_sub_ps(acc_rows[i], acc_min_rows[i])); + + } + } + } + + for (; y < nr / 4; y ++) { + + const block_q8_Kx4 * a_ptr = a_ptr_start + (y * nb); + + // Take group of eight block_q2_kx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = xstart; x < nc / 8; x++) { + + const block_q2_Kx8 * b_ptr = b_ptr_start + (x * b_nb); + + // Master FP accumulators + __m256 acc_rows[4]; + for (int i = 0; i < 4; i++) { + acc_rows[i] = _mm256_setzero_ps(); + } + + __m256 acc_min_rows[4]; + for (int i = 0; i < 4; i++) { + acc_min_rows[i] = _mm256_setzero_ps(); + } + + for (int64_t b = 0; b < nb; b++) { + // Delta values - Load the eight scale values of block_q2_kx8 + const __m256 col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); + + // dmin values - Load the eight dmin values of block_q2_kx8 + const __m256 col_dmin_f32 = GGML_F32Cx8_LOAD(b_ptr[b].dmin); + + // Loop to iterate over the sixteen sub blocks of a super block - eight sub blocks are processed per iteration + for (int sb = 0; sb < QK_K / 128; sb++) { + + // Load the eight block_q2_k for eight sub blocks quantized values interleaved with each other in chunks of eight bytes - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + sb * 256)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_0123_2 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_4567_2 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_0123_3 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_4567_3 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 224 + sb * 256)); + + // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of values + //superblock sub block which part of sub block + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + const __m256i rhs_raw_mat_0145_2 = _mm256_blend_epi32(rhs_raw_mat_0123_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_2, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_2, requiredOrder), rhs_raw_mat_4567_2, 240); + + const __m256i rhs_raw_mat_0145_3 = _mm256_blend_epi32(rhs_raw_mat_0123_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_3, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_3, requiredOrder), rhs_raw_mat_4567_3, 240); + + // 2-bit -> 8-bit + // First sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_00 = _mm256_and_si256(rhs_raw_mat_0145_0, m3b); //B00(0-7) B01(0-7) B04(0-7) B05(0-7) + const __m256i rhs_mat_2367_00 = _mm256_and_si256(rhs_raw_mat_2367_0, m3b); //B02(0-7) B03(0-7) B06(0-7) B07(0-7) + + const __m256i rhs_mat_0145_01 = _mm256_and_si256(rhs_raw_mat_0145_1, m3b); //B00(8-15) B01(8-15) B04(8-15) B05(8-15) + const __m256i rhs_mat_2367_01 = _mm256_and_si256(rhs_raw_mat_2367_1, m3b); //B02(8-15) B03(8-15) B06(8-15) B07(8-15) + + // Second sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_10 = _mm256_and_si256(rhs_raw_mat_0145_2, m3b); //B10(0-7) B11(0-7) B14(0-7) B15(0-7) + const __m256i rhs_mat_2367_10 = _mm256_and_si256(rhs_raw_mat_2367_2, m3b); //B12(0-7) B13(0-7) B16(0-7) B17(0-7) + + const __m256i rhs_mat_0145_11 = _mm256_and_si256(rhs_raw_mat_0145_3, m3b); //B10(8-15) B11(8-15) B14(8-15) B15(8-15) + const __m256i rhs_mat_2367_11 = _mm256_and_si256(rhs_raw_mat_2367_3, m3b); //B12(8-15) B13(8-15) B16(8-15) B17(8-15) + + // Third sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 2), m3b); //B20(0-7) B21(0-7) B24(0-7) B25(0-7) + const __m256i rhs_mat_2367_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 2), m3b); //B22(0-7) B23(0-7) B26(0-7) B27(0-7) + + const __m256i rhs_mat_0145_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 2), m3b); //B20(8-15) B21(8-15) B24(8-15) B25(8-15) + const __m256i rhs_mat_2367_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 2), m3b); //B22(8-15) B23(8-15) B26(8-15) B27(8-15) + + // Fourth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 2), m3b); //B30(0-7) B31(0-7) B34(0-7) B35(0-7) + const __m256i rhs_mat_2367_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 2), m3b); //B32(0-7) B33(0-7) B36(0-7) B37(0-7) + + const __m256i rhs_mat_0145_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 2), m3b); //B30(8-15) B31(8-15) B34(8-15) B35(8-15) + const __m256i rhs_mat_2367_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 2), m3b); //B32(8-15) B33(8-15) B36(8-15) B37(8-15) + + // Fifth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m3b); //B40(0-7) B41(0-7) B44(0-7) B45(0-7) + const __m256i rhs_mat_2367_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m3b); //B42(0-7) B43(0-7) B46(0-7) B47(0-7) + + const __m256i rhs_mat_0145_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m3b); //B40(8-15) B41(8-15) B44(8-15) B45(8-15) + const __m256i rhs_mat_2367_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m3b); //B42(8-15) B43(8-15) B46(8-15) B47(8-15) + + // Sixth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 4), m3b); //B50(0-7) B51(0-7) B54(0-7) B55(0-7) + const __m256i rhs_mat_2367_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 4), m3b); //B52(0-7) B53(0-7) B56(0-7) B57(0-7) + + const __m256i rhs_mat_0145_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 4), m3b); //B50(8-15) B51(8-15) B54(8-15) B55(8-15) + const __m256i rhs_mat_2367_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 4), m3b); //B52(8-15) B53(8-15) B56(8-15) B57(8-15) + + // Seventh sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 6), m3b); //B60(0-7) B61(0-7) B64(0-7) B65(0-7) + const __m256i rhs_mat_2367_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 6), m3b); //B62(0-7) B63(0-7) B66(0-7) B67(0-7) + + const __m256i rhs_mat_0145_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 6), m3b); //B60(8-15) B61(8-15) B64(8-15) B65(8-15) + const __m256i rhs_mat_2367_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 6), m3b); //B62(8-15) B63(8-15) B66(8-15) B67(8-15) + + // Eighth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 6), m3b); //B70(0-7) B71(0-7) B74(0-7) B75(0-7) + const __m256i rhs_mat_2367_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 6), m3b); //B72(0-7) B73(0-7) B76(0-7) B77(0-7) + + const __m256i rhs_mat_0145_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 6), m3b); //B70(8-15) B71(8-15) B74(8-15) B75(8-15) + const __m256i rhs_mat_2367_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 6), m3b); //B72(8-15) B73(8-15) B76(8-15) B77(8-15) + + // Shuffle pattern one - right side input + const __m256i rhs_mat_0145_00_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_00, 136); //B00(0-3) B01(0-3) B00(0-3) B01(0-3) B04(0-3) B05(0-3) B04(0-3) B05(0-3) + const __m256i rhs_mat_2367_00_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_00, 136); //B02(0-3) B03(0-3) B02(0-3) B03(0-3) B06(0-3) B07(0-3) B06(0-3) B07(0-3) + + const __m256i rhs_mat_0145_01_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_01, 136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) + const __m256i rhs_mat_2367_01_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_01, 136); //B02(8-11) B03(8-11) B02(8-11) B03(8-11) B06(8-11) B07(8-11) B06(8-11) B07(8-11) + + const __m256i rhs_mat_0145_10_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_10, 136); //B10(0-3) B11(0-3) B10(0-3) B11(0-3) B14(0-3) B15(0-3) B14(0-3) B15(0-3) + const __m256i rhs_mat_2367_10_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_10, 136); //B12(0-3) B13(0-3) B12(0-3) B13(0-3) B16(0-3) B17(0-3) B16(0-3) B17(0-3) + + const __m256i rhs_mat_0145_11_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_11, 136); //B10(8-11) B11(8-11) B10(8-11) B11(8-11) B14(8-11) B15(8-11) B14(8-11) B15(8-11) + const __m256i rhs_mat_2367_11_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_11, 136); //B12(8-11) B13(8-11) B12(8-11) B13(8-11) B16(8-11) B17(8-11) B16(8-11) B17(8-11) + + const __m256i rhs_mat_0145_20_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_20, 136); //B20(0-3) B21(0-3) B20(0-3) B21(0-3) B24(0-3) B25(0-3) B24(0-3) B25(0-3) + const __m256i rhs_mat_2367_20_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_20, 136); //B22(0-3) B23(0-3) B22(0-3) B23(0-3) B26(0-3) B27(0-3) B26(0-3) B27(0-3) + + const __m256i rhs_mat_0145_21_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_21, 136); //B20(8-11) B21(8-11) B20(8-11) B21(8-11) B24(8-11) B25(8-11) B24(8-11) B25(8-11) + const __m256i rhs_mat_2367_21_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_21, 136); //B22(8-11) B23(8-11) B22(8-11) B23(8-11) B26(8-11) B27(8-11) B26(8-11) B27(8-11) + + const __m256i rhs_mat_0145_30_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_30, 136); //B30(0-3) B31(0-3) B30(0-3) B31(0-3) B34(0-3) B35(0-3) B34(0-3) B35(0-3) + const __m256i rhs_mat_2367_30_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_30, 136); //B32(0-3) B33(0-3) B32(0-3) B33(0-3) B36(0-3) B37(0-3) B36(0-3) B37(0-3) + + const __m256i rhs_mat_0145_31_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_31, 136); //B30(8-11) B31(8-11) B30(8-11) B31(8-11) B34(8-11) B35(8-11) B34(8-11) B35(8-11 + const __m256i rhs_mat_2367_31_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_31, 136); //B32(8-11) B33(8-11) B32(8-11) B33(8-11) B36(8-11) B37(8-11) B36(8-11) B37(8-11) + + const __m256i rhs_mat_0145_40_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_40, 136); //B40(0-3) B41(0-3) B40(0-3) B41(0-3) B44(0-3) B45(0-3) B44(0-3) B45(0-3) + const __m256i rhs_mat_2367_40_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_40, 136); //B42(0-3) B43(0-3) B42(0-3) B43(0-3) B46(0-3) B47(0-3) B46(0-3) B47(0-3) + + const __m256i rhs_mat_0145_41_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_41, 136); //B40(8-11) B41(8-11) B40(8-11) B41(8-11) B44(8-11) B45(8-11) B44(8-11) B45(8-11) + const __m256i rhs_mat_2367_41_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_41, 136); //B42(8-11) B43(8-11) B42(8-11) B43(8-11) B46(8-11) B47(8-11) B46(8-11) B47(8-11) + + const __m256i rhs_mat_0145_50_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_50, 136); //B50(0-3) B51(0-3) B50(0-3) B51(0-3) B54(0-3) B55(0-3) B54(0-3) B55(0-3) + const __m256i rhs_mat_2367_50_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_50, 136); //B52(0-3) B53(0-3) B52(0-3) B53(0-3) B56(0-3) B57(0-3) B56(0-3) B57(0-3) + + const __m256i rhs_mat_0145_51_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_51, 136); //B50(8-11) B51(8-11) B50(8-11) B51(8-11) B54(8-11) B55(8-11) B54(8-11) B55(8-11) + const __m256i rhs_mat_2367_51_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_51, 136); //B52(8-11) B53(8-11) B52(8-11) B53(8-11) B56(8-11) B57(8-11) B56(8-11) B57(8-11) + + const __m256i rhs_mat_0145_60_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_60, 136); //B60(0-3) B61(0-3) B60(0-3) B61(0-3) B64(0-3) B65(0-3) B64(0-3) B65(0-3) + const __m256i rhs_mat_2367_60_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_60, 136); //B62(0-3) B63(0-3) B62(0-3) B63(0-3) B66(0-3) B67(0-3) B66(0-3) B67(0-3) + + const __m256i rhs_mat_0145_61_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_61, 136); //B60(8-11) B61(8-11) B60(8-11) B61(8-11) B64(8-11) B65(8-11) B64(8-11) B65(8-11) + const __m256i rhs_mat_2367_61_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_61, 136); //B62(8-11) B63(8-11) B62(8-11) B63(8-11) B66(8-11) B67(8-11) B66(8-11) B67(8-11) + + const __m256i rhs_mat_0145_70_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_70, 136); //B70(0-3) B71(0-3) B70(0-3) B71(0-3) B74(0-3) B75(0-3) B74(0-3) B75(0-3) + const __m256i rhs_mat_2367_70_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_70, 136); //B72(0-3) B73(0-3) B72(0-3) B73(0-3) B76(0-3) B77(0-3) B76(0-3) B77(0-3) + + const __m256i rhs_mat_0145_71_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_71, 136); //B70(8-11) B71(8-11) B70(8-11) B71(8-11) B74(8-11) B75(8-11) B74(8-11) B75(8-11) + const __m256i rhs_mat_2367_71_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_71, 136); //B72(8-11) B73(8-11) B72(8-11) B73(8-11) B76(8-11) B77(8-11) B76(8-11) B77(8-11) + + + // Shuffle pattern two - right side input + const __m256i rhs_mat_0145_00_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_00, 221); //B00(4-7) B01(4-7) B00(4-7) B01(4-7) B04(4-7) B05(4-7) B04(4-7) B05(4-7) + const __m256i rhs_mat_2367_00_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_00, 221); //B02(4-7) B03(4-7) B02(4-7) B03(4-7) B06(4-7) B07(4-7) B06(4-7) B07(4-7) + + const __m256i rhs_mat_0145_01_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_01, 221); //B00(12-15) B01(12-15) B00(12-15) B01(12-15) B04(12-15) B05(12-15) B04(12-15) B05(12-15) + const __m256i rhs_mat_2367_01_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_01, 221); //B02(12-15) B03(12-15) B02(12-15) B03(12-15) B06(12-15) B07(12-15) B06(12-15) B07(12-15) + + const __m256i rhs_mat_0145_10_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_10, 221); //B10(4-7) B11(4-7) B10(4-7) B11(4-7) B14(4-7) B15(4-7) B14(4-7) B15(4-7) + const __m256i rhs_mat_2367_10_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_10, 221); //B12(4-7) B13(4-7) B12(4-7) B13(4-7) B16(4-7) B17(4-7) B16(4-7) B17(4-7) + + const __m256i rhs_mat_0145_11_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_11, 221); //B10(12-15) B11(12-15) B10(12-15) B11(12-15) B14(12-15) B15(12-15) B14(12-15) B15(12-15) + const __m256i rhs_mat_2367_11_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_11, 221); //B12(12-15) B13(12-15) B12(12-15) B13(12-15) B16(12-15) B17(12-15) B16(12-15) B17(12-15) + + const __m256i rhs_mat_0145_20_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_20, 221); //B20(4-7) B21(4-7) B20(4-7) B21(4-7) B24(4-7) B25(4-7) B24(4-7) B25(4-7) + const __m256i rhs_mat_2367_20_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_20, 221); //B22(4-7) B23(4-7) B22(4-7) B23(4-7) B26(4-7) B27(4-7) B26(4-7) B27(4-7) + + const __m256i rhs_mat_0145_21_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_21, 221); //B20(12-15) B21(12-15) B20(12-15) B21(12-15) B24(12-15) B25(12-15) B24(12-15) B25(12-15) + const __m256i rhs_mat_2367_21_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_21, 221); //B22(12-15) B23(12-15) B22(12-15) B23(12-15) B26(12-15) B27(12-15) B26(12-15) B27(12-15) + + const __m256i rhs_mat_0145_30_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_30, 221); //B30(4-7) B31(4-7) B30(4-7) B31(4-7) B34(4-7) B35(4-7) B34(4-7) B35(4-7) + const __m256i rhs_mat_2367_30_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_30, 221); //B32(4-7) B33(4-7) B32(4-7) B33(4-7) B36(4-7) B37(4-7) B36(4-7) B37(4-7) + + const __m256i rhs_mat_0145_31_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_31, 221); //B30(12-15) B31(12-15) B30(12-15) B31(12-15) B34(12-15) B35(12-15) B34(12-15) B35(12-15) + const __m256i rhs_mat_2367_31_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_31, 221); //B32(12-15) B33(12-15) B32(12-15) B33(12-15) B36(12-15) B37(12-15) B36(12-15) B37(12-15) + + const __m256i rhs_mat_0145_40_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_40, 221); //B40(4-7) B41(4-7) B40(4-7) B41(4-7) B44(4-7) B45(4-7) B44(4-7) B45(4-7) + const __m256i rhs_mat_2367_40_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_40, 221); //B42(4-7) B43(4-7) B42(4-7) B43(4-7) B46(4-7) B47(4-7) B46(4-7) B47(4-7) + + const __m256i rhs_mat_0145_41_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_41, 221); //B40(12-15) B41(12-15) B40(12-15) B41(12-15) B44(12-15) B45(12-15) B44(12-15) B45(12-15) + const __m256i rhs_mat_2367_41_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_41, 221); //B42(12-15) B43(12-15) B42(12-15) B43(12-15) B46(12-15) B47(12-15) B46(12-15) B47(12-15) + + const __m256i rhs_mat_0145_50_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_50, 221); //B50(4-7) B51(4-7) B50(4-7) B51(4-7) B54(4-7) B55(4-7) B54(4-7) B55(4-7) + const __m256i rhs_mat_2367_50_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_50, 221); //B52(4-7) B53(4-7) B52(4-7) B53(4-7) B56(4-7) B57(4-7) B56(4-7) B57(4-7) + + const __m256i rhs_mat_0145_51_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_51, 221); //B50(12-15) B51(12-15) B50(12-15) B51(12-15) B54(12-15) B55(12-15) B54(12-15) B55(12-15) + const __m256i rhs_mat_2367_51_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_51, 221); //B52(12-15) B53(12-15) B52(12-15) B53(12-15) B56(12-15) B57(12-15) B56(12-15) B57(12-15) + + const __m256i rhs_mat_0145_60_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_60, 221); //B60(4-7) B61(4-7) B60(4-7) B61(4-7) B64(4-7) B65(4-7) B64(4-7) B65(4-7) + const __m256i rhs_mat_2367_60_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_60, 221); //B62(4-7) B63(4-7) B62(4-7) B63(4-7) B66(4-7) B67(4-7) B66(4-7) B67(4-7) + + const __m256i rhs_mat_0145_61_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_61, 221); //B60(12-15) B61(12-15) B60(12-15) B61(12-15) B64(12-15) B65(12-15) B64(12-15) B65(12-15) + const __m256i rhs_mat_2367_61_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_61, 221); //B62(12-15) B63(12-15) B62(12-15) B63(12-15) B66(12-15) B67(12-15) B66(12-15) B67(12-15) + + const __m256i rhs_mat_0145_70_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_70, 221); //B70(4-7) B71(4-7) B70(4-7) B71(4-7) B74(4-7) B75(4-7) B74(4-7) B75(4-7) + const __m256i rhs_mat_2367_70_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_70, 221); //B72(4-7) B73(4-7) B72(4-7) B73(4-7) B76(4-7) B77(4-7) B76(4-7) B77(4-7) + + const __m256i rhs_mat_0145_71_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_71, 221); //B70(12-15) B71(12-15) B70(12-15) B71(12-15) B74(12-15) B75(12-15) B74(12-15) B75(12-15) + const __m256i rhs_mat_2367_71_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_71, 221); //B72(12-15) B73(12-15) B72(12-15) B73(12-15) B76(12-15) B77(12-15) B76(12-15) B77(12-15) + + + //Scales and Mins of corresponding sub blocks from different Q2_K structures are stored together + //s00 m00 s01 m01 s10 m10 s11 m11 s20 m20 s21 m21 s30 m30 s31 m31 s40 m40 s41 m41 s50 m50 s51 m51 s60 m60 s61 m61 s70 m70 s71 m71 + + // Combine mins and scales for sub-blocks: 0-1, 2-3, 4-5, 6-7 in the sb loop + const __m128i mins_and_scales_01 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + sb * 64)); + const __m128i mins_and_scales_23 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 48 + sb * 64)); + + // Extract scales which is lower half from mins_and_scales + const __m128i scales_01 = _mm_and_si128(mins_and_scales_01, m4b_sse); + const __m128i scales_23 = _mm_and_si128(mins_and_scales_23, m4b_sse); + const __m128i scales_45 = _mm_and_si128(mins_and_scales_45, m4b_sse); + const __m128i scales_67 = _mm_and_si128(mins_and_scales_67, m4b_sse); + + // Extract mins which is upper half from mins_and_scales + const __m256i mins_01 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_01, 4), m4b_sse)); + const __m256i mins_23 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_23, 4), m4b_sse)); + const __m256i mins_45 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_45, 4), m4b_sse)); + const __m256i mins_67 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_67, 4), m4b_sse)); + + const __m256i scales_0 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_01, scalesmask1_sse)); + const __m256i scales_1 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_01, scalesmask2_sse)); + + const __m256i scales_2 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_23, scalesmask1_sse)); + const __m256i scales_3 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_23, scalesmask2_sse)); + + const __m256i scales_4 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_45, scalesmask1_sse)); + const __m256i scales_5 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_45, scalesmask2_sse)); + + const __m256i scales_6 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_67, scalesmask1_sse)); + const __m256i scales_7 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_67, scalesmask2_sse)); + + const __m256i scale_0145_0 = _mm256_shuffle_epi32(scales_0, 68); + const __m256i scale_2367_0 = _mm256_shuffle_epi32(scales_0, 238); + + const __m256i scale_0145_1 = _mm256_shuffle_epi32(scales_1, 68); + const __m256i scale_2367_1 = _mm256_shuffle_epi32(scales_1, 238); + + const __m256i scale_0145_2 = _mm256_shuffle_epi32(scales_2, 68); + const __m256i scale_2367_2 = _mm256_shuffle_epi32(scales_2, 238); + + const __m256i scale_0145_3 = _mm256_shuffle_epi32(scales_3, 68); + const __m256i scale_2367_3 = _mm256_shuffle_epi32(scales_3, 238); + + const __m256i scale_0145_4 = _mm256_shuffle_epi32(scales_4, 68); + const __m256i scale_2367_4 = _mm256_shuffle_epi32(scales_4, 238); + + const __m256i scale_0145_5 = _mm256_shuffle_epi32(scales_5, 68); + const __m256i scale_2367_5 = _mm256_shuffle_epi32(scales_5, 238); + + const __m256i scale_0145_6 = _mm256_shuffle_epi32(scales_6, 68); + const __m256i scale_2367_6 = _mm256_shuffle_epi32(scales_6, 238); + + const __m256i scale_0145_7 = _mm256_shuffle_epi32(scales_7, 68); + const __m256i scale_2367_7 = _mm256_shuffle_epi32(scales_7, 238); + + // Load the four block_q8_k quantized values interleaved with each other in chunks of eight bytes - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated into a 256 bit vector + __m256i lhs_mat_0123_00 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 512 * sb))); + __m256i lhs_mat_01_00 = _mm256_permute2f128_si256(lhs_mat_0123_00, lhs_mat_0123_00, 0); + __m256i lhs_mat_23_00 = _mm256_permute2f128_si256(lhs_mat_0123_00, lhs_mat_0123_00, 17); + __m256i lhs_mat_0123_01 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 32 + 512 * sb))); + __m256i lhs_mat_01_01 = _mm256_permute2f128_si256(lhs_mat_0123_01, lhs_mat_0123_01, 0); + __m256i lhs_mat_23_01 = _mm256_permute2f128_si256(lhs_mat_0123_01, lhs_mat_0123_01, 17); + __m256i lhs_mat_0123_10 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 64 + 512 * sb))); + __m256i lhs_mat_01_10 = _mm256_permute2f128_si256(lhs_mat_0123_10, lhs_mat_0123_10, 0); + __m256i lhs_mat_23_10 = _mm256_permute2f128_si256(lhs_mat_0123_10, lhs_mat_0123_10, 17); + __m256i lhs_mat_0123_11 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 96 + 512 * sb))); + __m256i lhs_mat_01_11 = _mm256_permute2f128_si256(lhs_mat_0123_11, lhs_mat_0123_11, 0); + __m256i lhs_mat_23_11 = _mm256_permute2f128_si256(lhs_mat_0123_11, lhs_mat_0123_11, 17); + __m256i lhs_mat_0123_20 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 128 + 512 * sb))); + __m256i lhs_mat_01_20 = _mm256_permute2f128_si256(lhs_mat_0123_20, lhs_mat_0123_20, 0); + __m256i lhs_mat_23_20 = _mm256_permute2f128_si256(lhs_mat_0123_20, lhs_mat_0123_20, 17); + __m256i lhs_mat_0123_21 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 160 + 512 * sb))); + __m256i lhs_mat_01_21 = _mm256_permute2f128_si256(lhs_mat_0123_21, lhs_mat_0123_21, 0); + __m256i lhs_mat_23_21 = _mm256_permute2f128_si256(lhs_mat_0123_21, lhs_mat_0123_21, 17); + __m256i lhs_mat_0123_30 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 192 + 512 * sb))); + __m256i lhs_mat_01_30 = _mm256_permute2f128_si256(lhs_mat_0123_30, lhs_mat_0123_30, 0); + __m256i lhs_mat_23_30 = _mm256_permute2f128_si256(lhs_mat_0123_30, lhs_mat_0123_30, 17); + __m256i lhs_mat_0123_31 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 224 + 512 * sb))); + __m256i lhs_mat_01_31 = _mm256_permute2f128_si256(lhs_mat_0123_31, lhs_mat_0123_31, 0); + __m256i lhs_mat_23_31 = _mm256_permute2f128_si256(lhs_mat_0123_31, lhs_mat_0123_31, 17); + + __m256i lhs_mat_0123_40 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 256 + 512 * sb))); + __m256i lhs_mat_01_40 = _mm256_permute2f128_si256(lhs_mat_0123_40, lhs_mat_0123_40, 0); + __m256i lhs_mat_23_40 = _mm256_permute2f128_si256(lhs_mat_0123_40, lhs_mat_0123_40, 17); + __m256i lhs_mat_0123_41 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 288 + 512 * sb))); + __m256i lhs_mat_01_41 = _mm256_permute2f128_si256(lhs_mat_0123_41, lhs_mat_0123_41, 0); + __m256i lhs_mat_23_41 = _mm256_permute2f128_si256(lhs_mat_0123_41, lhs_mat_0123_41, 17); + __m256i lhs_mat_0123_50 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 320 + 512 * sb))); + __m256i lhs_mat_01_50 = _mm256_permute2f128_si256(lhs_mat_0123_50, lhs_mat_0123_50, 0); + __m256i lhs_mat_23_50 = _mm256_permute2f128_si256(lhs_mat_0123_50, lhs_mat_0123_50, 17); + __m256i lhs_mat_0123_51 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 352 + 512 * sb))); + __m256i lhs_mat_01_51 = _mm256_permute2f128_si256(lhs_mat_0123_51, lhs_mat_0123_51, 0); + __m256i lhs_mat_23_51 = _mm256_permute2f128_si256(lhs_mat_0123_51, lhs_mat_0123_51, 17); + __m256i lhs_mat_0123_60 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 384 + 512 * sb))); + __m256i lhs_mat_01_60 = _mm256_permute2f128_si256(lhs_mat_0123_60, lhs_mat_0123_60, 0); + __m256i lhs_mat_23_60 = _mm256_permute2f128_si256(lhs_mat_0123_60, lhs_mat_0123_60, 17); + __m256i lhs_mat_0123_61 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 416 + 512 * sb))); + __m256i lhs_mat_01_61 = _mm256_permute2f128_si256(lhs_mat_0123_61, lhs_mat_0123_61, 0); + __m256i lhs_mat_23_61 = _mm256_permute2f128_si256(lhs_mat_0123_61, lhs_mat_0123_61, 17); + __m256i lhs_mat_0123_70 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 448 + 512 * sb))); + __m256i lhs_mat_01_70 = _mm256_permute2f128_si256(lhs_mat_0123_70, lhs_mat_0123_70, 0); + __m256i lhs_mat_23_70 = _mm256_permute2f128_si256(lhs_mat_0123_70, lhs_mat_0123_70, 17); + __m256i lhs_mat_0123_71 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 480 + 512 * sb))); + __m256i lhs_mat_01_71 = _mm256_permute2f128_si256(lhs_mat_0123_71, lhs_mat_0123_71, 0); + __m256i lhs_mat_23_71 = _mm256_permute2f128_si256(lhs_mat_0123_71, lhs_mat_0123_71, 17); + + // Bsums are loaded for the different Q8_K blocks + __m128i lhs_raw_bsums_01_0123 = _mm_loadu_si128((const __m128i *)((a_ptr[b].bsums + 32 * sb))); + __m128i lhs_raw_bsums_23_0123 = _mm_loadu_si128((const __m128i *)(a_ptr[b].bsums + 8 + 32 * sb)); + __m128i lhs_raw_bsums_01_4567 = _mm_loadu_si128((const __m128i *)((a_ptr[b].bsums + 16 + 32 * sb))); + __m128i lhs_raw_bsums_23_4567 = _mm_loadu_si128((const __m128i *)(a_ptr[b].bsums + 24 + 32 * sb)); + + // Shuffle pattern one - left side input + const __m256i lhs_mat_01_00_sp1 = _mm256_shuffle_epi32(lhs_mat_01_00, 160); //A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) + const __m256i lhs_mat_23_00_sp1 = _mm256_shuffle_epi32(lhs_mat_23_00, 160); //A02(0-3) A03(0-3) A02(0-3) A03(0-3) A02(0-3) A03(0-3) A02(0-3) A03(0-3) + + const __m256i lhs_mat_01_01_sp1 = _mm256_shuffle_epi32(lhs_mat_01_01, 160); //A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) + const __m256i lhs_mat_23_01_sp1 = _mm256_shuffle_epi32(lhs_mat_23_01, 160); //A02(8-11) A03(8-11) A02(8-11) A03(8-11) A02(8-11) A03(8-11) A02(8-11) A03(8-11) + + const __m256i lhs_mat_01_10_sp1 = _mm256_shuffle_epi32(lhs_mat_01_10, 160); //A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) + const __m256i lhs_mat_23_10_sp1 = _mm256_shuffle_epi32(lhs_mat_23_10, 160); //A12(0-3) A13(0-3) A12(0-3) A13(0-3) A12(0-3) A13(0-3) A12(0-3) A13(0-3) + + const __m256i lhs_mat_01_11_sp1 = _mm256_shuffle_epi32(lhs_mat_01_11, 160); //A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) + const __m256i lhs_mat_23_11_sp1 = _mm256_shuffle_epi32(lhs_mat_23_11, 160); //A12(8-11) A13(8-11) A12(8-11) A13(8-11) A12(8-11) A13(8-11) A12(8-11) A13(8-11) + + const __m256i lhs_mat_01_20_sp1 = _mm256_shuffle_epi32(lhs_mat_01_20, 160); //A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) + const __m256i lhs_mat_23_20_sp1 = _mm256_shuffle_epi32(lhs_mat_23_20, 160); //A22(0-3) A23(0-3) A22(0-3) A23(0-3) A22(0-3) A23(0-3) A22(0-3) A23(0-3) + + const __m256i lhs_mat_01_21_sp1 = _mm256_shuffle_epi32(lhs_mat_01_21, 160); //A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) + const __m256i lhs_mat_23_21_sp1 = _mm256_shuffle_epi32(lhs_mat_23_21, 160); //A22(8-11) A23(8-11) A22(8-11) A23(8-11) A22(8-11) A23(8-11) A22(8-11) A23(8-11) + + const __m256i lhs_mat_01_30_sp1 = _mm256_shuffle_epi32(lhs_mat_01_30, 160); //A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) + const __m256i lhs_mat_23_30_sp1 = _mm256_shuffle_epi32(lhs_mat_23_30, 160); //A32(0-3) A33(0-3) A32(0-3) A33(0-3) A32(0-3) A33(0-3) A32(0-3) A33(0-3) + + const __m256i lhs_mat_01_31_sp1 = _mm256_shuffle_epi32(lhs_mat_01_31, 160); //A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) + const __m256i lhs_mat_23_31_sp1 = _mm256_shuffle_epi32(lhs_mat_23_31, 160); //A32(8-11) A33(8-11) A32(8-11) A33(8-11) A32(8-11) A33(8-11) A32(8-11) A33(8-11) + + const __m256i lhs_mat_01_40_sp1 = _mm256_shuffle_epi32(lhs_mat_01_40, 160); //A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) + const __m256i lhs_mat_23_40_sp1 = _mm256_shuffle_epi32(lhs_mat_23_40, 160); //A42(0-3) A43(0-3) A42(0-3) A43(0-3) A42(0-3) A43(0-3) A42(0-3) A43(0-3) + + const __m256i lhs_mat_01_41_sp1 = _mm256_shuffle_epi32(lhs_mat_01_41, 160); //A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) + const __m256i lhs_mat_23_41_sp1 = _mm256_shuffle_epi32(lhs_mat_23_41, 160); //A42(8-11) A43(8-11) A42(8-11) A43(8-11) A42(8-11) A43(8-11) A42(8-11) A43(8-11) + + const __m256i lhs_mat_01_50_sp1 = _mm256_shuffle_epi32(lhs_mat_01_50, 160); //A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) + const __m256i lhs_mat_23_50_sp1 = _mm256_shuffle_epi32(lhs_mat_23_50, 160); //A52(0-3) A53(0-3) A52(0-3) A53(0-3) A52(0-3) A53(0-3) A52(0-3) A53(0-3) + + const __m256i lhs_mat_01_51_sp1 = _mm256_shuffle_epi32(lhs_mat_01_51, 160); //A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) + const __m256i lhs_mat_23_51_sp1 = _mm256_shuffle_epi32(lhs_mat_23_51, 160); //A52(8-11) A53(8-11) A52(8-11) A53(8-11) A52(8-11) A53(8-11) A52(8-11) A53(8-11) + + const __m256i lhs_mat_01_60_sp1 = _mm256_shuffle_epi32(lhs_mat_01_60, 160); //A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) + const __m256i lhs_mat_23_60_sp1 = _mm256_shuffle_epi32(lhs_mat_23_60, 160); //A62(0-3) A63(0-3) A62(0-3) A63(0-3) A62(0-3) A63(0-3) A62(0-3) A63(0-3) + + const __m256i lhs_mat_01_61_sp1 = _mm256_shuffle_epi32(lhs_mat_01_61, 160); //A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) + const __m256i lhs_mat_23_61_sp1 = _mm256_shuffle_epi32(lhs_mat_23_61, 160); //A62(8-11) A63(8-11) A62(8-11) A63(8-11) A62(8-11) A63(8-11) A62(8-11) A63(8-11) + + const __m256i lhs_mat_01_70_sp1 = _mm256_shuffle_epi32(lhs_mat_01_70, 160); //A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) + const __m256i lhs_mat_23_70_sp1 = _mm256_shuffle_epi32(lhs_mat_23_70, 160); //A72(0-3) A73(0-3) A72(0-3) A73(0-3) A72(0-3) A73(0-3) A72(0-3) A73(0-3) + + const __m256i lhs_mat_01_71_sp1 = _mm256_shuffle_epi32(lhs_mat_01_71, 160); //A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) + const __m256i lhs_mat_23_71_sp1 = _mm256_shuffle_epi32(lhs_mat_23_71, 160); //A72(8-11) A73(8-11) A72(8-11) A73(8-11) A72(8-11) A73(8-11) A72(8-11) A73(8-11) + + // Shuffle pattern two- left side input + const __m256i lhs_mat_01_00_sp2 = _mm256_shuffle_epi32(lhs_mat_01_00, 245); //A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) + const __m256i lhs_mat_23_00_sp2 = _mm256_shuffle_epi32(lhs_mat_23_00, 245); //A02(4-7) A03(4-7) A02(4-7) A03(4-7) A02(4-7) A03(4-7) A02(4-7) A03(4-7) + + const __m256i lhs_mat_01_01_sp2 = _mm256_shuffle_epi32(lhs_mat_01_01, 245); //A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) + const __m256i lhs_mat_23_01_sp2 = _mm256_shuffle_epi32(lhs_mat_23_01, 245); //A02(12-15) A03(12-15) A02(12-15) A03(12-15) A02(12-15) A03(12-15) A02(12-15) A03(12-15) + + const __m256i lhs_mat_01_10_sp2 = _mm256_shuffle_epi32(lhs_mat_01_10, 245); //A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) + const __m256i lhs_mat_23_10_sp2 = _mm256_shuffle_epi32(lhs_mat_23_10, 245); //A12(4-7) A13(4-7) A12(4-7) A13(4-7) A12(4-7) A13(4-7) A12(4-7) A13(4-7) + + const __m256i lhs_mat_01_11_sp2 = _mm256_shuffle_epi32(lhs_mat_01_11, 245); //A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) + const __m256i lhs_mat_23_11_sp2 = _mm256_shuffle_epi32(lhs_mat_23_11, 245); //A12(12-15) A13(12-15) A12(12-15) A13(12-15) A12(12-15) A13(12-15) A12(12-15) A13(12-15) + + const __m256i lhs_mat_01_20_sp2 = _mm256_shuffle_epi32(lhs_mat_01_20, 245); //A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) + const __m256i lhs_mat_23_20_sp2 = _mm256_shuffle_epi32(lhs_mat_23_20, 245); //A22(4-7) A23(4-7) A22(4-7) A23(4-7) A22(4-7) A23(4-7) A22(4-7) A23(4-7) + + const __m256i lhs_mat_01_21_sp2 = _mm256_shuffle_epi32(lhs_mat_01_21, 245); //A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) + const __m256i lhs_mat_23_21_sp2 = _mm256_shuffle_epi32(lhs_mat_23_21, 245); //A22(12-15) A23(12-15) A22(12-15) A23(12-15) A22(12-15) A23(12-15) A22(12-15) A23(12-15) + + const __m256i lhs_mat_01_30_sp2 = _mm256_shuffle_epi32(lhs_mat_01_30, 245); //A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) + const __m256i lhs_mat_23_30_sp2 = _mm256_shuffle_epi32(lhs_mat_23_30, 245); //A32(4-7) A33(4-7) A32(4-7) A33(4-7) A32(4-7) A33(4-7) A32(4-7) A33(4-7) + + const __m256i lhs_mat_01_31_sp2 = _mm256_shuffle_epi32(lhs_mat_01_31, 245); //A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) + const __m256i lhs_mat_23_31_sp2 = _mm256_shuffle_epi32(lhs_mat_23_31, 245); //A32(12-15) A33(12-15) A32(12-15) A33(12-15) A32(12-15) A33(12-15) A32(12-15) A33(12-15) + + const __m256i lhs_mat_01_40_sp2 = _mm256_shuffle_epi32(lhs_mat_01_40, 245); //A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) + const __m256i lhs_mat_23_40_sp2 = _mm256_shuffle_epi32(lhs_mat_23_40, 245); //A42(4-7) A43(4-7) A42(4-7) A43(4-7) A42(4-7) A43(4-7) A42(4-7) A43(4-7) + + const __m256i lhs_mat_01_41_sp2 = _mm256_shuffle_epi32(lhs_mat_01_41, 245); //A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) + const __m256i lhs_mat_23_41_sp2 = _mm256_shuffle_epi32(lhs_mat_23_41, 245); //A42(12-15) A43(12-15) A42(12-15) A43(12-15) A42(12-15) A43(12-15) A42(12-15) A43(12-15) + + const __m256i lhs_mat_01_50_sp2 = _mm256_shuffle_epi32(lhs_mat_01_50, 245); //A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) + const __m256i lhs_mat_23_50_sp2 = _mm256_shuffle_epi32(lhs_mat_23_50, 245); //A52(4-7) A53(4-7) A52(4-7) A53(4-7) A52(4-7) A53(4-7) A52(4-7) A53(4-7) + + const __m256i lhs_mat_01_51_sp2 = _mm256_shuffle_epi32(lhs_mat_01_51, 245); //A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) + const __m256i lhs_mat_23_51_sp2 = _mm256_shuffle_epi32(lhs_mat_23_51, 245); //A52(12-15) A53(12-15) A52(12-15) A53(12-15) A52(12-15) A53(12-15) A52(12-15) A53(12-15) + + const __m256i lhs_mat_01_60_sp2 = _mm256_shuffle_epi32(lhs_mat_01_60, 245); //A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) + const __m256i lhs_mat_23_60_sp2 = _mm256_shuffle_epi32(lhs_mat_23_60, 245); //A62(4-7) A63(4-7) A62(4-7) A63(4-7) A62(4-7) A63(4-7) A62(4-7) A63(4-7) + + const __m256i lhs_mat_01_61_sp2 = _mm256_shuffle_epi32(lhs_mat_01_61, 245); //A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) + const __m256i lhs_mat_23_61_sp2 = _mm256_shuffle_epi32(lhs_mat_23_61, 245); //A62(12-15) A63(12-15) A62(12-15) A63(12-15) A62(12-15) A63(12-15) A62(12-15) A63(12-15) + + const __m256i lhs_mat_01_70_sp2 = _mm256_shuffle_epi32(lhs_mat_01_70, 245); //A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) + const __m256i lhs_mat_23_70_sp2 = _mm256_shuffle_epi32(lhs_mat_23_70, 245); //A72(4-7) A73(4-7) A72(4-7) A73(4-7) A72(4-7) A73(4-7) A72(4-7) A73(4-7) + + const __m256i lhs_mat_01_71_sp2 = _mm256_shuffle_epi32(lhs_mat_01_71, 245); //A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) + const __m256i lhs_mat_23_71_sp2 = _mm256_shuffle_epi32(lhs_mat_23_71, 245); //A72(12-15) A73(12-15) A72(12-15) A73(12-15) A72(12-15) A73(12-15) A72(12-15) A73(12-15) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + __m256i iacc_mat_00_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp1, lhs_mat_01_00_sp1),_mm256_maddubs_epi16(rhs_mat_0145_01_sp1, lhs_mat_01_01_sp1)); + __m256i iacc_mat_01_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp1, lhs_mat_01_00_sp1),_mm256_maddubs_epi16(rhs_mat_2367_01_sp1, lhs_mat_01_01_sp1)); + + __m256i iacc_mat_10_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp1, lhs_mat_23_00_sp1),_mm256_maddubs_epi16(rhs_mat_0145_01_sp1, lhs_mat_23_01_sp1)); + __m256i iacc_mat_11_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp1, lhs_mat_23_00_sp1),_mm256_maddubs_epi16(rhs_mat_2367_01_sp1, lhs_mat_23_01_sp1)); + + __m256i iacc_mat_00_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp1, lhs_mat_01_10_sp1),_mm256_maddubs_epi16(rhs_mat_0145_11_sp1, lhs_mat_01_11_sp1)); + __m256i iacc_mat_01_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp1, lhs_mat_01_10_sp1),_mm256_maddubs_epi16(rhs_mat_2367_11_sp1, lhs_mat_01_11_sp1)); + + __m256i iacc_mat_10_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp1, lhs_mat_23_10_sp1),_mm256_maddubs_epi16(rhs_mat_0145_11_sp1, lhs_mat_23_11_sp1)); + __m256i iacc_mat_11_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp1, lhs_mat_23_10_sp1),_mm256_maddubs_epi16(rhs_mat_2367_11_sp1, lhs_mat_23_11_sp1)); + + __m256i iacc_mat_00_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp1, lhs_mat_01_20_sp1),_mm256_maddubs_epi16(rhs_mat_0145_21_sp1, lhs_mat_01_21_sp1)); + __m256i iacc_mat_01_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp1, lhs_mat_01_20_sp1),_mm256_maddubs_epi16(rhs_mat_2367_21_sp1, lhs_mat_01_21_sp1)); + + __m256i iacc_mat_10_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp1, lhs_mat_23_20_sp1),_mm256_maddubs_epi16(rhs_mat_0145_21_sp1, lhs_mat_23_21_sp1)); + __m256i iacc_mat_11_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp1, lhs_mat_23_20_sp1),_mm256_maddubs_epi16(rhs_mat_2367_21_sp1, lhs_mat_23_21_sp1)); + + __m256i iacc_mat_00_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp1, lhs_mat_01_30_sp1),_mm256_maddubs_epi16(rhs_mat_0145_31_sp1, lhs_mat_01_31_sp1)); + __m256i iacc_mat_01_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp1, lhs_mat_01_30_sp1),_mm256_maddubs_epi16(rhs_mat_2367_31_sp1, lhs_mat_01_31_sp1)); + + __m256i iacc_mat_10_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp1, lhs_mat_23_30_sp1),_mm256_maddubs_epi16(rhs_mat_0145_31_sp1, lhs_mat_23_31_sp1)); + __m256i iacc_mat_11_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp1, lhs_mat_23_30_sp1),_mm256_maddubs_epi16(rhs_mat_2367_31_sp1, lhs_mat_23_31_sp1)); + + __m256i iacc_mat_00_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp1, lhs_mat_01_40_sp1),_mm256_maddubs_epi16(rhs_mat_0145_41_sp1, lhs_mat_01_41_sp1)); + __m256i iacc_mat_01_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp1, lhs_mat_01_40_sp1),_mm256_maddubs_epi16(rhs_mat_2367_41_sp1, lhs_mat_01_41_sp1)); + + __m256i iacc_mat_10_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp1, lhs_mat_23_40_sp1),_mm256_maddubs_epi16(rhs_mat_0145_41_sp1, lhs_mat_23_41_sp1)); + __m256i iacc_mat_11_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp1, lhs_mat_23_40_sp1),_mm256_maddubs_epi16(rhs_mat_2367_41_sp1, lhs_mat_23_41_sp1)); + + __m256i iacc_mat_00_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp1, lhs_mat_01_50_sp1),_mm256_maddubs_epi16(rhs_mat_0145_51_sp1, lhs_mat_01_51_sp1)); + __m256i iacc_mat_01_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp1, lhs_mat_01_50_sp1),_mm256_maddubs_epi16(rhs_mat_2367_51_sp1, lhs_mat_01_51_sp1)); + + __m256i iacc_mat_10_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp1, lhs_mat_23_50_sp1),_mm256_maddubs_epi16(rhs_mat_0145_51_sp1, lhs_mat_23_51_sp1)); + __m256i iacc_mat_11_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp1, lhs_mat_23_50_sp1),_mm256_maddubs_epi16(rhs_mat_2367_51_sp1, lhs_mat_23_51_sp1)); + + __m256i iacc_mat_00_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp1, lhs_mat_01_60_sp1),_mm256_maddubs_epi16(rhs_mat_0145_61_sp1, lhs_mat_01_61_sp1)); + __m256i iacc_mat_01_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp1, lhs_mat_01_60_sp1),_mm256_maddubs_epi16(rhs_mat_2367_61_sp1, lhs_mat_01_61_sp1)); + + __m256i iacc_mat_10_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp1, lhs_mat_23_60_sp1),_mm256_maddubs_epi16(rhs_mat_0145_61_sp1, lhs_mat_23_61_sp1)); + __m256i iacc_mat_11_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp1, lhs_mat_23_60_sp1),_mm256_maddubs_epi16(rhs_mat_2367_61_sp1, lhs_mat_23_61_sp1)); + + __m256i iacc_mat_00_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp1, lhs_mat_01_70_sp1),_mm256_maddubs_epi16(rhs_mat_0145_71_sp1, lhs_mat_01_71_sp1)); + __m256i iacc_mat_01_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp1, lhs_mat_01_70_sp1),_mm256_maddubs_epi16(rhs_mat_2367_71_sp1, lhs_mat_01_71_sp1)); + + __m256i iacc_mat_10_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp1, lhs_mat_23_70_sp1),_mm256_maddubs_epi16(rhs_mat_0145_71_sp1, lhs_mat_23_71_sp1)); + __m256i iacc_mat_11_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp1, lhs_mat_23_70_sp1),_mm256_maddubs_epi16(rhs_mat_2367_71_sp1, lhs_mat_23_71_sp1)); + + + __m256i iacc_mat_00_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp2, lhs_mat_01_00_sp2),_mm256_maddubs_epi16(rhs_mat_0145_01_sp2, lhs_mat_01_01_sp2)); + __m256i iacc_mat_01_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp2, lhs_mat_01_00_sp2),_mm256_maddubs_epi16(rhs_mat_2367_01_sp2, lhs_mat_01_01_sp2)); + + __m256i iacc_mat_10_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp2, lhs_mat_23_00_sp2),_mm256_maddubs_epi16(rhs_mat_0145_01_sp2, lhs_mat_23_01_sp2)); + __m256i iacc_mat_11_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp2, lhs_mat_23_00_sp2),_mm256_maddubs_epi16(rhs_mat_2367_01_sp2, lhs_mat_23_01_sp2)); + + __m256i iacc_mat_00_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp2, lhs_mat_01_10_sp2),_mm256_maddubs_epi16(rhs_mat_0145_11_sp2, lhs_mat_01_11_sp2)); + __m256i iacc_mat_01_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp2, lhs_mat_01_10_sp2),_mm256_maddubs_epi16(rhs_mat_2367_11_sp2, lhs_mat_01_11_sp2)); + + __m256i iacc_mat_10_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp2, lhs_mat_23_10_sp2),_mm256_maddubs_epi16(rhs_mat_0145_11_sp2, lhs_mat_23_11_sp2)); + __m256i iacc_mat_11_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp2, lhs_mat_23_10_sp2),_mm256_maddubs_epi16(rhs_mat_2367_11_sp2, lhs_mat_23_11_sp2)); + + __m256i iacc_mat_00_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp2, lhs_mat_01_20_sp2),_mm256_maddubs_epi16(rhs_mat_0145_21_sp2, lhs_mat_01_21_sp2)); + __m256i iacc_mat_01_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp2, lhs_mat_01_20_sp2),_mm256_maddubs_epi16(rhs_mat_2367_21_sp2, lhs_mat_01_21_sp2)); + + __m256i iacc_mat_10_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp2, lhs_mat_23_20_sp2),_mm256_maddubs_epi16(rhs_mat_0145_21_sp2, lhs_mat_23_21_sp2)); + __m256i iacc_mat_11_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp2, lhs_mat_23_20_sp2),_mm256_maddubs_epi16(rhs_mat_2367_21_sp2, lhs_mat_23_21_sp2)); + + __m256i iacc_mat_00_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp2, lhs_mat_01_30_sp2),_mm256_maddubs_epi16(rhs_mat_0145_31_sp2, lhs_mat_01_31_sp2)); + __m256i iacc_mat_01_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp2, lhs_mat_01_30_sp2),_mm256_maddubs_epi16(rhs_mat_2367_31_sp2, lhs_mat_01_31_sp2)); + + __m256i iacc_mat_10_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp2, lhs_mat_23_30_sp2),_mm256_maddubs_epi16(rhs_mat_0145_31_sp2, lhs_mat_23_31_sp2)); + __m256i iacc_mat_11_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp2, lhs_mat_23_30_sp2),_mm256_maddubs_epi16(rhs_mat_2367_31_sp2, lhs_mat_23_31_sp2)); + + __m256i iacc_mat_00_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp2, lhs_mat_01_40_sp2),_mm256_maddubs_epi16(rhs_mat_0145_41_sp2, lhs_mat_01_41_sp2)); + __m256i iacc_mat_01_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp2, lhs_mat_01_40_sp2),_mm256_maddubs_epi16(rhs_mat_2367_41_sp2, lhs_mat_01_41_sp2)); + + __m256i iacc_mat_10_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp2, lhs_mat_23_40_sp2),_mm256_maddubs_epi16(rhs_mat_0145_41_sp2, lhs_mat_23_41_sp2)); + __m256i iacc_mat_11_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp2, lhs_mat_23_40_sp2),_mm256_maddubs_epi16(rhs_mat_2367_41_sp2, lhs_mat_23_41_sp2)); + + __m256i iacc_mat_00_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp2, lhs_mat_01_50_sp2),_mm256_maddubs_epi16(rhs_mat_0145_51_sp2, lhs_mat_01_51_sp2)); + __m256i iacc_mat_01_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp2, lhs_mat_01_50_sp2),_mm256_maddubs_epi16(rhs_mat_2367_51_sp2, lhs_mat_01_51_sp2)); + + __m256i iacc_mat_10_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp2, lhs_mat_23_50_sp2),_mm256_maddubs_epi16(rhs_mat_0145_51_sp2, lhs_mat_23_51_sp2)); + __m256i iacc_mat_11_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp2, lhs_mat_23_50_sp2),_mm256_maddubs_epi16(rhs_mat_2367_51_sp2, lhs_mat_23_51_sp2)); + + __m256i iacc_mat_00_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp2, lhs_mat_01_60_sp2),_mm256_maddubs_epi16(rhs_mat_0145_61_sp2, lhs_mat_01_61_sp2)); + __m256i iacc_mat_01_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp2, lhs_mat_01_60_sp2),_mm256_maddubs_epi16(rhs_mat_2367_61_sp2, lhs_mat_01_61_sp2)); + + __m256i iacc_mat_10_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp2, lhs_mat_23_60_sp2),_mm256_maddubs_epi16(rhs_mat_0145_61_sp2, lhs_mat_23_61_sp2)); + __m256i iacc_mat_11_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp2, lhs_mat_23_60_sp2),_mm256_maddubs_epi16(rhs_mat_2367_61_sp2, lhs_mat_23_61_sp2)); + + __m256i iacc_mat_00_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp2, lhs_mat_01_70_sp2),_mm256_maddubs_epi16(rhs_mat_0145_71_sp2, lhs_mat_01_71_sp2)); + __m256i iacc_mat_01_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp2, lhs_mat_01_70_sp2),_mm256_maddubs_epi16(rhs_mat_2367_71_sp2, lhs_mat_01_71_sp2)); + + __m256i iacc_mat_10_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp2, lhs_mat_23_70_sp2),_mm256_maddubs_epi16(rhs_mat_0145_71_sp2, lhs_mat_23_71_sp2)); + __m256i iacc_mat_11_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp2, lhs_mat_23_70_sp2),_mm256_maddubs_epi16(rhs_mat_2367_71_sp2, lhs_mat_23_71_sp2)); + + // Combine results from both shuffle patterns for each output block. + __m256i iacc_mat_00_0 = _mm256_add_epi16(iacc_mat_00_0_sp1, iacc_mat_00_0_sp2); + __m256i iacc_mat_01_0 = _mm256_add_epi16(iacc_mat_01_0_sp1, iacc_mat_01_0_sp2); + __m256i iacc_mat_10_0 = _mm256_add_epi16(iacc_mat_10_0_sp1, iacc_mat_10_0_sp2); + __m256i iacc_mat_11_0 = _mm256_add_epi16(iacc_mat_11_0_sp1, iacc_mat_11_0_sp2); + + __m256i iacc_mat_00_1 = _mm256_add_epi16(iacc_mat_00_1_sp1, iacc_mat_00_1_sp2); + __m256i iacc_mat_01_1 = _mm256_add_epi16(iacc_mat_01_1_sp1, iacc_mat_01_1_sp2); + __m256i iacc_mat_10_1 = _mm256_add_epi16(iacc_mat_10_1_sp1, iacc_mat_10_1_sp2); + __m256i iacc_mat_11_1 = _mm256_add_epi16(iacc_mat_11_1_sp1, iacc_mat_11_1_sp2); + + __m256i iacc_mat_00_2 = _mm256_add_epi16(iacc_mat_00_2_sp1, iacc_mat_00_2_sp2); + __m256i iacc_mat_01_2 = _mm256_add_epi16(iacc_mat_01_2_sp1, iacc_mat_01_2_sp2); + __m256i iacc_mat_10_2 = _mm256_add_epi16(iacc_mat_10_2_sp1, iacc_mat_10_2_sp2); + __m256i iacc_mat_11_2 = _mm256_add_epi16(iacc_mat_11_2_sp1, iacc_mat_11_2_sp2); + + __m256i iacc_mat_00_3 = _mm256_add_epi16(iacc_mat_00_3_sp1, iacc_mat_00_3_sp2); + __m256i iacc_mat_01_3 = _mm256_add_epi16(iacc_mat_01_3_sp1, iacc_mat_01_3_sp2); + __m256i iacc_mat_10_3 = _mm256_add_epi16(iacc_mat_10_3_sp1, iacc_mat_10_3_sp2); + __m256i iacc_mat_11_3 = _mm256_add_epi16(iacc_mat_11_3_sp1, iacc_mat_11_3_sp2); + + __m256i iacc_mat_00_4 = _mm256_add_epi16(iacc_mat_00_4_sp1, iacc_mat_00_4_sp2); + __m256i iacc_mat_01_4 = _mm256_add_epi16(iacc_mat_01_4_sp1, iacc_mat_01_4_sp2); + __m256i iacc_mat_10_4 = _mm256_add_epi16(iacc_mat_10_4_sp1, iacc_mat_10_4_sp2); + __m256i iacc_mat_11_4 = _mm256_add_epi16(iacc_mat_11_4_sp1, iacc_mat_11_4_sp2); + + __m256i iacc_mat_00_5 = _mm256_add_epi16(iacc_mat_00_5_sp1, iacc_mat_00_5_sp2); + __m256i iacc_mat_01_5 = _mm256_add_epi16(iacc_mat_01_5_sp1, iacc_mat_01_5_sp2); + __m256i iacc_mat_10_5 = _mm256_add_epi16(iacc_mat_10_5_sp1, iacc_mat_10_5_sp2); + __m256i iacc_mat_11_5 = _mm256_add_epi16(iacc_mat_11_5_sp1, iacc_mat_11_5_sp2); + + __m256i iacc_mat_00_6 = _mm256_add_epi16(iacc_mat_00_6_sp1, iacc_mat_00_6_sp2); + __m256i iacc_mat_01_6 = _mm256_add_epi16(iacc_mat_01_6_sp1, iacc_mat_01_6_sp2); + __m256i iacc_mat_10_6 = _mm256_add_epi16(iacc_mat_10_6_sp1, iacc_mat_10_6_sp2); + __m256i iacc_mat_11_6 = _mm256_add_epi16(iacc_mat_11_6_sp1, iacc_mat_11_6_sp2); + + __m256i iacc_mat_00_7 = _mm256_add_epi16(iacc_mat_00_7_sp1, iacc_mat_00_7_sp2); + __m256i iacc_mat_01_7 = _mm256_add_epi16(iacc_mat_01_7_sp1, iacc_mat_01_7_sp2); + __m256i iacc_mat_10_7 = _mm256_add_epi16(iacc_mat_10_7_sp1, iacc_mat_10_7_sp2); + __m256i iacc_mat_11_7 = _mm256_add_epi16(iacc_mat_11_7_sp1, iacc_mat_11_7_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + iacc_mat_00_0 = _mm256_madd_epi16(iacc_mat_00_0, scale_0145_0); + iacc_mat_01_0 = _mm256_madd_epi16(iacc_mat_01_0, scale_2367_0); + iacc_mat_10_0 = _mm256_madd_epi16(iacc_mat_10_0, scale_0145_0); + iacc_mat_11_0 = _mm256_madd_epi16(iacc_mat_11_0, scale_2367_0); + + iacc_mat_00_1 = _mm256_madd_epi16(iacc_mat_00_1, scale_0145_1); + iacc_mat_01_1 = _mm256_madd_epi16(iacc_mat_01_1, scale_2367_1); + iacc_mat_10_1 = _mm256_madd_epi16(iacc_mat_10_1, scale_0145_1); + iacc_mat_11_1 = _mm256_madd_epi16(iacc_mat_11_1, scale_2367_1); + + iacc_mat_00_2 = _mm256_madd_epi16(iacc_mat_00_2, scale_0145_2); + iacc_mat_01_2 = _mm256_madd_epi16(iacc_mat_01_2, scale_2367_2); + iacc_mat_10_2 = _mm256_madd_epi16(iacc_mat_10_2, scale_0145_2); + iacc_mat_11_2 = _mm256_madd_epi16(iacc_mat_11_2, scale_2367_2); + + iacc_mat_00_3 = _mm256_madd_epi16(iacc_mat_00_3, scale_0145_3); + iacc_mat_01_3 = _mm256_madd_epi16(iacc_mat_01_3, scale_2367_3); + iacc_mat_10_3 = _mm256_madd_epi16(iacc_mat_10_3, scale_0145_3); + iacc_mat_11_3 = _mm256_madd_epi16(iacc_mat_11_3, scale_2367_3); + + iacc_mat_00_4 = _mm256_madd_epi16(iacc_mat_00_4, scale_0145_4); + iacc_mat_01_4 = _mm256_madd_epi16(iacc_mat_01_4, scale_2367_4); + iacc_mat_10_4 = _mm256_madd_epi16(iacc_mat_10_4, scale_0145_4); + iacc_mat_11_4 = _mm256_madd_epi16(iacc_mat_11_4, scale_2367_4); + + iacc_mat_00_5 = _mm256_madd_epi16(iacc_mat_00_5, scale_0145_5); + iacc_mat_01_5 = _mm256_madd_epi16(iacc_mat_01_5, scale_2367_5); + iacc_mat_10_5 = _mm256_madd_epi16(iacc_mat_10_5, scale_0145_5); + iacc_mat_11_5 = _mm256_madd_epi16(iacc_mat_11_5, scale_2367_5); + + iacc_mat_00_6 = _mm256_madd_epi16(iacc_mat_00_6, scale_0145_6); + iacc_mat_01_6 = _mm256_madd_epi16(iacc_mat_01_6, scale_2367_6); + iacc_mat_10_6 = _mm256_madd_epi16(iacc_mat_10_6, scale_0145_6); + iacc_mat_11_6 = _mm256_madd_epi16(iacc_mat_11_6, scale_2367_6); + + iacc_mat_00_7 = _mm256_madd_epi16(iacc_mat_00_7, scale_0145_7); + iacc_mat_01_7 = _mm256_madd_epi16(iacc_mat_01_7, scale_2367_7); + iacc_mat_10_7 = _mm256_madd_epi16(iacc_mat_10_7, scale_0145_7); + iacc_mat_11_7 = _mm256_madd_epi16(iacc_mat_11_7, scale_2367_7); + + __m256i iacc_mat_00 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_00_0, iacc_mat_00_1), _mm256_add_epi32(iacc_mat_00_2, iacc_mat_00_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_00_4, iacc_mat_00_5), _mm256_add_epi32(iacc_mat_00_6, iacc_mat_00_7))); + __m256i iacc_mat_01 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_01_0, iacc_mat_01_1), _mm256_add_epi32(iacc_mat_01_2, iacc_mat_01_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_01_4, iacc_mat_01_5), _mm256_add_epi32(iacc_mat_01_6, iacc_mat_01_7))); + __m256i iacc_mat_10 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_10_0, iacc_mat_10_1), _mm256_add_epi32(iacc_mat_10_2, iacc_mat_10_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_10_4, iacc_mat_10_5), _mm256_add_epi32(iacc_mat_10_6, iacc_mat_10_7))); + __m256i iacc_mat_11 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_11_0, iacc_mat_11_1), _mm256_add_epi32(iacc_mat_11_2, iacc_mat_11_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_11_4, iacc_mat_11_5), _mm256_add_epi32(iacc_mat_11_6, iacc_mat_11_7))); + + // Straighten out to make 4 row vectors + __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); + __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); + __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); + __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); + + // Load the scale(d) values for all the 4 Q8_k blocks and repeat it across lanes + const __m128 row_scale_f32_sse = _mm_load_ps(a_ptr[b].d); + const __m256 row_scale_f32 = _mm256_set_m128(row_scale_f32_sse, row_scale_f32_sse); + + // Multiply with appropiate scales and accumulate (for both d and dmin) below + acc_rows[0] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); + acc_rows[1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); + acc_rows[2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); + acc_rows[3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); + + __m256i lhs_bsums_01_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_0123), lhs_raw_bsums_01_0123, 1); + __m256i lhs_bsums_23_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_0123), lhs_raw_bsums_23_0123, 1); + __m256i lhs_bsums_01_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_4567), lhs_raw_bsums_01_4567, 1); + __m256i lhs_bsums_23_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_4567), lhs_raw_bsums_23_4567, 1); + + // Take two bsums from two Q8_Ks at a time and multiply with corresponding mins values from each Q2_K + __m256i iacc_row_min_0_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 0), mins_01); + __m256i iacc_row_min_1_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 170), mins_01); + __m256i iacc_row_min_2_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 0), mins_01); + __m256i iacc_row_min_3_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 170), mins_01); + + __m256i iacc_row_min_0_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 85), mins_23); + __m256i iacc_row_min_1_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 255), mins_23); + __m256i iacc_row_min_2_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 85), mins_23); + __m256i iacc_row_min_3_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 255), mins_23); + + __m256i iacc_row_min_0_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 0), mins_45); + __m256i iacc_row_min_1_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 170), mins_45); + __m256i iacc_row_min_2_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 0), mins_45); + __m256i iacc_row_min_3_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 170), mins_45); + + __m256i iacc_row_min_0_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 85), mins_67); + __m256i iacc_row_min_1_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 255), mins_67); + __m256i iacc_row_min_2_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 85), mins_67); + __m256i iacc_row_min_3_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 255), mins_67); + + __m256i iacc_row_min_0 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_0_01, iacc_row_min_0_23), _mm256_add_epi32(iacc_row_min_0_45,iacc_row_min_0_67)); + __m256i iacc_row_min_1 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_1_01, iacc_row_min_1_23), _mm256_add_epi32(iacc_row_min_1_45,iacc_row_min_1_67)); + __m256i iacc_row_min_2 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_2_01, iacc_row_min_2_23), _mm256_add_epi32(iacc_row_min_2_45,iacc_row_min_2_67)); + __m256i iacc_row_min_3 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_3_01, iacc_row_min_3_23), _mm256_add_epi32(iacc_row_min_3_45,iacc_row_min_3_67)); + + acc_min_rows[0] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_0), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_min_rows[0]); + acc_min_rows[1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_1), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_min_rows[1]); + acc_min_rows[2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_2), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_min_rows[2]); + acc_min_rows[3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_3), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_min_rows[3]); + } + } + // Store the accumulated values + for (int i = 0; i < 4; i++) { + _mm256_storeu_ps((float * )(s + ((y * 4 + i) * bs + x * 8)), _mm256_sub_ps(acc_rows[i], acc_min_rows[i])); + } + } + } +#else + + ggml_gemm_q2_K_8x8_q8_K_generic(n, s, bs, vx, vy, nr, nc); + + #endif } diff --git a/ggml/src/ggml-cpu/ggml-cpu.c b/ggml/src/ggml-cpu/ggml-cpu.c index c5271b7757..f6bea3df34 100644 --- a/ggml/src/ggml-cpu/ggml-cpu.c +++ b/ggml/src/ggml-cpu/ggml-cpu.c @@ -253,6 +253,12 @@ static const struct ggml_type_traits_cpu type_traits_cpu[GGML_TYPE_COUNT] = { .vec_dot_type = GGML_TYPE_Q8_1, .nrows = 1, }, + [GGML_TYPE_MXFP4] = { + .from_float = quantize_row_mxfp4, + .vec_dot = ggml_vec_dot_mxfp4_q8_0, + .vec_dot_type = GGML_TYPE_Q8_0, + .nrows = 1, + }, [GGML_TYPE_Q2_K] = { .from_float = quantize_row_q2_K, .vec_dot = ggml_vec_dot_q2_K_q8_K, @@ -1670,6 +1676,10 @@ static void ggml_compute_forward(struct ggml_compute_params * params, struct ggm { ggml_compute_forward_add(params, tensor); } break; + case GGML_OP_ADD_ID: + { + ggml_compute_forward_add_id(params, tensor); + } break; case GGML_OP_ADD1: { ggml_compute_forward_add1(params, tensor); @@ -1924,7 +1934,7 @@ static void ggml_compute_forward(struct ggml_compute_params * params, struct ggm } break; case GGML_OP_FLASH_ATTN_EXT: { - ggml_compute_forward_flash_attn_ext(params, tensor->src[0], tensor->src[1], tensor->src[2], tensor->src[3], tensor); + ggml_compute_forward_flash_attn_ext(params, tensor); } break; case GGML_OP_FLASH_ATTN_BACK: { @@ -2012,6 +2022,11 @@ static void ggml_compute_forward(struct ggml_compute_params * params, struct ggm ggml_compute_forward_opt_step_adamw(params, tensor); } break; + case GGML_OP_OPT_STEP_SGD: + { + ggml_compute_forward_opt_step_sgd(params, tensor); + } + break; case GGML_OP_NONE: { // nop @@ -2111,6 +2126,7 @@ static int ggml_get_n_tasks(struct ggml_tensor * node, int n_threads) { case GGML_OP_DUP: case GGML_OP_CONT: case GGML_OP_ADD: + case GGML_OP_ADD_ID: case GGML_OP_ADD1: case GGML_OP_ACC: { @@ -2172,6 +2188,7 @@ static int ggml_get_n_tasks(struct ggml_tensor * node, int n_threads) { case GGML_GLU_OP_REGLU: case GGML_GLU_OP_GEGLU: case GGML_GLU_OP_SWIGLU: + case GGML_GLU_OP_SWIGLU_OAI: case GGML_GLU_OP_GEGLU_ERF: case GGML_GLU_OP_GEGLU_QUICK: { @@ -2313,6 +2330,7 @@ static int ggml_get_n_tasks(struct ggml_tensor * node, int n_threads) { case GGML_OP_CROSS_ENTROPY_LOSS: case GGML_OP_CROSS_ENTROPY_LOSS_BACK: case GGML_OP_OPT_STEP_ADAMW: + case GGML_OP_OPT_STEP_SGD: { n_tasks = n_threads; } break; @@ -2673,6 +2691,7 @@ struct ggml_cplan ggml_graph_plan( } } break; case GGML_OP_ADD: + case GGML_OP_ADD_ID: case GGML_OP_ADD1: { if (ggml_is_quantized(node->src[0]->type)) { diff --git a/ggml/src/ggml-cpu/ggml-cpu.cpp b/ggml/src/ggml-cpu/ggml-cpu.cpp index c9daa4c39e..8dacd36714 100644 --- a/ggml/src/ggml-cpu/ggml-cpu.cpp +++ b/ggml/src/ggml-cpu/ggml-cpu.cpp @@ -35,7 +35,7 @@ // ggml-backend interface -std::vector& ggml_backend_cpu_get_extra_buffers_type() { +std::vector & ggml_backend_cpu_get_extra_buffer_types() { static std::vector bufts = []() { std::vector bufts; @@ -57,8 +57,6 @@ std::vector& ggml_backend_cpu_get_extra_buffers_type } #endif - bufts.push_back(NULL); - return bufts; }(); @@ -66,14 +64,20 @@ std::vector& ggml_backend_cpu_get_extra_buffers_type } static ggml_backend_buffer_type_t * ggml_backend_cpu_device_get_extra_buffers_type(ggml_backend_dev_t device) { - return ggml_backend_cpu_get_extra_buffers_type().data(); + static std::vector extra_bufts = [] { + std::vector bufts = ggml_backend_cpu_get_extra_buffer_types(); + bufts.push_back(nullptr); + return bufts; + }(); + + return extra_bufts.data(); GGML_UNUSED(device); } static bool ggml_backend_cpu_is_extra_buffer_type(ggml_backend_buffer_type_t buft) { - for (auto * extra : ggml_backend_cpu_get_extra_buffers_type()) { - if (extra && extra == buft) { + for (auto * extra : ggml_backend_cpu_get_extra_buffer_types()) { + if (extra == buft) { return true; } } @@ -210,10 +214,10 @@ ggml_backend_t ggml_backend_cpu_init(void) { ctx->abort_callback_data = NULL; ggml_backend_t cpu_backend = new ggml_backend { - /* .guid = */ ggml_backend_cpu_guid(), - /* .interface = */ ggml_backend_cpu_i, - /* .device = */ ggml_backend_reg_dev_get(ggml_backend_cpu_reg(), 0), - /* .context = */ ctx, + /* .guid = */ ggml_backend_cpu_guid(), + /* .iface = */ ggml_backend_cpu_i, + /* .device = */ ggml_backend_reg_dev_get(ggml_backend_cpu_reg(), 0), + /* .context = */ ctx, }; if (cpu_backend == NULL) { @@ -397,20 +401,13 @@ static bool ggml_backend_cpu_device_supports_op(ggml_backend_dev_t dev, const st return true; } - // extra_buffer_op? - for (auto extra : ggml_backend_cpu_get_extra_buffers_type()) { - if (extra) { - auto buf_extra = (ggml::cpu::extra_buffer_type*) extra->context; - if (buf_extra && buf_extra->supports_op(dev, op)) { - return true; - } - } - } - - // the other case need host buffer. - for (int i = 0; i < GGML_MAX_SRC; i++) { - if (op->src[i] && op->src[i]->buffer && !ggml_backend_buft_is_host(op->src[i]->buffer->buft)) { - return false; + // check extra buffer types + // note: only the first sources are checked for extra buffer types to reduce overhead, increase if necessary + for (int i = 0; i < 4; i++) { + if (op->src[i] && op->src[i]->buffer && + ggml_backend_cpu_is_extra_buffer_type(op->src[i]->buffer->buft)) { + auto * buf_extra = (ggml::cpu::extra_buffer_type *) op->src[i]->buffer->buft->context; + return buf_extra->supports_op(dev, op); } } diff --git a/ggml/src/ggml-cpu/kleidiai/kernels.cpp b/ggml/src/ggml-cpu/kleidiai/kernels.cpp index 910fd0ee4e..ddd29d002d 100644 --- a/ggml/src/ggml-cpu/kleidiai/kernels.cpp +++ b/ggml/src/ggml-cpu/kleidiai/kernels.cpp @@ -22,9 +22,94 @@ #include "kai_common.h" +#include "simd-mappings.h" + #include "kernels.h" #define NELEMS(x) sizeof(x) / sizeof(*x) + +static const size_t INT4_PER_BYTE = 2; +static const size_t INT4_BITS = 4; +static const int Q4_0_ZERO_POINT = 8; +const size_t INT4_PER_UINT16 = 4; + +static void dequantize_row_qsi4c32pscalef16( + const void *packed_data, + int32_t row_idx, + int64_t nc, + float *out, + size_t nr_pack, + size_t packed_row_stride, + size_t kr, + size_t bl, + size_t num_bytes_multiplier +) { + size_t group_idx = row_idx / nr_pack; + size_t row_in_group = row_idx % nr_pack; + const uint8_t *packed_group = (const uint8_t *)packed_data + group_idx * packed_row_stride; + size_t num_blocks = nc / bl; + const uint8_t *block_ptr = packed_group; + + for (size_t b = 0; b < num_blocks; ++b) { + uint16_t scale_f16 = *((const uint16_t *)(block_ptr + row_in_group * num_bytes_multiplier)); + float scale = GGML_CPU_FP16_TO_FP32(scale_f16); + + const uint8_t *segment_ptr = block_ptr + nr_pack * num_bytes_multiplier; + size_t num_segments = bl / kr; + size_t num_bytes_per_segment = kr / INT4_PER_BYTE; + + for (size_t s = 0; s < num_segments; ++s) { + const uint8_t *seg_base = segment_ptr + s * nr_pack * num_bytes_per_segment; + const uint8_t *qbytes = seg_base + row_in_group * num_bytes_per_segment; + for (size_t k = 0; k < num_bytes_per_segment; ++k) { + uint8_t byte = qbytes[k] ^ 0x88; + int x0 = (byte & 0x0F) - Q4_0_ZERO_POINT; + int x1 = (byte >> INT4_BITS) - Q4_0_ZERO_POINT; + out[b * bl + s * num_bytes_per_segment + k] = x0 * scale; + out[b * bl + s * num_bytes_per_segment + k + bl/2] = x1 * scale; + } + } + block_ptr += nr_pack * num_bytes_multiplier + num_segments * nr_pack * num_bytes_per_segment; + } +} + +static void dequantize_row_qsi4c32ps1s0scalef16( + const void *packed_data, + int32_t row_idx, + int64_t k, + float *out, + size_t nr, + size_t packed_row_stride, + size_t kr, + size_t bl, + size_t num_bytes_multiplier +) { + const size_t num_blocks = k / bl; + const size_t bl4 = bl / INT4_PER_UINT16; + + size_t group_idx = row_idx / nr; + size_t row_in_group = row_idx % nr; + + const uint8_t *packed_group = (const uint8_t *)packed_data + group_idx * packed_row_stride; + const uint16_t *qdata = (const uint16_t *)packed_group; + const uint16_t *scales = (const uint16_t *)(packed_group + packed_row_stride - (nr * num_blocks * num_bytes_multiplier)); + + for (size_t block_idx = 0; block_idx < num_blocks; ++block_idx) { + uint16_t scale_f16 = scales[row_in_group + block_idx * nr]; + float scale = GGML_CPU_FP16_TO_FP32(scale_f16); + + for (size_t bl4_idx = 0; bl4_idx < bl4; ++bl4_idx) { + uint16_t q = qdata[(block_idx * bl4 + bl4_idx) * nr + row_in_group]; + + for (size_t qidx = 0; qidx < INT4_PER_UINT16; ++qidx) { + int v = ((q >> (qidx * 4)) & 0xF) - Q4_0_ZERO_POINT; + out[block_idx * bl + bl4_idx * INT4_BITS + qidx] = v * scale; + } + } + } + GGML_UNUSED(kr); +} + static ggml_kleidiai_kernels gemm_gemv_kernels[] = { #if defined(__ARM_FEATURE_SME) { @@ -63,8 +148,10 @@ static ggml_kleidiai_kernels gemm_gemv_kernels[] = { /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32_neon, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32ps1s0scalef16_qsu4c32s16s0_neon, - /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32ps1s0scalef16_qsu4c32s16s0_neon, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32ps1s0scalef16_qsu4c32s16s0_neon, + /* .packed_stride = */ kai_get_rhs_packed_stride_rhs_pack_nxk_qsi4c32ps1s0scalef16_qsu4c32s16s0_neon, + /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32ps1s0scalef16_qsu4c32s16s0_neon, + /* .to_float = */ dequantize_row_qsi4c32ps1s0scalef16, }, /* .required_cpu = */ CPU_FEATURE_SME, /* .lhs_type = */ GGML_TYPE_F32, @@ -107,8 +194,10 @@ static ggml_kleidiai_kernels gemm_gemv_kernels[] = { /* .pack_func = */ kai_run_lhs_pack_bf16p2vlx2_f32_sme, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_kxn_bf16p2vlx2b_f32_x32_sme, - /* .pack_func = */ kai_run_rhs_pack_kxn_bf16p2vlx2b_f32_x32_sme, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_kxn_bf16p2vlx2b_f32_x32_sme, + /* .packed_stride = */ NULL, + /* .pack_func = */ kai_run_rhs_pack_kxn_bf16p2vlx2b_f32_x32_sme, + /* .to_float = */ NULL, }, /* .required_cpu = */ CPU_FEATURE_SME, /* .lhs_type = */ GGML_TYPE_F32, @@ -154,8 +243,10 @@ static ggml_kleidiai_kernels gemm_gemv_kernels[] = { /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, - /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_stride = */ kai_get_rhs_packed_stride_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .to_float = */ dequantize_row_qsi4c32pscalef16, }, /* .required_cpu = */ CPU_FEATURE_DOTPROD, /* .lhs_type = */ GGML_TYPE_F32, @@ -200,8 +291,10 @@ static ggml_kleidiai_kernels gemm_gemv_kernels[] = { /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, - /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_stride = */ kai_get_rhs_packed_stride_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .to_float = */ dequantize_row_qsi4c32pscalef16, }, /* .required_cpu = */ CPU_FEATURE_DOTPROD | CPU_FEATURE_I8MM, /* .lhs_type = */ GGML_TYPE_F32, @@ -247,8 +340,10 @@ static ggml_kleidiai_kernels gemm_gemv_kernels[] = { /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, - /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_stride = */ kai_get_rhs_packed_stride_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .to_float = */ dequantize_row_qsi4c32pscalef16, }, /* .required_cpu = */ CPU_FEATURE_DOTPROD | CPU_FEATURE_I8MM, /* .lhs_type = */ GGML_TYPE_F32, @@ -293,8 +388,10 @@ static ggml_kleidiai_kernels gemm_gemv_kernels[] = { /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, - /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_stride = */ kai_get_rhs_packed_stride_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .to_float = */ dequantize_row_qsi4c32pscalef16, }, /* .required_cpu = */ CPU_FEATURE_DOTPROD, /* .lhs_type = */ GGML_TYPE_F32, diff --git a/ggml/src/ggml-cpu/kleidiai/kernels.h b/ggml/src/ggml-cpu/kleidiai/kernels.h index 3b268d4a22..bc8f33405d 100644 --- a/ggml/src/ggml-cpu/kleidiai/kernels.h +++ b/ggml/src/ggml-cpu/kleidiai/kernels.h @@ -71,12 +71,15 @@ struct rhs_packing_info { std::function, std::function > packed_size; + size_t (*packed_stride)(size_t k, size_t nr, size_t kr, size_t bl); std::variant< std::function, std::function > pack_func; + void (*to_float)(const void *packed_data, int32_t row_idx, int64_t nc, float *out, size_t nr_pack, size_t packed_row_stride, + size_t kr, size_t bl, size_t num_bytes_multiplier); }; struct ggml_kleidiai_kernels { diff --git a/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp b/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp index fafe45e6c5..dff8fa244a 100644 --- a/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp +++ b/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp @@ -40,6 +40,17 @@ struct ggml_kleidiai_context { ggml_kleidiai_kernels * kernels; } static ctx = { CPU_FEATURE_NONE, NULL }; +static const char* cpu_feature_to_string(cpu_feature f) { + switch (f) { + case CPU_FEATURE_NONE: return "NONE"; + case CPU_FEATURE_DOTPROD: return "DOTPROD"; + case CPU_FEATURE_I8MM: return "I8MM"; + case CPU_FEATURE_SVE: return "SVE"; + case CPU_FEATURE_SME: return "SME"; + default: return "UNKNOWN"; + } +} + static void init_kleidiai_context(void) { ggml_critical_section_start(); @@ -62,6 +73,11 @@ static void init_kleidiai_context(void) { ctx.features |= ggml_cpu_has_sme() ? CPU_FEATURE_SME : CPU_FEATURE_NONE; } ctx.kernels = ggml_kleidiai_select_kernels_q4_0(ctx.features); +#ifndef NDEBUG + if (ctx.kernels) { + GGML_LOG_DEBUG("kleidiai: using kernel with CPU feature %s\n", cpu_feature_to_string(ctx.kernels->required_cpu)); + } +#endif } ggml_critical_section_end(); } @@ -102,6 +118,9 @@ static void transpose_f32kxn_f16nxk(size_t n, size_t k, float * dst, const uint1 class tensor_traits : public ggml::cpu::tensor_traits { bool work_size(int /* n_threads */, const struct ggml_tensor * op, size_t & size) override { + if (op->op != GGML_OP_MUL_MAT) { + return false; + } ggml_kleidiai_kernels *kernels = ggml_kleidiai_select_kernels(ctx.features, op); GGML_ASSERT(kernels); kernel_info * kernel = op->src[1]->ne[1] == 1 ? &kernels->gemv : &kernels->gemm; @@ -135,6 +154,10 @@ class tensor_traits : public ggml::cpu::tensor_traits { } else if (dst->src[0]->type == GGML_TYPE_F16) { return compute_forward_kv_cache(params, dst); } + } else if (dst->op == GGML_OP_GET_ROWS) { + if (dst->src[0]->type == GGML_TYPE_Q4_0) { + return compute_forward_get_rows(params, dst); + } } return false; } @@ -236,7 +259,10 @@ class tensor_traits : public ggml::cpu::tensor_traits { const int64_t m_start = 0; const int64_t n_step = static_cast(kernel->get_n_step()); - const int64_t num_threads = KAI_MIN(n / n_step, nth); + int64_t num_threads = KAI_MIN(n / n_step, nth); + if (num_threads <= 0) { + num_threads = 1; + } if (ith < num_threads) { const int64_t num_n_per_thread0 = round_down(n / num_threads, n_step); @@ -270,6 +296,8 @@ class tensor_traits : public ggml::cpu::tensor_traits { } bool compute_forward_q4_0(struct ggml_compute_params * params, struct ggml_tensor * dst) { + GGML_ASSERT(dst->src[0]->type == GGML_TYPE_Q4_0); + const ggml_tensor * src0 = dst->src[0]; const ggml_tensor * src1 = dst->src[1]; @@ -284,7 +312,8 @@ class tensor_traits : public ggml::cpu::tensor_traits { GGML_ASSERT(kernel); const int ith = params->ith; - const int nth = params->nth; + const int nth_raw = params->nth; + const int nth = nth_raw > 0 ? nth_raw : 1; const size_t k = ne00; const size_t m = ne11; @@ -302,9 +331,12 @@ class tensor_traits : public ggml::cpu::tensor_traits { const size_t num_n_per_thread = kai_roundup(kai_roundup(n, nth) / nth, n_step); const size_t n_start = ith * num_n_per_thread; - size_t n_to_process = num_n_per_thread; - if ((n_start + n_to_process) > n) { - n_to_process = n - n_start; + size_t n_to_process = 0; + if (n_start < n) { + n_to_process = num_n_per_thread; + if ((n_start + n_to_process) > n) { + n_to_process = n - n_start; + } } // Calculate number of columns to be processed per thread @@ -336,14 +368,57 @@ class tensor_traits : public ggml::cpu::tensor_traits { const void* lhs_ptr = (const void*)((const char *)lhs_packed + lhs_packed_offset); float *dst_ptr = reinterpret_cast(static_cast(dst->data) + dst_offset); - variant_call(kernel->run_kernel, m, n_to_process, k, QK4_0, lhs_ptr, rhs_ptr, dst_ptr, dst_stride, - sizeof(float), -FLT_MAX, FLT_MAX); + if (n_to_process > 0) { + variant_call(kernel->run_kernel, m, n_to_process, k, QK4_0, lhs_ptr, rhs_ptr, dst_ptr, dst_stride, + sizeof(float), -FLT_MAX, FLT_MAX); + } + + return true; + } + + bool compute_forward_get_rows(struct ggml_compute_params * params, struct ggml_tensor * dst) { + GGML_ASSERT(dst->src[0]->type == GGML_TYPE_Q4_0); + GGML_ASSERT(ctx.kernels); + + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + + GGML_TENSOR_BINARY_OP_LOCALS + + rhs_packing_info * rhs_info = &ctx.kernels->rhs_info; + kernel_info * kernel = &ctx.kernels->gemm; + + const int64_t nc = ne00; + const int64_t nr = ggml_nelements(src1); + + const size_t block_rows = kernel->get_nr(); + const size_t kr = kernel->get_kr(); + + const size_t num_bytes_multiplier = sizeof(uint16_t); + const size_t packed_stride = rhs_info->packed_stride(nc, block_rows, kr, QK4_0); + + const int ith = params->ith; + const int nth = params->nth; + + const int dr = (nr + nth - 1) / nth; + const int ir0 = dr * ith; + const int ir1 = MIN(ir0 + dr, nr); + + for (int64_t i = ir0; i < ir1; ++i) { + GGML_ASSERT(src1->type == GGML_TYPE_I32); + int64_t row_idx = ((const int32_t *)src1->data)[i]; + GGML_ASSERT(row_idx >= 0 && row_idx < src0->ne[1]); + + float *out = (float *)((char *)dst->data + i * nb1); + rhs_info->to_float(src0->data, row_idx, nc, out, block_rows, packed_stride, kr, QK4_0, num_bytes_multiplier); + } return true; } public: int repack(struct ggml_tensor * tensor, const void * data, size_t data_size) { + GGML_ASSERT(tensor->type == GGML_TYPE_Q4_0); GGML_ASSERT(ctx.kernels); const size_t n = tensor->ne[1]; const size_t k = tensor->ne[0]; @@ -351,17 +426,12 @@ public: size_t kr = ctx.kernels->gemm.get_kr(); size_t sr = ctx.kernels->gemm.get_sr(); -#ifndef NDEBUG - const size_t repacked_size = variant_call(ctx.kernels->rhs_info.packed_size, n, k, nr, kr, QK4_0); - GGML_ASSERT(repacked_size <= data_size && "repacked size larger than the packed size!"); -#endif struct kai_rhs_pack_qs4cxs1s0_param params; params.lhs_zero_point = 1; params.rhs_zero_point = 8; variant_call(ctx.kernels->rhs_info.pack_func, 1, n, k, nr, kr, sr, QK4_0, (const uint8_t*)data, nullptr, tensor->data, 0, ¶ms); return 0; - GGML_UNUSED(data_size); } }; @@ -375,8 +445,8 @@ static ggml::cpu::tensor_traits * get_tensor_traits(ggml_backend_buffer_t, struc static enum ggml_status ggml_backend_cpu_kleidiai_buffer_init_tensor(ggml_backend_buffer_t buffer, struct ggml_tensor * tensor) { tensor->extra = (void *) ggml::cpu::kleidiai::get_tensor_traits(buffer, tensor); - GGML_UNUSED(buffer); return GGML_STATUS_SUCCESS; + GGML_UNUSED(buffer); } static void ggml_backend_cpu_kleidiai_buffer_set_tensor(ggml_backend_buffer_t buffer, struct ggml_tensor * tensor, @@ -418,18 +488,35 @@ static size_t ggml_backend_cpu_kleidiai_buffer_type_get_alignment(ggml_backend_b GGML_UNUSED(buft); } +static size_t ggml_backend_cpu_kleidiai_buffer_type_get_alloc_size(ggml_backend_buffer_type_t buft, const struct ggml_tensor * tensor) { + GGML_ASSERT(tensor->type == GGML_TYPE_Q4_0); + GGML_ASSERT(ctx.kernels); + + const size_t n = tensor->ne[1]; + const size_t k = tensor->ne[0]; + const size_t nr = ctx.kernels->gemm.get_nr(); + const size_t kr = ctx.kernels->gemm.get_kr(); + + return variant_call(ctx.kernels->rhs_info.packed_size, n, k, nr, kr, QK4_0); + + GGML_UNUSED(buft); +} + namespace ggml::cpu::kleidiai { class extra_buffer_type : ggml::cpu::extra_buffer_type { bool supports_op(ggml_backend_dev_t, const struct ggml_tensor * op) override { - if (op->op == GGML_OP_MUL_MAT && + if ((op->op == GGML_OP_MUL_MAT || op->op == GGML_OP_GET_ROWS) && op->src[0]->type == GGML_TYPE_Q4_0 && op->src[0]->buffer && (ggml_n_dims(op->src[0]) == 2) && op->src[0]->buffer->buft == ggml_backend_cpu_kleidiai_buffer_type() && ctx.kernels) { + if (op->op == GGML_OP_GET_ROWS && op->src[1]->ne[0] != 8) { + return false; + } if (op->src[1]->buffer && !ggml_backend_buft_is_host(op->src[1]->buffer->buft)) { return false; } - if (op->src[1]->type == GGML_TYPE_F32 && + if ((op->src[1]->type == GGML_TYPE_F32 || op->src[1]->type == GGML_TYPE_I32) && ggml_ne(op->src[1], 2) == 1 && ggml_ne(op->src[1], 3) == 1) { return true; } @@ -438,7 +525,7 @@ class extra_buffer_type : ggml::cpu::extra_buffer_type { } ggml::cpu::tensor_traits * get_tensor_traits(const struct ggml_tensor * op) override { - if (op->op == GGML_OP_MUL_MAT) { + if (op->op == GGML_OP_MUL_MAT || op->op == GGML_OP_GET_ROWS) { if (op->src[0]->buffer && op->src[0]->buffer->buft == ggml_backend_cpu_kleidiai_buffer_type()) { return (ggml::cpu::tensor_traits *) op->src[0]->extra; } @@ -469,7 +556,7 @@ ggml_backend_buffer_type_t ggml_backend_cpu_kleidiai_buffer_type(void) { /* .alloc_buffer = */ ggml_backend_cpu_kleidiai_buffer_type_alloc_buffer, /* .get_alignment = */ ggml_backend_cpu_kleidiai_buffer_type_get_alignment, /* .get_max_size = */ nullptr, // defaults to SIZE_MAX - /* .get_alloc_size = */ nullptr, // defaults to ggml_nbytes + /* .get_alloc_size = */ ggml_backend_cpu_kleidiai_buffer_type_get_alloc_size, /* .is_host = */ nullptr, }, /* .device = */ ggml_backend_reg_dev_get(ggml_backend_cpu_reg(), 0), diff --git a/ggml/src/ggml-cpu/ops.cpp b/ggml/src/ggml-cpu/ops.cpp index 6581d27add..b72a2556a5 100644 --- a/ggml/src/ggml-cpu/ops.cpp +++ b/ggml/src/ggml-cpu/ops.cpp @@ -8,6 +8,7 @@ #include "vec.h" #include +#include // ggml_compute_forward_dup @@ -1283,6 +1284,7 @@ void ggml_compute_forward_add( case GGML_TYPE_Q5_0: case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -1309,6 +1311,77 @@ void ggml_compute_forward_add( } } +// ggml_compute_forward_add_id + +static void ggml_compute_forward_add_id_f32( + const ggml_compute_params * params, + ggml_tensor * dst) { + + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + const ggml_tensor * src2 = dst->src[2]; + + GGML_ASSERT(dst->type == GGML_TYPE_F32); + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT(src2->type == GGML_TYPE_I32); + + GGML_ASSERT(src0->nb[0] == sizeof(float)); + GGML_ASSERT(src1->nb[0] == sizeof(float)); + + const int ith = params->ith; + const int nth = params->nth; + + const int nr = ggml_nrows(src0); + + GGML_TENSOR_TERNARY_OP_LOCALS + + GGML_ASSERT( nb0 == sizeof(float)); + GGML_ASSERT(nb10 == sizeof(float)); + + // rows per thread + const int dr = (nr + nth - 1)/nth; + + // row range for this thread + const int ir0 = dr*ith; + const int ir1 = MIN(ir0 + dr, nr); + + for (int ir = ir0; ir < ir1; ++ir) { + // src0 indices + const int i3 = ir/(ne2*ne1); + const int i2 = (ir - i3*ne2*ne1)/ne1; + const int i1 = (ir - i3*ne2*ne1 - i2*ne1); + + // src1 indices + const int i11 = *(int32_t *) ((char *) src2->data + i1*nb20 + i2*nb21); + + GGML_ASSERT(i11 >= 0 && i11 < ne11); + + ggml_vec_add_f32(ne0, + (float *) ((char *) dst->data + i3*nb3 + i2*nb2 + i1*nb1 ), + (float *) ((char *) src0->data + i3*nb03 + i2*nb02 + i1*nb01), + (float *) ((char *) src1->data + i11*nb11)); + } +} + +void ggml_compute_forward_add_id( + const ggml_compute_params * params, + ggml_tensor * dst) { + + const ggml_tensor * src0 = dst->src[0]; + + switch (src0->type) { + case GGML_TYPE_F32: + { + ggml_compute_forward_add_id_f32(params, dst); + } break; + default: + { + GGML_ABORT("unsupported type for ggml_compute_forward_add_id: %s", ggml_type_name(src0->type)); + } + } +} + // ggml_compute_forward_add1 static void ggml_compute_forward_add1_f32( @@ -1660,6 +1733,7 @@ void ggml_compute_forward_add1( case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: case GGML_TYPE_Q8_1: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -1787,6 +1861,7 @@ void ggml_compute_forward_acc( case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: case GGML_TYPE_Q8_1: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -3614,6 +3689,93 @@ static void ggml_compute_forward_swiglu( } } +// ggml_compute_forward_swiglu_oai + +static void ggml_compute_forward_swiglu_oai_f32( + const ggml_compute_params * params, + ggml_tensor * dst) { + + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + char * src0_d = (char *) src0->data; + char * src1_d = (char *) (src1 ? src1->data : src0->data); + const size_t src0_o = src0->nb[1]; + const size_t src1_o = src1 ? src1->nb[1] : src0->nb[1]; + + GGML_ASSERT(ggml_is_contiguous_1(src0)); + GGML_ASSERT(ggml_is_contiguous_1(dst)); + + if (src1) { + GGML_ASSERT(ggml_is_contiguous_1(src1)); + GGML_ASSERT(src0->type == src1->type); + } + + const int ith = params->ith; + const int nth = params->nth; + + const int nc = src1 ? src0->ne[0] : src0->ne[0] / 2; + const int nr = ggml_nrows(src0); + + GGML_ASSERT(dst->ne[0] == nc); + GGML_ASSERT(ggml_nrows(dst) == nr); + + const int32_t swapped = ggml_get_op_params_i32(dst, 1); + const float alpha = ggml_get_op_params_f32(dst, 2); + const float limit = ggml_get_op_params_f32(dst, 3); + + // rows per thread + const int dr = (nr + nth - 1)/nth; + + // row range for this thread + const int ir0 = dr*ith; + const int ir1 = MIN(ir0 + dr, nr); + + for (int i1 = ir0; i1 < ir1; i1++) { + float * src0_p = (float *) (src0_d + i1*src0_o); + float * src1_p = (float *) (src1_d + i1*src1_o); + float * dst_p = (float *) ((char *) dst->data + i1*(dst->nb[1])); + + if (!src1) { + src0_p += swapped ? nc : 0; + src1_p += swapped ? 0 : nc; + } + + for (int k = 0; k < nc; k++) { + const float x = std::min(src0_p[k], limit); + const float y = std::clamp(src1_p[k], -limit, limit); + const float out_glu = x / (1.f + expf(alpha * (-x))); + dst_p[k] = out_glu * (y + 1.f); + } + +#ifndef NDEBUG + for (int k = 0; k < nc; k++) { + const float x = dst_p[k]; + GGML_UNUSED(x); + assert(!isnan(x)); + assert(!isinf(x)); + } +#endif + } +} + +static void ggml_compute_forward_swiglu_oai( + const ggml_compute_params * params, + ggml_tensor * dst) { + + const ggml_tensor * src0 = dst->src[0]; + + switch (src0->type) { + case GGML_TYPE_F32: + { + ggml_compute_forward_swiglu_oai_f32(params, dst); + } break; + default: + { + GGML_ABORT("fatal error"); + } + } +} + // ggml_compute_forward_geglu_erf static void ggml_compute_forward_geglu_erf_f32( @@ -4599,6 +4761,7 @@ void ggml_compute_forward_out_prod( case GGML_TYPE_Q5_0: case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -4873,6 +5036,7 @@ void ggml_compute_forward_set( case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: case GGML_TYPE_Q8_1: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -5134,6 +5298,7 @@ void ggml_compute_forward_get_rows( case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: case GGML_TYPE_Q8_1: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -5523,6 +5688,7 @@ static void ggml_compute_forward_soft_max_f32( const ggml_tensor * src0 = dst->src[0]; const ggml_tensor * src1 = dst->src[1]; + const ggml_tensor * src2 = dst->src[2]; assert(ggml_is_contiguous(dst)); assert(ggml_are_same_shape(src0, dst)); @@ -5557,6 +5723,9 @@ static void ggml_compute_forward_soft_max_f32( const bool use_f16 = (src1 && src1->type == GGML_TYPE_F16); + // sinks + const float * sk = src2 ? (float *)((char *) src2->data) : nullptr; + for (int64_t i03 = 0; i03 < ne03; i03++) { for (int64_t i02 = 0; i02 < ne02; i02++) { for (int64_t i01 = ith; i01 < ne01; i01 += nth) { @@ -5599,9 +5768,18 @@ static void ggml_compute_forward_soft_max_f32( float max = -INFINITY; ggml_vec_max_f32(ne00, &max, wp); + // if we have sinks, make a correction as if they were included in the softmax + if (sk) { + max = MAX(max, sk[i02]); + } + ggml_float sum = ggml_vec_soft_max_f32(ne00, dp, wp, max); assert(sum > 0.0); + if (sk) { + sum += (ggml_float) expf(sk[i02] - max); + } + sum = 1.0/sum; ggml_vec_scale_f32(ne00, dp, sum); @@ -5836,6 +6014,7 @@ void ggml_compute_forward_clamp( case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: case GGML_TYPE_Q8_1: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -7989,12 +8168,14 @@ void ggml_compute_forward_argsort( static void ggml_compute_forward_flash_attn_ext_f16( const ggml_compute_params * params, - const ggml_tensor * q, - const ggml_tensor * k, - const ggml_tensor * v, - const ggml_tensor * mask, ggml_tensor * dst) { + const ggml_tensor * q = dst->src[0]; + const ggml_tensor * k = dst->src[1]; + const ggml_tensor * v = dst->src[2]; + const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * sinks = dst->src[4]; + GGML_TENSOR_LOCALS(int64_t, neq, q, ne) GGML_TENSOR_LOCALS(size_t, nbq, q, nb) GGML_TENSOR_LOCALS(int64_t, nek, k, ne) @@ -8189,6 +8370,23 @@ static void ggml_compute_forward_flash_attn_ext_f16( } } + // sinks + if (sinks) { + const float s = ((float *)((char *) sinks->data))[h]; + + float ms = 1.0f; + float vs = 1.0f; + + if (s > M) { + ms = expf(M - s); + ggml_vec_scale_f32(DV, VKQ32, ms); + } else { + vs = expf(s - M); + } + + S = S*ms + vs; + } + // V /= S const float S_inv = 1.0f/S; ggml_vec_scale_f32(DV, VKQ32, S_inv); @@ -8208,17 +8406,13 @@ static void ggml_compute_forward_flash_attn_ext_f16( void ggml_compute_forward_flash_attn_ext( const ggml_compute_params * params, - const ggml_tensor * q, - const ggml_tensor * k, - const ggml_tensor * v, - const ggml_tensor * mask, ggml_tensor * dst) { switch (dst->op_params[3]) { case GGML_PREC_DEFAULT: case GGML_PREC_F32: { // uses F32 accumulators - ggml_compute_forward_flash_attn_ext_f16(params, q, k, v, mask, dst); + ggml_compute_forward_flash_attn_ext_f16(params, dst); } break; default: { @@ -9080,6 +9274,10 @@ void ggml_compute_forward_glu( { ggml_compute_forward_swiglu(params, dst); } break; + case GGML_GLU_OP_SWIGLU_OAI: + { + ggml_compute_forward_swiglu_oai(params, dst); + } break; case GGML_GLU_OP_GEGLU_ERF: { ggml_compute_forward_geglu_erf(params, dst); @@ -10132,6 +10330,7 @@ static void ggml_compute_forward_opt_step_adamw_f32( const int ir1 = MIN(ir0 + dr, nr); const float * adamw_params_ptr = ggml_get_data_f32(adamw_params); + const float alpha = adamw_params_ptr[0]; const float beta1 = adamw_params_ptr[1]; const float beta2 = adamw_params_ptr[2]; @@ -10139,7 +10338,7 @@ static void ggml_compute_forward_opt_step_adamw_f32( const float wd = adamw_params_ptr[4]; const float beta1h = adamw_params_ptr[5]; const float beta2h = adamw_params_ptr[6]; - + const float keep = 1.f - alpha * wd; for (int ir = ir0; ir < ir1; ++ir) { const int64_t i03 = ir/(ne02*ne01); const int64_t i02 = (ir - i03*ne02*ne01)/ne01; @@ -10162,7 +10361,7 @@ static void ggml_compute_forward_opt_step_adamw_f32( // The weight decay is applied independently of the Adam momenta m and v. // This is NOT equivalent to l2 regularization that adds w[i00]*w[i00] to the loss. // See: https://arxiv.org/pdf/1711.05101v3.pdf - w[i00] = w[i00]*(1.0f - alpha*wd) - alpha*mh/vh; + w[i00] = w[i00] * keep - alpha * mh / vh; } } } @@ -10184,3 +10383,63 @@ void ggml_compute_forward_opt_step_adamw( } } } + +static void ggml_compute_forward_opt_step_sgd_f32(const ggml_compute_params * params, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src0_grad = dst->src[1]; + const ggml_tensor * sgd_params = dst->src[2]; + + GGML_ASSERT(ggml_are_same_shape(src0, src0_grad)); + GGML_ASSERT(ggml_nelements(sgd_params) == 2); + + const int ith = params->ith; + const int nth = params->nth; + + const int nr = ggml_nrows(src0); + + GGML_TENSOR_UNARY_OP_LOCALS + GGML_ASSERT(nb00 == sizeof(float)); + + // rows per thread + const int dr = (nr + nth - 1) / nth; + + // row range for this thread + const int ir0 = dr * ith; + const int ir1 = MIN(ir0 + dr, nr); + + // using adamw param subset we care about - alpha, wd - could have a separate struct + const float * sgd_params_ptr = ggml_get_data_f32(sgd_params); + const float alpha = sgd_params_ptr[0]; + const float keep = 1.f - alpha * sgd_params_ptr[1]; + + for (int ir = ir0; ir < ir1; ++ir) { + const int64_t i03 = ir / (ne02 * ne01); + const int64_t i02 = (ir - i03 * ne02 * ne01) / ne01; + const int64_t i01 = (ir - i03 * ne02 * ne01 - i02 * ne01); + + const size_t offset = i03 * nb03 + i02 * nb02 + i01 * nb01; + + float * w = (float *) ((char *) src0->data + offset); // weight + const float * g = (const float *) ((const char *) src0_grad->data + offset); // grad + + for (int i00 = 0; i00 < ne00; ++i00) { + w[i00] = w[i00] * keep - alpha * g[i00]; + } + } +} + +void ggml_compute_forward_opt_step_sgd(const ggml_compute_params * params, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + + switch (src0->type) { + case GGML_TYPE_F32: + { + ggml_compute_forward_opt_step_sgd_f32(params, dst); + } + break; + default: + { + GGML_ABORT("fatal error - sgd is F32 only"); + } + } +} diff --git a/ggml/src/ggml-cpu/ops.h b/ggml/src/ggml-cpu/ops.h index 3a32ec20db..82ea79eaa5 100644 --- a/ggml/src/ggml-cpu/ops.h +++ b/ggml/src/ggml-cpu/ops.h @@ -29,6 +29,7 @@ extern "C" { void ggml_compute_forward_dup(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_add(const struct ggml_compute_params * params, struct ggml_tensor * dst); +void ggml_compute_forward_add_id(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_add1(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_acc(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_sum(const struct ggml_compute_params * params, struct ggml_tensor * dst); @@ -82,13 +83,7 @@ void ggml_compute_forward_arange(const struct ggml_compute_params * params, stru void ggml_compute_forward_timestep_embedding(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_argsort(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_leaky_relu(const struct ggml_compute_params * params, struct ggml_tensor * dst); -void ggml_compute_forward_flash_attn_ext( - const struct ggml_compute_params * params, - const struct ggml_tensor * q, - const struct ggml_tensor * k, - const struct ggml_tensor * v, - const struct ggml_tensor * mask, - struct ggml_tensor * dst); +void ggml_compute_forward_flash_attn_ext(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_flash_attn_back( const struct ggml_compute_params * params, const bool masked, @@ -112,7 +107,7 @@ void ggml_compute_forward_cross_entropy_loss(const struct ggml_compute_params * void ggml_compute_forward_cross_entropy_loss_back(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_opt_step_adamw(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_mul_mat(const struct ggml_compute_params * params, struct ggml_tensor * dst); - +void ggml_compute_forward_opt_step_sgd(const struct ggml_compute_params * params, struct ggml_tensor * dst); #ifdef __cplusplus } #endif diff --git a/ggml/src/ggml-cpu/quants.c b/ggml/src/ggml-cpu/quants.c index ee35ab42fd..365cb36d2d 100644 --- a/ggml/src/ggml-cpu/quants.c +++ b/ggml/src/ggml-cpu/quants.c @@ -46,6 +46,10 @@ void quantize_row_q8_1_generic(const float * GGML_RESTRICT x, void * GGML_RESTRI quantize_row_q8_1_ref(x, y, k); } +void quantize_row_mxfp4(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k) { + quantize_row_mxfp4_ref(x, y, k); +} + // // 2-6 bit quantization in super-blocks // @@ -181,6 +185,37 @@ void ggml_vec_dot_q4_1_q8_1_generic(int n, float * GGML_RESTRICT s, size_t bs, c *s = sumf; } +void ggml_vec_dot_mxfp4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { + assert(nrc == 1); + UNUSED(nrc); + UNUSED(bx); + UNUSED(by); + UNUSED(bs); + assert(n % QK_MXFP4 == 0); + static_assert(QK_MXFP4 == QK8_0, "QK_MXFP4 and QK8_0 must be the same"); + + const block_mxfp4 * GGML_RESTRICT x = vx; + const block_q8_0 * GGML_RESTRICT y = vy; + + const int nb = n / QK_MXFP4; + + int ib = 0; + float sumf = 0; + + for (; ib < nb; ++ib) { + const float d = GGML_CPU_FP16_TO_FP32(y[ib].d)*GGML_E8M0_TO_FP32_HALF(x[ib].e); + + int sumi1 = 0; + int sumi2 = 0; + for (int j = 0; j < QK_MXFP4/2; ++j) { + sumi1 += y[ib].qs[j + 0] * kvalues_mxfp4[x[ib].qs[j] & 0xf]; + sumi2 += y[ib].qs[j + QK_MXFP4/2] * kvalues_mxfp4[x[ib].qs[j] >> 4]; + } + sumf += d * (sumi1 + sumi2); + } + *s = sumf; +} + void ggml_vec_dot_q5_0_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { const int qk = QK8_0; const int nb = n / qk; diff --git a/ggml/src/ggml-cpu/quants.h b/ggml/src/ggml-cpu/quants.h index dc4342c87f..d83eb1b144 100644 --- a/ggml/src/ggml-cpu/quants.h +++ b/ggml/src/ggml-cpu/quants.h @@ -19,6 +19,8 @@ void quantize_row_q5_1(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, in void quantize_row_q8_0(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); void quantize_row_q8_1(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); +void quantize_row_mxfp4(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); + void quantize_row_q2_K(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); void quantize_row_q3_K(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); void quantize_row_q4_K(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); @@ -39,6 +41,8 @@ void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const voi void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); +void ggml_vec_dot_mxfp4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); + void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); @@ -67,8 +71,12 @@ void ggml_vec_dot_q4_1_q8_1_generic(int n, float * GGML_RESTRICT s, size_t bs, c void ggml_vec_dot_q5_0_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q5_1_q8_1_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q8_0_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); + +void ggml_vec_dot_mxfp4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); + void ggml_vec_dot_tq1_0_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_tq2_0_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); + void ggml_vec_dot_q2_K_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q3_K_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q4_K_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); diff --git a/ggml/src/ggml-cpu/repack.cpp b/ggml/src/ggml-cpu/repack.cpp index 72ee93a5ab..f531d21e23 100644 --- a/ggml/src/ggml-cpu/repack.cpp +++ b/ggml/src/ggml-cpu/repack.cpp @@ -14,7 +14,6 @@ #include #include #include -#include // for qsort #include // for GGML_ASSERT #include "repack.h" @@ -207,8 +206,9 @@ void ggml_gemv_q4_0_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const int ncols_interleaved = 4; const int blocklen = 4; - assert (n % qk == 0); - assert (nc % ncols_interleaved == 0); + assert(nr == 1); + assert(n % qk == 0); + assert(nc % ncols_interleaved == 0); UNUSED(s); UNUSED(bs); @@ -308,30 +308,28 @@ void ggml_gemv_q4_0_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, UNUSED(ncols_interleaved); UNUSED(blocklen); - { - float sumf[8]; - int sumi; + float sumf[8]; + int sumi; - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); + const block_q8_0 * a_ptr = (const block_q8_0 *) vy; + for (int x = 0; x < nc / ncols_interleaved; x++) { + const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); + for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (2 * blocklen)); k++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumi = 0; + for (int i = 0; i < blocklen; ++i) { + const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); + const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); + sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; } + sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); } } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; } + for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; } } @@ -413,11 +411,11 @@ void ggml_gemv_q4_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, } } -void ggml_gemv_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { - const int qk = QK8_0; +void ggml_gemv_q2_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK_K; const int nb = n / qk; - const int ncols_interleaved = 4; - const int blocklen = 4; + const int ncols_interleaved = 8; + const int blocklen = 8; assert (n % qk == 0); assert (nc % ncols_interleaved == 0); @@ -432,30 +430,136 @@ void ggml_gemv_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs UNUSED(ncols_interleaved); UNUSED(blocklen); - { - float sumf[4]; - int sumi; + float sumf[8]; + float sum_minf[8]; + int sumi1,sumi2,sumi3,sumi4; + int sumi; - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_iq4_nlx4 * b_ptr = (const block_iq4_nlx4 *) vx + (x * nb); + const block_q8_K * a_ptr = (const block_q8_K *)vy; + for(int x = 0; x < nc / ncols_interleaved; x++) { + const block_q2_Kx8 * b_ptr = (const block_q2_Kx8 *) vx + (x * nb); + for (int j = 0; j < ncols_interleaved; j++) { + sumf[j] = 0.0; + sum_minf[j] = 0.0; + } + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (4 * blocklen)); k++) { + const uint8_t *scales_0 = b_ptr[l].scales + (k / 4) * 64 ; + const uint8_t *scales_1 = b_ptr[l].scales + (k / 4) * 64 + 16; + const uint8_t *scales_2 = b_ptr[l].scales + (k / 4) * 64 + 32; + const uint8_t *scales_3 = b_ptr[l].scales + (k / 4) * 64 + 48; + for (int j = 0; j < ncols_interleaved; j++) { + sumi1 = 0; + sumi2 = 0; + sumi3 = 0; + sumi4 = 0; + sumi = 0; + int offset = ((k / 2) % 2) + j * 2; + for (int i = 0; i < blocklen; ++i){ + const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 3); + const int v1 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 2 ) & 3); + const int v2 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4 ) & 3); + const int v3 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 6 ) & 3); + sumi1 = (v0 * a_ptr[l].qs[(k >> 2) * 128 + (k % 4) * blocklen + i]); + sumi2 = (v1 * a_ptr[l].qs[(k >> 2) * 128 + (k % 4) * blocklen + i + 32]); + sumi3 = (v2 * a_ptr[l].qs[(k >> 2) * 128 + (k % 4) * blocklen + i + 64]); + sumi4 = (v3 * a_ptr[l].qs[(k >> 2) * 128 + (k % 4) * blocklen + i + 96]); - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; - const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])); - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); + sumi1 = sumi1 * (scales_0[offset] & 0xF); + sumi2 = sumi2 * (scales_1[offset] & 0xF); + sumi3 = sumi3 * (scales_2[offset] & 0xF); + sumi4 = sumi4 * (scales_3[offset] & 0xF); + sumi += sumi1 + sumi2 + sumi3 + sumi4; } + sumf[j] += sumi * GGML_FP16_TO_FP32(b_ptr[l].d[j]) * a_ptr[l].d; + } + } + for(int sb = 0; sb < 8; sb++) { + const uint8_t *mins = b_ptr[l].scales + sb * 16; + for(int j = 0; j < ncols_interleaved; j++){ + sum_minf[j] += ((mins[j * 2] >> 4) * a_ptr[l].bsums[sb * 2] + (mins[(j * 2)+ 1] >> 4) * a_ptr[l].bsums[sb * 2 + 1]) * GGML_FP16_TO_FP32(b_ptr[l].dmin[j]) * a_ptr[l].d; } } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; } + for (int j = 0; j < ncols_interleaved; j++) { + s[x * ncols_interleaved + j] = sumf[j] - sum_minf[j]; + } + } +} + +void ggml_gemv_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK8_0; + const int nb = n / qk; + const int ncols_interleaved = 4; + const int blocklen = 4; + + assert(nr == 1); + assert(n % qk == 0); + assert(nc % ncols_interleaved == 0); + + UNUSED(bs); + UNUSED(nr); + + float sumf[4]; + int sumi; + + const block_q8_0 * a_ptr = (const block_q8_0 *) vy; + for (int x = 0; x < nc / ncols_interleaved; x++) { + const block_iq4_nlx4 * b_ptr = (const block_iq4_nlx4 *) vx + (x * nb); + + for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (2 * blocklen)); k++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumi = 0; + for (int i = 0; i < blocklen; ++i) { + const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; + const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; + sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])); + } + sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); + } + } + } + for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; + } +} + +void ggml_gemv_iq4_nl_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK8_0; + const int nb = n / qk; + const int ncols_interleaved = 8; + const int blocklen = 8; + + assert(nr == 1); + assert(n % qk == 0); + assert(nc % ncols_interleaved == 0); + + UNUSED(bs); + UNUSED(nr); + + float sumf[8]; + int sumi; + + const block_q8_0 * a_ptr = (const block_q8_0 *) vy; + for (int x = 0; x < nc / ncols_interleaved; x++) { + const block_iq4_nlx8 * b_ptr = (const block_iq4_nlx8 *) vx + (x * nb); + + for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (2 * blocklen)); k++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumi = 0; + for (int i = 0; i < blocklen; ++i) { + const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; + const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; + sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])); + } + sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); + } + } + } + for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; } } @@ -712,6 +816,97 @@ void ggml_gemm_q4_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, } } +void ggml_gemm_q2_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK_K; + const int nb = n / qk; + const int ncols_interleaved = 8; + const int blocklen = 8; + + assert (n % qk == 0); + assert (nr % 4 == 0); + assert (nc % ncols_interleaved == 0); + + UNUSED(s); + UNUSED(bs); + UNUSED(vx); + UNUSED(vy); + UNUSED(nr); + UNUSED(nc); + UNUSED(nb); + UNUSED(ncols_interleaved); + UNUSED(blocklen); + + float sumf[4][8]; + float sum_minf[4][8]; + int sumi1, sumi2, sumi3, sumi4; + int sumi; + + for (int y = 0; y < nr / 4; y++) { + const block_q8_Kx4 * a_ptr = (const block_q8_Kx4 *) vy + (y * nb); + for (int x = 0; x < nc / ncols_interleaved; x++) { + const block_q2_Kx8 * b_ptr = (const block_q2_Kx8 *) vx + (x * nb); + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumf[m][j] = 0.0; + sum_minf[m][j] = 0.0; + } + } + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (4 * blocklen)); k++) { + + const uint8_t *scales_0 = b_ptr[l].scales + (k / 4) * 64 ; + const uint8_t *scales_1 = b_ptr[l].scales + (k / 4) * 64 + 16; + const uint8_t *scales_2 = b_ptr[l].scales + (k / 4) * 64 + 32; + const uint8_t *scales_3 = b_ptr[l].scales + (k / 4) * 64 + 48; + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumi1 = 0; + sumi2 = 0; + sumi3 = 0; + sumi4 = 0; + sumi = 0; + int offset = ((k / 2) % 2) + j * 2; + for (int i = 0; i < blocklen; ++i){ + const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 3); + const int v1 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 2 ) & 3); + const int v2 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4 ) & 3); + const int v3 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 6 ) & 3); + sumi1 = (v0 * a_ptr[l].qs[(k >> 2) * 512 + (k % 4) * 4 * blocklen + m * blocklen + i]); + sumi2 = (v1 * a_ptr[l].qs[(k >> 2) * 512 + (k % 4) * 4 * blocklen + m * blocklen + i + 128]); + sumi3 = (v2 * a_ptr[l].qs[(k >> 2) * 512 + (k % 4) * 4 * blocklen + m * blocklen + i + 256]); + sumi4 = (v3 * a_ptr[l].qs[(k >> 2) * 512 + (k % 4) * 4 * blocklen + m * blocklen + i + 384]); + sumi1 = sumi1 * (scales_0[offset] & 0xF); + sumi2 = sumi2 * (scales_1[offset] & 0xF); + sumi3 = sumi3 * (scales_2[offset] & 0xF); + sumi4 = sumi4 * (scales_3[offset] & 0xF); + sumi += sumi1 + sumi2 + sumi3 + sumi4; + } + sumf[m][j] += sumi * GGML_FP16_TO_FP32(b_ptr[l].d[j]) * a_ptr[l].d[m]; + } + } + } + for(int sb = 0; sb < 8; sb++) { + const uint8_t *mins = b_ptr[l].scales + sb * 16; + for(int m = 0; m < 4; m++) { + const int16_t *bsums = a_ptr[l].bsums + (sb * 8) + (m * 4) - ((sb % 2) * 6); + for(int j = 0; j < ncols_interleaved; j++) { + int mins_prod = ((mins[j * 2] >> 4) * bsums[0] + (mins[(j * 2)+ 1] >> 4) * bsums[1]); + sum_minf[m][j] += (mins_prod) * GGML_FP16_TO_FP32(b_ptr[l].dmin[j]) * a_ptr[l].d[m]; + } + } + } + } + + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) { + s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j] - sum_minf[m][j]; + } + } + } + } +} + + void ggml_gemm_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { const int qk = QK8_0; const int nb = n / qk; @@ -768,6 +963,50 @@ void ggml_gemm_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs } } +void ggml_gemm_iq4_nl_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK8_0; + const int nb = n / qk; + const int ncols_interleaved = 8; + const int blocklen = 8; + + assert(n % qk == 0); + assert(nr % 4 == 0); + assert(nc % ncols_interleaved == 0); + + float sumf[4][8]; + int sumi; + + for (int y = 0; y < nr / 4; y++) { + const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); + for (int x = 0; x < nc / ncols_interleaved; x++) { + const block_iq4_nlx8 * b_ptr = (const block_iq4_nlx8 *) vx + (x * nb); + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; + } + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (2 * blocklen)); k++) { + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumi = 0; + for (int i = 0; i < blocklen; ++i) { + const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; + const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; + sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + + (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])); + } + sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); + } + } + } + } + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) + s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; + } + } + } +} + } // extern "C" static block_q4_0x4 make_block_q4_0x4(block_q4_0 * in, unsigned int blck_size_interleave) { @@ -915,6 +1154,50 @@ static block_q4_Kx8 make_block_q4_Kx8(block_q4_K * in, unsigned int blck_size_in return out; } +static block_q2_Kx8 make_block_q2_Kx8(block_q2_K * in, unsigned int blck_size_interleave) { + block_q2_Kx8 out; + + // Delta(scale) and dmin values of the eight Q2_K structures are copied onto the output interleaved structure + for (int i = 0; i < 8; i++) { + out.d[i] = in[i].GGML_COMMON_AGGR_U.GGML_COMMON_AGGR_S.d; + } + + for (int i = 0; i < 8; i++) { + out.dmin[i] = in[i].GGML_COMMON_AGGR_U.GGML_COMMON_AGGR_S.dmin; + } + + const int end = QK_K * 2 / blck_size_interleave; + + // Interleave Q2_K quants by taking 8 bytes at a time + for (int i = 0; i < end; ++i) { + int src_id = i % 8; + int src_offset = (i / 8) * blck_size_interleave; + int dst_offset = i * blck_size_interleave; + + uint64_t elems; + memcpy(&elems, &in[src_id].qs[src_offset], sizeof(uint64_t)); + memcpy(&out.qs[dst_offset], &elems, sizeof(uint64_t)); + } + + // The below logic is designed so as to unpack and rearrange scales and mins values in Q2_K + // Currently the Q2_K structure has 16 scales and 16 mins packed in 16 bytes ( 4 bits for each value) + // The output Q2_Kx8 structure has 128 bytes for storing scales and mins + // Every 16 byte is packed such that it contains scales and mins for corresponding sub blocks from Q2_K structure + // For eg - First 16 bytes contains 16 scales and 16 mins - each of first and second sub blocks from different Q2_K structures + + for(int i = 0; i < 128; i++){ + + // Index for selecting which q2k super block + int src1 = (i % 16) / 2; + // Index for selecting scale + int src2 = ((i / 16) * 2) + (i % 2); + + out.scales[i] = in[src1].scales[src2]; + } + return out; + +} + static int repack_q4_0_to_q4_0_4_bl(struct ggml_tensor * t, int interleave_block, const void * GGML_RESTRICT data, size_t data_size) { GGML_ASSERT(t->type == GGML_TYPE_Q4_0); GGML_ASSERT(interleave_block == 4 || interleave_block == 8); @@ -976,6 +1259,37 @@ static int repack_q4_K_to_q4_K_8_bl(struct ggml_tensor * t, int interleave_block GGML_UNUSED(data_size); } +static int repack_q2_K_to_q2_K_8_bl(struct ggml_tensor * t, int interleave_block, const void * GGML_RESTRICT data, size_t data_size) { + GGML_ASSERT(t->type == GGML_TYPE_Q2_K); + GGML_ASSERT(interleave_block == 8); + constexpr int nrows_interleaved = 8; + + block_q2_Kx8 * dst = (block_q2_Kx8*)t->data; + const block_q2_K * src = (const block_q2_K*) data; + block_q2_K dst_tmp[8]; + int nrow = ggml_nrows(t); + int nblocks = t->ne[0] / QK_K; + + GGML_ASSERT(data_size == nrow * nblocks * sizeof(block_q2_K)); + + if (t->ne[1] % nrows_interleaved != 0 || t->ne[0] % 8 != 0) { + return -1; + } + + for (int b = 0; b < nrow; b += nrows_interleaved) { + for (int64_t x = 0; x < nblocks; x++) { + for (int i = 0; i < nrows_interleaved; i++ ) { + dst_tmp[i] = src[x + i * nblocks]; + } + *dst++ = make_block_q2_Kx8(dst_tmp, interleave_block); + } + src += nrows_interleaved * nblocks; + } + return 0; + + GGML_UNUSED(data_size); +} + static int repack_q4_0_to_q4_0_8_bl(struct ggml_tensor * t, int interleave_block, const void * GGML_RESTRICT data, size_t data_size) { GGML_ASSERT(t->type == GGML_TYPE_Q4_0); GGML_ASSERT(interleave_block == 8); @@ -1044,15 +1358,16 @@ static block_iq4_nlx4 make_block_iq4_nlx4(block_iq4_nl * in, unsigned int blck_s static int repack_iq4_nl_to_iq4_nl_4_bl(struct ggml_tensor * t, int interleave_block, const void * GGML_RESTRICT data, size_t data_size) { GGML_ASSERT(t->type == GGML_TYPE_IQ4_NL); - //GGML_ASSERT(interleave_block == 4 || interleave_block == 8); GGML_ASSERT(interleave_block == 4); - block_iq4_nlx4 * dst = (block_iq4_nlx4 *)t->data; - const block_iq4_nl * src = (const block_iq4_nl *)data; + const block_iq4_nl * src = (const block_iq4_nl *)data; + block_iq4_nlx4 * dst = ( block_iq4_nlx4 *)t->data; + block_iq4_nl dst_tmp[4]; + int nrow = ggml_nrows(t); int nrows_interleaved = 4; - int nblocks = t->ne[0] / QK4_0; + int nblocks = t->ne[0] / QK4_NL; GGML_ASSERT(data_size == nrow * nblocks * sizeof(block_iq4_nl)); @@ -1074,6 +1389,63 @@ static int repack_iq4_nl_to_iq4_nl_4_bl(struct ggml_tensor * t, int interleave_b GGML_UNUSED(data_size); } +static block_iq4_nlx8 make_block_iq4_nlx8(block_iq4_nl * in, unsigned int blck_size_interleave) { + block_iq4_nlx8 out; + + for (int i = 0; i < 8; i++) { + out.d[i] = in[i].d; + } + + const int end = QK4_NL * 4 / blck_size_interleave; + + if (blck_size_interleave == 8) { + for (int i = 0; i < end; ++i) { + int src_id = i % 8; + int src_offset = (i / 8) * blck_size_interleave; + int dst_offset = i * blck_size_interleave; + + memcpy(&out.qs[dst_offset], &in[src_id].qs[src_offset], sizeof(uint64_t)); + } + } else { + GGML_ASSERT(false); + } + + return out; +} + +static int repack_iq4_nl_to_iq4_nl_8_bl(struct ggml_tensor * t, int interleave_block, const void * GGML_RESTRICT data, size_t data_size) { + GGML_ASSERT(t->type == GGML_TYPE_IQ4_NL); + GGML_ASSERT(interleave_block == 8); + + const block_iq4_nl * src = (const block_iq4_nl *)data; + block_iq4_nlx8 * dst = ( block_iq4_nlx8 *)t->data; + + block_iq4_nl dst_tmp[8]; + + int nrow = ggml_nrows(t); + int nrows_interleaved = 8; + int nblocks = t->ne[0] / QK4_NL; + + GGML_ASSERT(data_size == nrow * nblocks * sizeof(block_iq4_nl)); + + if (t->ne[1] % nrows_interleaved != 0) { + return -1; + } + + for (int b = 0; b < nrow; b += nrows_interleaved) { + for (int64_t x = 0; x < nblocks; x++) { + for (int i = 0; i < nrows_interleaved; i++) { + dst_tmp[i] = src[x + i * nblocks]; + } + *dst++ = make_block_iq4_nlx8(dst_tmp, interleave_block); + } + src += nrows_interleaved * nblocks; + } + return 0; + + GGML_UNUSED(data_size); +} + namespace ggml::cpu::repack { // repack template @@ -1096,6 +1468,10 @@ template <> int repack(struct ggml_tensor * t, const void * da return repack_q4_K_to_q4_K_8_bl(t, 8, data, data_size); } +template <> int repack(struct ggml_tensor * t, const void * data, size_t data_size) { + return repack_q2_K_to_q2_K_8_bl(t, 8, data, data_size); +} + template <> int repack(struct ggml_tensor * t, const void * data, size_t data_size) { return repack_iq4_nl_to_iq4_nl_4_bl(t, 4, data, data_size); } @@ -1105,6 +1481,10 @@ template <> int repack(struct ggml_tensor * t, const void * // return repack_iq4_nl_to_iq4_nl_4_bl(t, 8, data, data_size); //} +template <> int repack(struct ggml_tensor * t, const void * data, size_t data_size) { + return repack_iq4_nl_to_iq4_nl_8_bl(t, 8, data, data_size); +} + // gemv template void gemv(int, float *, size_t, const void *, const void *, int, int); @@ -1125,10 +1505,18 @@ template <> void gemv(int n, float * s, size_t ggml_gemv_q4_K_8x8_q8_K(n, s, bs, vx, vy, nr, nc); } +template <> void gemv(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { + ggml_gemv_q2_K_8x8_q8_K(n, s, bs, vx, vy, nr, nc); +} + template <> void gemv(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { ggml_gemv_iq4_nl_4x4_q8_0(n, s, bs, vx, vy, nr, nc); } +template <> void gemv(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { + ggml_gemv_iq4_nl_8x8_q8_0(n, s, bs, vx, vy, nr, nc); +} + // gemm template void gemm(int, float *, size_t, const void *, const void *, int, int); @@ -1149,10 +1537,18 @@ template <> void gemm(int n, float * s, size_t ggml_gemm_q4_K_8x8_q8_K(n, s, bs, vx, vy, nr, nc); } +template <> void gemm(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { + ggml_gemm_q2_K_8x8_q8_K(n, s, bs, vx, vy, nr, nc); +} + template <> void gemm(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { ggml_gemm_iq4_nl_4x4_q8_0(n, s, bs, vx, vy, nr, nc); } +template <> void gemm(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { + ggml_gemm_iq4_nl_8x8_q8_0(n, s, bs, vx, vy, nr, nc); +} + class tensor_traits_base : public ggml::cpu::tensor_traits { public: virtual int repack(struct ggml_tensor * t, const void * data, size_t data_size) = 0; @@ -1422,8 +1818,12 @@ static const ggml::cpu::tensor_traits * ggml_repack_get_optimal_repack_type(cons static const ggml::cpu::repack::tensor_traits q4_0_8x8_q8_0; static const ggml::cpu::repack::tensor_traits q4_K_8x8_q8_K; + // instance for Q2 + static const ggml::cpu::repack::tensor_traits q2_K_8x8_q8_K; + // instance for IQ4 static const ggml::cpu::repack::tensor_traits iq4_nl_4x4_q8_0; + static const ggml::cpu::repack::tensor_traits iq4_nl_8x8_q8_0; if (cur->type == GGML_TYPE_Q4_0) { if (ggml_cpu_has_avx2() || (ggml_cpu_has_sve() && ggml_cpu_has_matmul_int8() && ggml_cpu_get_sve_cnt() == QK8_0)) { @@ -1447,7 +1847,18 @@ static const ggml::cpu::tensor_traits * ggml_repack_get_optimal_repack_type(cons return &q4_K_8x8_q8_K; } } + } else if (cur->type == GGML_TYPE_Q2_K) { + if (ggml_cpu_has_avx512()) { + if (cur->ne[1] % 8 == 0) { + return &q2_K_8x8_q8_K; + } + } } else if (cur->type == GGML_TYPE_IQ4_NL) { + if (ggml_cpu_has_avx2()) { + if (cur->ne[1] % 8 == 0) { + return &iq4_nl_8x8_q8_0; + } + } if (ggml_cpu_has_neon() && ggml_cpu_has_dotprod()) { if (cur->ne[1] % 4 == 0) { return &iq4_nl_4x4_q8_0; diff --git a/ggml/src/ggml-cpu/repack.h b/ggml/src/ggml-cpu/repack.h index 4421e5f8e7..cb32b503d3 100644 --- a/ggml/src/ggml-cpu/repack.h +++ b/ggml/src/ggml-cpu/repack.h @@ -44,7 +44,14 @@ struct block_q4_Kx8 { }; static_assert(sizeof(block_q4_Kx8) == sizeof(ggml_half) * 16 + K_SCALE_SIZE * 8 + QK_K * 4, "wrong q4_K block size/padding"); +struct block_q2_Kx8 { + ggml_half d[8]; // super-block scale for quantized scales + ggml_half dmin[8]; // super-block scale for quantized mins + uint8_t scales[128]; // scales and mins, quantized with 4 bits + uint8_t qs[512]; // 2--bit quants +}; +static_assert(sizeof(block_q2_Kx8) == sizeof(ggml_half) * 16 + QK_K/2 + QK_K * 2, "wrong q2_K block size/padding"); struct block_q8_Kx4 { float d[4]; // delta int8_t qs[QK_K * 4]; // quants @@ -60,6 +67,13 @@ struct block_iq4_nlx4 { static_assert(sizeof(block_iq4_nlx4) == 4 * sizeof(ggml_half) + QK4_NL * 2, "wrong iq4_nlx4 block size/padding"); +struct block_iq4_nlx8 { + ggml_half d[8]; // deltas for 8 iq4_nl blocks + uint8_t qs[QK4_NL * 4]; // nibbles / quants for 8 iq4_nl blocks +}; + +static_assert(sizeof(block_iq4_nlx8) == 8 * sizeof(ggml_half) + QK4_NL * 4, "wrong iq4_nlx8 block size/padding"); + #if defined(__cplusplus) extern "C" { #endif @@ -71,12 +85,16 @@ void ggml_gemv_q4_0_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const vo void ggml_gemv_q4_0_4x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_q4_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemv_q2_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_iq4_nl_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemv_iq4_nl_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_4x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemm_q2_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_iq4_nl_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemm_iq4_nl_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); // Native implementations void ggml_quantize_mat_q8_0_4x4_generic(const float * GGML_RESTRICT x, void * GGML_RESTRICT vy, int64_t k); @@ -86,12 +104,16 @@ void ggml_gemv_q4_0_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, void ggml_gemv_q4_0_4x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_q4_0_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_q4_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemv_q2_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemv_iq4_nl_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_4x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemm_q2_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemm_iq4_nl_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); #if defined(__cplusplus) } // extern "C" diff --git a/ggml/src/ggml-cpu/traits.cpp b/ggml/src/ggml-cpu/traits.cpp index 139fa59641..4f32f10255 100644 --- a/ggml/src/ggml-cpu/traits.cpp +++ b/ggml/src/ggml-cpu/traits.cpp @@ -10,7 +10,7 @@ extra_buffer_type::~extra_buffer_type() {} } // namespace ggml::cpu bool ggml_cpu_extra_compute_forward(struct ggml_compute_params * params, struct ggml_tensor * op) { - for (auto extra : ggml_backend_cpu_get_extra_buffers_type()) { + for (auto extra : ggml_backend_cpu_get_extra_buffer_types()) { if (extra && extra->context) { auto buf_extra = (ggml::cpu::extra_buffer_type *) extra->context; auto tensor_traits = buf_extra->get_tensor_traits(op); @@ -23,7 +23,7 @@ bool ggml_cpu_extra_compute_forward(struct ggml_compute_params * params, struct } bool ggml_cpu_extra_work_size(int n_threads, const struct ggml_tensor * op, size_t * size) { - for (auto extra : ggml_backend_cpu_get_extra_buffers_type()) { + for (auto extra : ggml_backend_cpu_get_extra_buffer_types()) { if (extra && extra->context) { auto buf_extra = (ggml::cpu::extra_buffer_type *) extra->context; auto tensor_traits = buf_extra->get_tensor_traits(op); diff --git a/ggml/src/ggml-cpu/traits.h b/ggml/src/ggml-cpu/traits.h index 99a6186b1d..f4e0990ddf 100644 --- a/ggml/src/ggml-cpu/traits.h +++ b/ggml/src/ggml-cpu/traits.h @@ -33,6 +33,6 @@ class extra_buffer_type { } // namespace ggml::cpu // implemented in ggml-cpu.cpp. -std::vector & ggml_backend_cpu_get_extra_buffers_type(); +std::vector & ggml_backend_cpu_get_extra_buffer_types(); #endif diff --git a/ggml/src/ggml-cpu/vec.h b/ggml/src/ggml-cpu/vec.h index d18783a00a..2250d93cb0 100644 --- a/ggml/src/ggml-cpu/vec.h +++ b/ggml/src/ggml-cpu/vec.h @@ -55,7 +55,22 @@ inline static void ggml_vec_cpy_i32(const int n, int32_t * y, const int32_t * x) inline static void ggml_vec_set_f16(const int n, ggml_fp16_t * x, const ggml_fp16_t v) { for (int i = 0; i < n; ++i) x[i] = v; } inline static void ggml_vec_set_bf16(const int n, ggml_bf16_t * x, const ggml_bf16_t v) { for (int i = 0; i < n; ++i) x[i] = v; } -inline static void ggml_vec_add_f32 (const int n, float * z, const float * x, const float * y) { for (int i = 0; i < n; ++i) z[i] = x[i] + y[i]; } + +inline static void ggml_vec_add_f32 (const int n, float * z, const float * x, const float * y) { + int i = 0; +#if defined(__AVX2__) + for (; i + 7 < n; i += 8) { + __m256 vx = _mm256_loadu_ps(x + i); + __m256 vy = _mm256_loadu_ps(y + i); + __m256 vz = _mm256_add_ps(vx, vy); + _mm256_storeu_ps(z + i, vz); + } +#endif + for (; i < n; ++i) { + z[i] = x[i] + y[i]; + } +} + inline static void ggml_vec_add_f16 (const int n, ggml_fp16_t * z, const ggml_fp16_t * x, const ggml_fp16_t * y) { for (int i = 0; i < n; ++i) { z[i] = GGML_CPU_FP32_TO_FP16(GGML_CPU_FP16_TO_FP32(x[i]) + GGML_CPU_FP16_TO_FP32(y[i])); @@ -992,9 +1007,9 @@ void ggml_vec_swiglu_f32(const int n, float * y, const float * x, const float * inline static void ggml_vec_swiglu_f16(const int n, ggml_fp16_t * y, const ggml_fp16_t * x, const ggml_fp16_t * g) { for (int i = 0; i < n; ++i) { - float v = GGML_CPU_FP16_TO_FP32(x[i]); - float w = GGML_CPU_FP16_TO_FP32(g[i]); - y[i] = GGML_CPU_FP32_TO_FP16((v/(1.0f + expf(-v))) * w); + float xi = GGML_CPU_FP16_TO_FP32(x[i]); + float gi = GGML_CPU_FP16_TO_FP32(g[i]); + y[i] = GGML_CPU_FP32_TO_FP16((xi/(1.0f + expf(-xi))) * gi); } } diff --git a/ggml/src/ggml-cuda/CMakeLists.txt b/ggml/src/ggml-cuda/CMakeLists.txt index c9ff4aa321..bce07ac362 100644 --- a/ggml/src/ggml-cuda/CMakeLists.txt +++ b/ggml/src/ggml-cuda/CMakeLists.txt @@ -102,12 +102,12 @@ if (CUDAToolkit_FOUND) if (GGML_STATIC) if (WIN32) # As of 12.3.1 CUDA Toolkit for Windows does not offer a static cublas library - target_link_libraries(ggml-cuda PRIVATE CUDA::cudart_static CUDA::cublas CUDA::cublasLt) + target_link_libraries(ggml-cuda PRIVATE CUDA::cudart_static CUDA::cublas) else () - target_link_libraries(ggml-cuda PRIVATE CUDA::cudart_static CUDA::cublas_static CUDA::cublasLt_static) + target_link_libraries(ggml-cuda PRIVATE CUDA::cudart_static CUDA::cublas_static) endif() else() - target_link_libraries(ggml-cuda PRIVATE CUDA::cudart CUDA::cublas CUDA::cublasLt) + target_link_libraries(ggml-cuda PRIVATE CUDA::cudart CUDA::cublas) endif() if (GGML_CUDA_NO_VMM) @@ -120,6 +120,10 @@ if (CUDAToolkit_FOUND) set(CUDA_FLAGS -use_fast_math -extended-lambda) + if (GGML_CUDA_DEBUG) + list(APPEND CUDA_FLAGS -lineinfo) + endif() + if (CUDAToolkit_VERSION VERSION_GREATER_EQUAL "12.8") # Options are: # - none (not recommended) diff --git a/ggml/src/ggml-cuda/add-id.cu b/ggml/src/ggml-cuda/add-id.cu new file mode 100644 index 0000000000..8bed62ac9d --- /dev/null +++ b/ggml/src/ggml-cuda/add-id.cu @@ -0,0 +1,58 @@ +#include "add-id.cuh" + +static __global__ void add_id_kernel( + const float * src0, const float * src1, const int32_t * src2, float * dst, + int64_t ne0, int64_t ne1, + size_t nb01, size_t nb02, + size_t nb11, + size_t nb21 + ) { + + const int64_t i1 = blockIdx.x; + const int64_t i2 = blockIdx.y; + + const int i11 = *(int32_t *) ((char *) src2 + i1*sizeof(int32_t) + i2*nb21); + + const size_t nb1 = ne0 * sizeof(float); + const size_t nb2 = ne1 * nb1; + + float * dst_row = (float *)((char *)dst + i1*nb1 + i2*nb2); + const float * src0_row = (const float *)((char *)src0 + i1*nb01 + i2*nb02); + const float * src1_row = (const float *)((char *)src1 + i11*nb11); + + for (int64_t i0 = threadIdx.x; i0 < ne0; i0 += blockDim.x) { + dst_row[i0] = src0_row[i0] + src1_row[i0]; + } +} + +void ggml_cuda_op_add_id(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + const ggml_tensor * src2 = dst->src[2]; + + GGML_TENSOR_TERNARY_OP_LOCALS + + GGML_ASSERT(dst->type == GGML_TYPE_F32); + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT(src2->type == GGML_TYPE_I32); + + GGML_ASSERT(nb00 == sizeof(float)); + GGML_ASSERT(nb10 == sizeof(float)); + GGML_ASSERT(nb20 == sizeof(int32_t)); + + const float * src0_d = (const float *)src0->data; + const float * src1_d = (const float *)src1->data; + const int32_t * src2_d = (const int32_t *)src2->data; + float * dst_d = (float *)dst->data; + + int threads = std::min((int)ne00, 768); // cols + dim3 blocks(ne01, ne02); // n_experts_used, n_tokens + add_id_kernel<<>>( + src0_d, src1_d, src2_d, dst_d, + ne0, ne1, + nb01, nb02, + nb11, + nb21 + ); +} diff --git a/ggml/src/ggml-cuda/add-id.cuh b/ggml/src/ggml-cuda/add-id.cuh new file mode 100644 index 0000000000..30b1721ac3 --- /dev/null +++ b/ggml/src/ggml-cuda/add-id.cuh @@ -0,0 +1,3 @@ +#include "common.cuh" + +void ggml_cuda_op_add_id(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff --git a/ggml/src/ggml-cuda/common.cuh b/ggml/src/ggml-cuda/common.cuh index 1a2708ec9d..2b14b30ac9 100644 --- a/ggml/src/ggml-cuda/common.cuh +++ b/ggml/src/ggml-cuda/common.cuh @@ -1,6 +1,7 @@ #pragma once #include "ggml.h" +#include "ggml-impl.h" #include "ggml-cuda.h" #include @@ -56,7 +57,7 @@ #define GGML_CUDA_CC_GCN4 (GGML_CUDA_CC_OFFSET_AMD + 0x803) // Tonga, Fiji, Polaris, minimum for fast fp16 #define GGML_CUDA_CC_VEGA (GGML_CUDA_CC_OFFSET_AMD + 0x900) // Vega56/64, minimum for fp16 dual issue #define GGML_CUDA_CC_VEGA20 (GGML_CUDA_CC_OFFSET_AMD + 0x906) // MI50/Radeon VII, minimum for dp4a -#define GGML_CUDA_CC_CDNA (GGML_CUDA_CC_OFFSET_AMD + 0x908) // MI100, minimum for MFMA, acc registers +#define GGML_CUDA_CC_CDNA1 (GGML_CUDA_CC_OFFSET_AMD + 0x908) // MI100, minimum for MFMA, acc registers #define GGML_CUDA_CC_CDNA2 (GGML_CUDA_CC_OFFSET_AMD + 0x910) // MI210, minimum acc register renameing #define GGML_CUDA_CC_CDNA3 (GGML_CUDA_CC_OFFSET_AMD + 0x942) // MI300 @@ -72,8 +73,9 @@ #define GGML_CUDA_CC_IS_RDNA2(cc) (cc >= GGML_CUDA_CC_RDNA2 && cc < GGML_CUDA_CC_RDNA3) #define GGML_CUDA_CC_IS_RDNA3(cc) (cc >= GGML_CUDA_CC_RDNA3 && cc < GGML_CUDA_CC_RDNA4) #define GGML_CUDA_CC_IS_RDNA4(cc) (cc >= GGML_CUDA_CC_RDNA4) -#define GGML_CUDA_CC_IS_GCN(cc) (cc > GGML_CUDA_CC_OFFSET_AMD && cc < GGML_CUDA_CC_CDNA) -#define GGML_CUDA_CC_IS_CDNA(cc) (cc >= GGML_CUDA_CC_CDNA && cc < GGML_CUDA_CC_RDNA1) +#define GGML_CUDA_CC_IS_GCN(cc) (cc > GGML_CUDA_CC_OFFSET_AMD && cc < GGML_CUDA_CC_CDNA1) +#define GGML_CUDA_CC_IS_CDNA(cc) (cc >= GGML_CUDA_CC_CDNA1 && cc < GGML_CUDA_CC_RDNA1) +#define GGML_CUDA_CC_IS_CDNA3(cc) (cc >= GGML_CUDA_CC_CDNA3 && cc < GGML_CUDA_CC_RDNA1) // Moore Threads #define GGML_CUDA_CC_QY1 (GGML_CUDA_CC_OFFSET_MTHREADS + 0x210) // MTT S80, MTT S3000 @@ -85,6 +87,10 @@ #define GGML_CUDA_CC_IS_QY2(cc) (cc >= GGML_CUDA_CC_QY2 && cc < GGML_CUDA_CC_NG) #define GGML_CUDA_CC_IS_NG(cc) (cc >= GGML_CUDA_CC_NG) +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 +# define GGML_CUDA_USE_CUB +#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 + #ifdef __CUDA_ARCH_LIST__ constexpr bool ggml_cuda_has_arch_impl(int) { return false; @@ -175,7 +181,7 @@ static const char * cu_get_error_str(CUresult err) { #define CU_CHECK(err) CUDA_CHECK_GEN(err, CUDA_SUCCESS, cu_get_error_str) #endif -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) # define CUDA_SET_SHARED_MEMORY_LIMIT(kernel, nbytes) \ do { \ static bool shared_memory_limit_raised[GGML_CUDA_MAX_DEVICES] = { false }; \ @@ -190,7 +196,7 @@ static const char * cu_get_error_str(CUresult err) { do { \ GGML_UNUSED(nbytes); \ } while (0) -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#endif // !(defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) #if CUDART_VERSION >= 11010 || defined(GGML_USE_MUSA) #define GGML_CUDA_ASSUME(x) __builtin_assume(x) @@ -210,9 +216,9 @@ typedef float2 dfloat2; #define GGML_USE_VMM #endif // (!defined(GGML_USE_HIP) && !defined(GGML_CUDA_NO_VMM)) || (defined(GGML_USE_HIP) && !defined(GGML_HIP_NO_VMM)) -#if (defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) || __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL +#if defined(GGML_USE_HIP) || __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL #define FP16_AVAILABLE -#endif // (defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) || __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL +#endif // defined(GGML_USE_HIP) || __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL #if defined(FP16_AVAILABLE) && __CUDA_ARCH__ != 610 #define FAST_FP16_AVAILABLE @@ -226,13 +232,21 @@ typedef float2 dfloat2; #define FP16_MMA_AVAILABLE #endif // defined(GGML_HIP_ROCWMMA_FATTN) && (defined(CDNA) || defined(RDNA3) || (defined(GGML_HIP_ROCWMMA_FATTN_GFX12) && defined(RDNA4))) -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_TURING -#define NEW_MMA_AVAILABLE -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_TURING +#if defined(GGML_USE_HIP) && defined(CDNA) && !defined(GGML_HIP_NO_MMQ_MFMA) +#define AMD_MFMA_AVAILABLE +#endif // defined(GGML_USE_HIP) && defined(CDNA) && !defined(GGML_HIP_NO_MMQ_MFMA) -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE +#if !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_TURING +#define TURING_MMA_AVAILABLE +#endif // !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_TURING + +#if !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE +#define AMPERE_MMA_AVAILABLE +#endif // !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE + +#if !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #define CP_ASYNC_AVAILABLE -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE +#endif // !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #if !defined(GGML_CUDA_NO_FA) && !(defined(GGML_USE_MUSA) && __MUSA_ARCH__ < 220) #define FLASH_ATTN_AVAILABLE @@ -254,7 +268,7 @@ static bool fast_fp16_hardware_available(const int cc) { // Any FP16 tensor core instructions are available for ggml code. static bool fp16_mma_available(const int cc) { -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) && !defined(GGML_HIP_ROCWMMA_FATTN) +#if defined(GGML_USE_HIP) && !defined(GGML_HIP_ROCWMMA_FATTN) return false; #else if ((GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA) || @@ -270,7 +284,7 @@ static bool fp16_mma_available(const int cc) { } else { return false; } -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) && !defined(GGML_HIP_ROCWMMA_FATTN) +#endif // defined(GGML_USE_HIP) && !defined(GGML_HIP_ROCWMMA_FATTN) } // To be used for feature selection of external libraries, e.g. cuBLAS. @@ -288,35 +302,47 @@ static bool fp32_mma_hardware_available(const int cc) { return GGML_CUDA_CC_IS_CDNA(cc); } +static bool amd_mfma_available(const int cc) { +#if !defined(GGML_HIP_NO_MMQ_MFMA) + return GGML_CUDA_CC_IS_CDNA(cc); +#else + return false; +#endif //!defined(GGML_HIP_NO_MMQ_MFMA) +} + // Volta technically had FP16 tensor cores but they work very differently compared to Turing and later. -static bool new_mma_available(const int cc) { +static bool turing_mma_available(const int cc) { return GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_TURING; } +static bool ampere_mma_available(const int cc) { + return GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_AMPERE; +} + static bool cp_async_available(const int cc) { - return cc < GGML_CUDA_CC_OFFSET_AMD && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_AMPERE; + return GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_AMPERE; } static constexpr __device__ int ggml_cuda_get_physical_warp_size() { -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) && (defined(__GFX9__) || defined(__GFX8__)) +#if defined(GGML_USE_HIP) && (defined(__GFX9__) || defined(__GFX8__)) return 64; #else return 32; -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) && (defined(__GFX9__) || defined(__GFX8__)) +#endif // defined(GGML_USE_HIP) && (defined(__GFX9__) || defined(__GFX8__)) } [[noreturn]] static __device__ void no_device_code( const char * file_name, const int line, const char * function_name, const int arch, const char * arch_list) { -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) printf("%s:%d: ERROR: HIP kernel %s has no device code compatible with HIP arch %d.\n", file_name, line, function_name, arch); GGML_UNUSED(arch_list); #else printf("%s:%d: ERROR: CUDA kernel %s has no device code compatible with CUDA arch %d. ggml-cuda.cu was compiled for: %s\n", file_name, line, function_name, arch, arch_list); -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#endif // defined(GGML_USE_HIP) __trap(); GGML_UNUSED(no_device_code); // suppress unused function warning @@ -353,7 +379,7 @@ struct ggml_cuda_unroll<1> { template static __device__ __forceinline__ int warp_reduce_sum(int x) { -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE +#if !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE return __reduce_add_sync(0xffffffff, x); #else #pragma unroll @@ -361,7 +387,7 @@ static __device__ __forceinline__ int warp_reduce_sum(int x) { x += __shfl_xor_sync(0xffffffff, x, offset, width); } return x; -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE +#endif // !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE } template @@ -398,24 +424,18 @@ static __device__ __forceinline__ half2 warp_reduce_sum(half2 a) { #endif // FP16_AVAILABLE } -// Row reduction kernel template - compute sum (norm=false) or mean (norm=true) -template -static __global__ void reduce_rows_f32(const float * x, float * dst, const int ncols) { - const int row = blockIdx.x; - const int col = threadIdx.x; - - float sum = 0.0f; - for (int i = col; i < ncols; i += blockDim.x) { - sum += x[row * ncols + i]; +template +static __device__ __forceinline__ int warp_reduce_all(int x) { +#ifdef GGML_USE_HIP +#pragma unroll + for (int offset = width/2; offset > 0; offset >>= 1) { + x = x && __shfl_xor_sync(0xffffffff, x, offset, width); } - - sum = warp_reduce_sum(sum); - - if (col != 0) { - return; - } - - dst[row] = norm ? sum / ncols : sum; + return x; +#else + static_assert(width == WARP_SIZE, "width != WARP_SIZE not implemented"); + return __all_sync(0xffffffff, x); +#endif // GGML_USE_HIP } template @@ -430,11 +450,11 @@ static __device__ __forceinline__ float warp_reduce_max(float x) { static __device__ __forceinline__ half ggml_cuda_hmax(const half a, const half b) { #ifdef FP16_AVAILABLE -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && CUDART_VERSION < CUDART_HMAX +#if !defined(GGML_USE_HIP) && CUDART_VERSION < CUDART_HMAX return __float2half(fmaxf(__half2float(a), __half2float(b))); #else return __hmax(a, b); -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && CUDART_VERSION < CUDART_HMAX +#endif // !defined(GGML_USE_HIP) && CUDART_VERSION < CUDART_HMAX #else NO_DEVICE_CODE; @@ -444,25 +464,21 @@ static __device__ __forceinline__ half ggml_cuda_hmax(const half a, const half b } static __device__ __forceinline__ half2 ggml_cuda_hmax2(const half2 a, const half2 b) { -#if defined(GGML_USE_HIP) && HIP_VERSION >= 50700000 +#if defined(GGML_USE_HIP) return half2(__hmax(a.x, b.x), __hmax(a.y, b.y)); -#elif !defined(GGML_USE_HIP) && CUDART_VERSION >= CUDART_HMAX +#elif CUDART_VERSION >= CUDART_HMAX return __hmax2(a, b); -#elif !defined(GGML_USE_HIP) +#else half2 ret; reinterpret_cast(ret.x) = __float2half(fmaxf( __low2float(a), __low2float(b))); reinterpret_cast(ret.y) = __float2half(fmaxf(__high2float(a), __high2float(b))); return ret; -#else - GGML_UNUSED(a); - GGML_UNUSED(b); - NO_DEVICE_CODE; #endif } template static __device__ __forceinline__ half2 warp_reduce_max(half2 x) { -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL || (defined(GGML_USE_HIP) && HIP_VERSION >= 50700000) +#if !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL || defined(GGML_USE_HIP) #pragma unroll for (int offset = width/2; offset > 0; offset >>= 1) { x = ggml_cuda_hmax2(x, __shfl_xor_sync(0xffffffff, x, offset, width)); @@ -471,7 +487,7 @@ static __device__ __forceinline__ half2 warp_reduce_max(half2 x) { #else GGML_UNUSED(x); NO_DEVICE_CODE; -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL || (defined(GGML_USE_HIP) && HIP_VERSION >= 50700000) +#endif // !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL || defined(GGML_USE_HIP) } #if CUDART_VERSION < CUDART_HMASK @@ -483,7 +499,7 @@ static __device__ __forceinline__ uint32_t __hgt2_mask(const half2 a, const half #endif // CUDART_VERSION < CUDART_HMASK static __device__ __forceinline__ int ggml_cuda_dp4a(const int a, const int b, int c) { -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) #if defined(CDNA) || defined(RDNA2) || defined(__gfx906__) c = __builtin_amdgcn_sdot4(a, b, c, false); #elif defined(RDNA3) || defined(RDNA4) @@ -509,7 +525,7 @@ static __device__ __forceinline__ int ggml_cuda_dp4a(const int a, const int b, i #endif return c; -#else // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#else // defined(GGML_USE_HIP) #if __CUDA_ARCH__ >= GGML_CUDA_CC_DP4A || defined(GGML_USE_MUSA) return __dp4a(a, b, c); @@ -519,7 +535,25 @@ static __device__ __forceinline__ int ggml_cuda_dp4a(const int a, const int b, i return c + a8[0]*b8[0] + a8[1]*b8[1] + a8[2]*b8[2] + a8[3]*b8[3]; #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_DP4A || defined(GGML_USE_MUSA) -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#endif // defined(GGML_USE_HIP) +} + +static __device__ __forceinline__ float ggml_cuda_e8m0_to_fp32(uint8_t x) { +#if CUDART_VERSION >= 12080 + const nv_bfloat16 e = __nv_cvt_e8m0_to_bf16raw(x); + return (float) e; +#else + uint32_t bits; + if (x == 0) { + bits = 0x00400000; + } else { + bits = (uint32_t) x << 23; + } + + float result; + memcpy(&result, &bits, sizeof(float)); + return result; +#endif // CUDART_VERSION >= 12050 } typedef void (*dequantize_kernel_t)(const void * vx, const int64_t ib, const int iqs, dfloat2 & v); @@ -580,6 +614,13 @@ struct ggml_cuda_type_traits { static constexpr int qi = QI8_0; }; +template<> +struct ggml_cuda_type_traits { + static constexpr int qk = QK_MXFP4; + static constexpr int qr = QR_MXFP4; + static constexpr int qi = QI_MXFP4; +}; + template<> struct ggml_cuda_type_traits { static constexpr int qk = QK_K; @@ -765,7 +806,7 @@ struct ggml_tensor_extra_gpu { }; -#if (defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS)) +#if (defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS)) || defined(GGML_MUSA_GRAPHS) #define USE_CUDA_GRAPH #endif diff --git a/ggml/src/ggml-cuda/convert.cu b/ggml/src/ggml-cuda/convert.cu index eeaa14bf57..8f0efdcc12 100644 --- a/ggml/src/ggml-cuda/convert.cu +++ b/ggml/src/ggml-cuda/convert.cu @@ -6,24 +6,33 @@ #define CUDA_Q8_0_NE_ALIGN 2048 template -static __global__ void dequantize_block(const void * __restrict__ vx, dst_t * __restrict__ y, const int64_t k) { - const int64_t i = (int64_t)2*(blockDim.x*blockIdx.x + threadIdx.x); +static __global__ void dequantize_block(const void * __restrict__ vx, dst_t * __restrict__ y, + const int64_t ne00, const int64_t ne01, const int64_t ne02, + const int64_t s01, const int64_t s02, const int64_t s03) { + const int64_t i00 = 2 * (int64_t(blockDim.x)*blockIdx.x + threadIdx.x); - if (i >= k) { + if (i00 >= ne00) { return; } - const int64_t ib = i/qk; // block index - const int64_t iqs = (i%qk)/qr; // quant index - const int64_t iybs = i - i%qk; // y block start index + const int64_t i01 = blockIdx.y; + const int64_t i02 = blockIdx.z % ne02; + const int64_t i03 = blockIdx.z / ne02; + + const int64_t ibx0 = i03*s03 + i02*s02 + i01*s01; + + const int64_t ib = ibx0 + i00/qk; // block index + const int64_t iqs = (i00%qk)/qr; // quant index + const int64_t iybs = i00 - i00%qk; // y block start index const int64_t y_offset = qr == 1 ? 1 : qk/2; // dequantize dfloat2 v; dequantize_kernel(vx, ib, iqs, v); - y[iybs + iqs + 0] = v.x; - y[iybs + iqs + y_offset] = v.y; + const int64_t iy0 = ((i03*ne02 + i02)*ne01 + i01)*ne00 + iybs + iqs; + y[iy0 + 0] = ggml_cuda_cast(v.x); + y[iy0 + y_offset] = ggml_cuda_cast(v.y); } template @@ -456,10 +465,36 @@ static __global__ void dequantize_block_iq4_xs(const void * __restrict__ vx, dst } } +template +static __global__ void dequantize_block_mxfp4(const void * __restrict__ vx, dst_t * __restrict__ yy) { + + const int64_t i = blockIdx.x; + const block_mxfp4 * x = (const block_mxfp4 *) vx + i*(QK_K/QK_MXFP4); + + const int64_t tid = threadIdx.x; + const int64_t il = tid/8; // 0...3 + const int64_t ib = tid%8; // 0...7 + dst_t * y = yy + i*QK_K + 32*ib + 4*il; + const uint8_t * q4 = x[ib].qs + 4*il; + const float d = ggml_cuda_e8m0_to_fp32(x[ib].e); + for (int j = 0; j < 4; ++j) { + y[j+ 0] = d * kvalues_mxfp4[q4[j] & 0xf]*0.5f; + y[j+16] = d * kvalues_mxfp4[q4[j] >> 4]*0.5f; + } +} + template -static void dequantize_block_cuda(const void * __restrict__ vx, dst_t * __restrict__ y, const int64_t k, cudaStream_t stream) { - const int num_blocks = (k + 2*CUDA_DEQUANTIZE_BLOCK_SIZE - 1) / (2*CUDA_DEQUANTIZE_BLOCK_SIZE); - dequantize_block<<>>(vx, y, k); +static void dequantize_block_cuda(const void * vx, dst_t * y, + const int64_t ne00, const int64_t ne01, const int64_t ne02, const int64_t ne03, + const int64_t s01, const int64_t s02, const int64_t s03, cudaStream_t stream) { + const dim3 num_blocks((ne00 + 2*CUDA_DEQUANTIZE_BLOCK_SIZE - 1) / (2*CUDA_DEQUANTIZE_BLOCK_SIZE), ne01, ne02*ne03); + dequantize_block<<>> + (vx, y, ne00, ne01, ne02, s01, s02, s03); +} + +template +static void dequantize_block_cont_cuda(const void * __restrict__ vx, dst_t * __restrict__ y, const int64_t k, cudaStream_t stream) { + dequantize_block_cuda(vx, y, k, 1, 1, 1, k/qk, k/qk, k/qk, stream); } static void dequantize_block_q8_0_f16_cuda(const void * __restrict__ vx, half * __restrict__ y, const int64_t k, cudaStream_t stream) { @@ -571,6 +606,12 @@ static void dequantize_row_iq4_xs_cuda(const void * vx, dst_t * y, const int64_t dequantize_block_iq4_xs<<>>(vx, y); } +template +static void dequantize_row_mxfp4_cuda(const void * vx, dst_t * y, const int64_t k, cudaStream_t stream) { + const int nb = (k + QK_K - 1) / QK_K; + dequantize_block_mxfp4<<>>(vx, y); +} + template static __global__ void convert_unary( const void * __restrict__ vx, dst_t * __restrict__ y, const int64_t ne00, const int64_t ne01, const int64_t ne02, @@ -589,7 +630,7 @@ static __global__ void convert_unary( const int64_t ix = i03*s03 + i02*s02 + i01*s01 + i00; const int64_t iy = ((i03*ne02 + i02)*ne01 + i01)*ne00 + i00; - y[iy] = float(x[ix]); + y[iy] = ggml_cuda_cast(x[ix]); } template @@ -624,14 +665,14 @@ to_fp16_cuda_t ggml_get_to_fp16_cuda(ggml_type type) { case GGML_TYPE_Q4_1: return dequantize_row_q4_1_cuda; case GGML_TYPE_Q5_0: - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q5_1: - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q8_0: if (fp16_available(ggml_cuda_info().devices[ggml_cuda_get_device()].cc)) { return dequantize_block_q8_0_f16_cuda; } - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q2_K: return dequantize_row_q2_K_cuda; case GGML_TYPE_Q3_K: @@ -660,6 +701,8 @@ to_fp16_cuda_t ggml_get_to_fp16_cuda(ggml_type type) { return dequantize_row_iq4_xs_cuda; case GGML_TYPE_IQ3_S: return dequantize_row_iq3_s_cuda; + case GGML_TYPE_MXFP4: + return dequantize_row_mxfp4_cuda; case GGML_TYPE_F32: return convert_unary_cont_cuda; case GGML_TYPE_BF16: @@ -676,11 +719,11 @@ to_fp32_cuda_t ggml_get_to_fp32_cuda(ggml_type type) { case GGML_TYPE_Q4_1: return dequantize_row_q4_1_cuda; case GGML_TYPE_Q5_0: - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q5_1: - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q8_0: - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q2_K: return dequantize_row_q2_K_cuda; case GGML_TYPE_Q3_K: @@ -709,6 +752,8 @@ to_fp32_cuda_t ggml_get_to_fp32_cuda(ggml_type type) { return dequantize_row_iq4_xs_cuda; case GGML_TYPE_IQ3_S: return dequantize_row_iq3_s_cuda; + case GGML_TYPE_MXFP4: + return dequantize_row_mxfp4_cuda; case GGML_TYPE_F16: return convert_unary_cont_cuda; case GGML_TYPE_BF16: @@ -722,6 +767,16 @@ to_fp16_nc_cuda_t ggml_get_to_fp16_nc_cuda(ggml_type type) { switch (type) { case GGML_TYPE_F32: return convert_unary_cuda; + case GGML_TYPE_Q4_0: + return dequantize_block_cuda; + case GGML_TYPE_Q4_1: + return dequantize_block_cuda; + case GGML_TYPE_Q5_0: + return dequantize_block_cuda; + case GGML_TYPE_Q5_1: + return dequantize_block_cuda; + case GGML_TYPE_Q8_0: + return dequantize_block_cuda; case GGML_TYPE_BF16: return convert_unary_cuda; default: @@ -733,6 +788,16 @@ to_bf16_nc_cuda_t ggml_get_to_bf16_nc_cuda(ggml_type type) { switch (type) { case GGML_TYPE_F32: return convert_unary_cuda; + case GGML_TYPE_Q4_0: + return dequantize_block_cuda; + case GGML_TYPE_Q4_1: + return dequantize_block_cuda; + case GGML_TYPE_Q5_0: + return dequantize_block_cuda; + case GGML_TYPE_Q5_1: + return dequantize_block_cuda; + case GGML_TYPE_Q8_0: + return dequantize_block_cuda; case GGML_TYPE_F16: return convert_unary_cuda; default: @@ -744,6 +809,16 @@ to_fp32_nc_cuda_t ggml_get_to_fp32_nc_cuda(ggml_type type) { switch (type) { case GGML_TYPE_F16: return convert_unary_cuda; + case GGML_TYPE_Q4_0: + return dequantize_block_cuda; + case GGML_TYPE_Q4_1: + return dequantize_block_cuda; + case GGML_TYPE_Q5_0: + return dequantize_block_cuda; + case GGML_TYPE_Q5_1: + return dequantize_block_cuda; + case GGML_TYPE_Q8_0: + return dequantize_block_cuda; case GGML_TYPE_BF16: return convert_unary_cuda; default: diff --git a/ggml/src/ggml-cuda/convert.cuh b/ggml/src/ggml-cuda/convert.cuh index f04214be17..c62e8a1b10 100644 --- a/ggml/src/ggml-cuda/convert.cuh +++ b/ggml/src/ggml-cuda/convert.cuh @@ -29,3 +29,16 @@ typedef to_t_nc_cuda_t to_bf16_nc_cuda_t; to_fp32_nc_cuda_t ggml_get_to_fp32_nc_cuda(ggml_type type); to_fp16_nc_cuda_t ggml_get_to_fp16_nc_cuda(ggml_type type); to_bf16_nc_cuda_t ggml_get_to_bf16_nc_cuda(ggml_type type); + +template + __host__ __device__ inline dst_t ggml_cuda_cast(src_t x) { + if constexpr (std::is_same_v) { + return x; + } else if constexpr(std::is_same_v) { + return __float2bfloat16(float(x)); + } else if constexpr(std::is_same_v) { + return __bfloat162float(x); + } else { + return float(x); + } +} diff --git a/ggml/src/ggml-cuda/cpy-utils.cuh b/ggml/src/ggml-cuda/cpy-utils.cuh index e7a0bd2f1a..e621cb9811 100644 --- a/ggml/src/ggml-cuda/cpy-utils.cuh +++ b/ggml/src/ggml-cuda/cpy-utils.cuh @@ -1,26 +1,7 @@ #pragma once #include "ggml-common.h" - -static __device__ __forceinline__ void convert_f32_f32(const float * src, float * dst) { - *dst = *src; -} - -static __device__ __forceinline__ void convert_f32_f16(const float * src, half * dst) { - *dst = __float2half(*src); -} - -static __device__ __forceinline__ void convert_f32_bf16(const float * src, nv_bfloat16 * dst) { - *dst = *src; -} - -static __device__ __forceinline__ void convert_f16_f16(const half * src, half * dst) { - *dst = *src; -} - -static __device__ __forceinline__ void convert_f16_f32(const half * src, float * dst) { - *dst = *src; -} +#include "convert.cuh" static __device__ __forceinline__ int best_index_int8(int n, const int8_t * val, float x) { if (x <= val[0]) return 0; @@ -230,22 +211,7 @@ static __device__ void cpy_blck_f32_iq4_nl(const char * cxi, char * cdsti) { quantize_f32_iq4_nl_block((const float *)cxi, (block_iq4_nl *)cdsti); } -static __device__ void cpy_1_f32_f32(const char * cxi, char * cdsti) { - convert_f32_f32((const float *)cxi, (float *)cdsti); -} - -static __device__ void cpy_1_f32_f16(const char * cxi, char * cdsti) { - convert_f32_f16((const float *)cxi, (half *)cdsti); -} - -static __device__ void cpy_1_f32_bf16(const char * cxi, char * cdsti) { - convert_f32_bf16((const float *)cxi, (nv_bfloat16 *)cdsti); -} - -static __device__ void cpy_1_f16_f16(const char * cxi, char * cdsti) { - convert_f16_f16((const half *)cxi, (half *)cdsti); -} - -static __device__ void cpy_1_f16_f32(const char * cxi, char * cdsti) { - convert_f16_f32((const half *)cxi, (float *)cdsti); +template +static __device__ void cpy_1_flt(const char * cxi, char * cdsti) { + *(dst_t *) cdsti = ggml_cuda_cast(*(const src_t *) cxi); } diff --git a/ggml/src/ggml-cuda/cpy.cu b/ggml/src/ggml-cuda/cpy.cu index e7d0da0870..f9bb025643 100644 --- a/ggml/src/ggml-cuda/cpy.cu +++ b/ggml/src/ggml-cuda/cpy.cu @@ -1,17 +1,17 @@ #include "cpy.cuh" #include "dequantize.cuh" #include "cpy-utils.cuh" -#ifdef GGML_USE_MUSA +#if defined(GGML_USE_MUSA) && defined(GGML_MUSA_MUDNN_COPY) #include "ggml-musa/mudnn.cuh" -#endif // GGML_USE_MUSA +#endif // GGML_USE_MUSA && GGML_MUSA_MUDNN_COPY typedef void (*cpy_kernel_t)(const char * cx, char * cdst); template -static __global__ void cpy_f32_f16(const char * cx, char * cdst_direct, const int ne, - const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, - const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, - const int nb12, const int nb13, char ** cdst_indirect, int graph_cpynode_index) { +static __global__ void cpy_flt(const char * cx, char * cdst_direct, const int ne, + const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, + const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, + const int nb12, const int nb13, char ** cdst_indirect, int graph_cpynode_index) { const int64_t i = blockDim.x*blockIdx.x + threadIdx.x; if (i >= ne) { @@ -121,7 +121,7 @@ static __global__ void cpy_q_f32(const char * cx, char * cdst_direct, const int // Copy destination pointers to GPU to be available when pointer indirection is in use void ggml_cuda_cpy_dest_ptrs_copy(ggml_cuda_graph * cuda_graph, char ** host_dest_ptrs, const int host_dest_ptrs_size, cudaStream_t stream) { -#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) +#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) || defined(GGML_MUSA_GRAPHS) if (cuda_graph->dest_ptrs_size < host_dest_ptrs_size) { // (re-)allocate GPU memory for destination pointers CUDA_CHECK(cudaStreamSynchronize(stream)); if (cuda_graph->dest_ptrs_d != nullptr) { @@ -139,43 +139,14 @@ void ggml_cuda_cpy_dest_ptrs_copy(ggml_cuda_graph * cuda_graph, char ** host_des #endif } -static void ggml_cpy_f16_f32_cuda( +template +static void ggml_cpy_flt_cuda( const char * cx, char * cdst, const int ne, const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, cudaStream_t stream, char ** cdst_indirect, int & graph_cpynode_index) { const int num_blocks = (ne + CUDA_CPY_BLOCK_SIZE - 1) / CUDA_CPY_BLOCK_SIZE; - cpy_f32_f16<<>> - (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); -} - -static void ggml_cpy_f32_f32_cuda( - const char * cx, char * cdst, const int ne, - const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, - const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, cudaStream_t stream, char ** cdst_indirect, int & graph_cpynode_index) { - - const int num_blocks = (ne + CUDA_CPY_BLOCK_SIZE - 1) / CUDA_CPY_BLOCK_SIZE; - cpy_f32_f16<<>> - (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); -} - -static void ggml_cpy_f32_bf16_cuda( - const char * cx, char * cdst, const int ne, - const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, - const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, cudaStream_t stream, char ** cdst_indirect, int & graph_cpynode_index) { - - const int num_blocks = (ne + CUDA_CPY_BLOCK_SIZE - 1) / CUDA_CPY_BLOCK_SIZE; - cpy_f32_f16<<>> - (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); -} - -static void ggml_cpy_f32_f16_cuda( - const char * cx, char * cdst, const int ne, - const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, - const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, cudaStream_t stream, char ** cdst_indirect, int & graph_cpynode_index) { - - const int num_blocks = (ne + CUDA_CPY_BLOCK_SIZE - 1) / CUDA_CPY_BLOCK_SIZE; - cpy_f32_f16<<>> + cpy_flt><<>> (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); } @@ -307,16 +278,6 @@ static void ggml_cpy_f32_iq4_nl_cuda( (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); } -static void ggml_cpy_f16_f16_cuda( - const char * cx, char * cdst, const int ne, - const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, - const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, cudaStream_t stream, char ** cdst_indirect, int & graph_cpynode_index) { - - const int num_blocks = (ne + CUDA_CPY_BLOCK_SIZE - 1) / CUDA_CPY_BLOCK_SIZE; - cpy_f32_f16<<>> - (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); -} - void ggml_cuda_cpy(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, ggml_tensor * src1, bool disable_indirection_for_this_node) { const int64_t ne = ggml_nelements(src0); GGML_ASSERT(ne == ggml_nelements(src1)); @@ -353,7 +314,7 @@ void ggml_cuda_cpy(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, gg char ** dest_ptrs_d = nullptr; int graph_cpynode_index = -1; -#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) +#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) || defined(GGML_MUSA_GRAPHS) if(ctx.cuda_graph->use_cpy_indirection && !disable_indirection_for_this_node) { dest_ptrs_d = ctx.cuda_graph->dest_ptrs_d; graph_cpynode_index = ctx.cuda_graph->graph_cpynode_index; @@ -363,20 +324,20 @@ void ggml_cuda_cpy(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, gg #endif if (src0->type == src1->type && ggml_is_contiguous(src0) && ggml_is_contiguous(src1)) { GGML_ASSERT(ggml_nbytes(src0) == ggml_nbytes(src1)); -#ifdef GGML_USE_MUSA +#if defined(GGML_USE_MUSA) && defined(GGML_MUSA_MUDNN_COPY) if (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16) { CUDA_CHECK(mudnnMemcpyAsync(ctx, src1, src0)); } else -#endif // GGML_USE_MUSA +#endif // GGML_USE_MUSA && GGML_MUSA_MUDNN_COPY { CUDA_CHECK(cudaMemcpyAsync(src1_ddc, src0_ddc, ggml_nbytes(src0), cudaMemcpyDeviceToDevice, main_stream)); } } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32) { - ggml_cpy_f32_f32_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_BF16) { - ggml_cpy_f32_bf16_cuda(src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F16) { - ggml_cpy_f32_f16_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_Q8_0) { ggml_cpy_f32_q8_0_cuda(src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_Q8_0 && src1->type == GGML_TYPE_F32) { @@ -403,14 +364,22 @@ void ggml_cuda_cpy(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, gg } else if (src0->type == GGML_TYPE_Q5_1 && src1->type == GGML_TYPE_F32) { ggml_cpy_q5_1_f32_cuda(src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F16) { - ggml_cpy_f16_f16_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_BF16) { + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F32) { - ggml_cpy_f16_f32_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_BF16) { + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_F16) { + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_F32) { + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else { GGML_ABORT("%s: unsupported type combination (%s to %s)\n", __func__, ggml_type_name(src0->type), ggml_type_name(src1->type)); } -#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) +#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) || defined(GGML_MUSA_GRAPHS) if(ctx.cuda_graph->use_cpy_indirection && !disable_indirection_for_this_node) { ctx.cuda_graph->graph_cpynode_index = graph_cpynode_index; } @@ -430,11 +399,11 @@ void* ggml_cuda_cpy_fn(const ggml_tensor * src0, ggml_tensor * src1) { if (src0->type == src1->type && ggml_is_contiguous(src0) && ggml_is_contiguous(src1)) { return nullptr; } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32) { - return (void*) cpy_f32_f16; + return (void*) cpy_flt>; } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_BF16) { - return (void*) cpy_f32_f16; + return (void*) cpy_flt>; } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F16) { - return (void*) cpy_f32_f16; + return (void*) cpy_flt>; } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_Q8_0) { return (void*) cpy_f32_q; } else if (src0->type == GGML_TYPE_Q8_0 && src1->type == GGML_TYPE_F32) { @@ -458,9 +427,17 @@ void* ggml_cuda_cpy_fn(const ggml_tensor * src0, ggml_tensor * src1) { } else if (src0->type == GGML_TYPE_Q5_1 && src1->type == GGML_TYPE_F32) { return (void*) cpy_q_f32, QK5_1>; } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F16) { - return (void*) cpy_f32_f16; + return (void*) cpy_flt>; + } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_BF16) { + return (void*) cpy_flt>; } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F32) { - return (void*) cpy_f32_f16; + return (void*) cpy_flt>; + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_F16) { + return (void*) cpy_flt>; + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_BF16) { + return (void*) cpy_flt>; + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_F32) { + return (void*) cpy_flt>; } else { GGML_ABORT("%s: unsupported type combination (%s to %s)\n", __func__, ggml_type_name(src0->type), ggml_type_name(src1->type)); diff --git a/ggml/src/ggml-cuda/fattn-common.cuh b/ggml/src/ggml-cuda/fattn-common.cuh index 9122fca6cf..e46f0e2081 100644 --- a/ggml/src/ggml-cuda/fattn-common.cuh +++ b/ggml/src/ggml-cuda/fattn-common.cuh @@ -15,6 +15,8 @@ typedef void (* fattn_kernel_t)( const char * __restrict__ K, const char * __restrict__ V, const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, float * __restrict__ dst, float2 * __restrict__ dst_meta, const float scale, @@ -23,33 +25,13 @@ typedef void (* fattn_kernel_t)( const float m1, const uint32_t n_head_log2, const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int ne33, - const int nb31, - const int nb32, - const int nb33, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3); + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33); typedef half (*vec_dot_KQ_f16_t)( const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8 , const void * __restrict__ Q_ds); @@ -520,6 +502,55 @@ constexpr __device__ dequantize_1_f32_t get_dequantize_1_f32(ggml_type type_V) { nullptr; } +template +__launch_bounds__(FATTN_KQ_STRIDE/2, 1) +static __global__ void flash_attn_mask_to_KV_max( + const half2 * __restrict__ mask, int * __restrict__ KV_max, const int ne30, const int s31, const int s33) { + const int ne31 = gridDim.x; + const int tid = threadIdx.x; + const int sequence = blockIdx.y; + const int jt = blockIdx.x; + + mask += sequence*s33 + jt*ncols1*s31; + + __shared__ int buf_iw[WARP_SIZE]; + if (tid < WARP_SIZE) { + buf_iw[tid] = 1; + } + __syncthreads(); + + int KV_max_sj = (ne30 - 1) * FATTN_KQ_STRIDE; + for (; KV_max_sj >= 0; KV_max_sj -= FATTN_KQ_STRIDE) { + int all_inf = 1; + +#pragma unroll + for (int j = 0; j < ncols1; ++j) { + const float2 tmp = __half22float2(mask[j*s31 + KV_max_sj/2 + tid]); + all_inf = all_inf && int(isinf(tmp.x)) && int(isinf(tmp.y)); + } + + all_inf = warp_reduce_all(all_inf); + if (tid % WARP_SIZE == 0) { + buf_iw[tid / WARP_SIZE] = all_inf; + } + __syncthreads(); + all_inf = buf_iw[tid % WARP_SIZE]; + __syncthreads(); + all_inf = warp_reduce_all(all_inf); + + if (!all_inf) { + KV_max_sj += FATTN_KQ_STRIDE; + break; + } + } + + if (threadIdx.x != 0) { + return; + } + + KV_max[sequence*ne31 + jt] = KV_max_sj; +} + template // D == head size __launch_bounds__(D, 1) static __global__ void flash_attn_stream_k_fixup( @@ -612,9 +643,9 @@ static __global__ void flash_attn_stream_k_fixup( } template // D == head size -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#if !defined(GGML_USE_HIP) __launch_bounds__(D, 1) -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#endif // !(defined(GGML_USE_HIP) static __global__ void flash_attn_combine_results( const float * __restrict__ VKQ_parts, const float2 * __restrict__ VKQ_meta, @@ -706,7 +737,8 @@ void launch_fattn( GGML_ASSERT(V || is_mla); - const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * sinks = dst->src[4]; ggml_tensor * KQV = dst; @@ -731,6 +763,7 @@ void launch_fattn( ggml_cuda_pool_alloc K_f16(pool); ggml_cuda_pool_alloc V_f16(pool); + ggml_cuda_pool_alloc KV_max(pool); ggml_cuda_pool_alloc dst_tmp(pool); ggml_cuda_pool_alloc dst_tmp_meta(pool); @@ -745,40 +778,84 @@ void launch_fattn( size_t nb23 = V ? V->nb[3] : nb13; if (need_f16_K && K->type != GGML_TYPE_F16) { - GGML_ASSERT(ggml_is_contiguously_allocated(K)); - K_f16.alloc(ggml_nelements(K)); - to_fp16_cuda_t to_fp16 = ggml_get_to_fp16_cuda(K->type); - to_fp16(K_data, K_f16.ptr, ggml_nelements(K), main_stream); - K_data = (char *) K_f16.ptr; - const size_t bs = ggml_blck_size(K->type); const size_t ts = ggml_type_size(K->type); - nb11 = nb11*bs*sizeof(half)/ts; - nb12 = nb12*bs*sizeof(half)/ts; - nb13 = nb13*bs*sizeof(half)/ts; + K_f16.alloc(ggml_nelements(K)); + if (ggml_is_contiguously_allocated(K)) { + to_fp16_cuda_t to_fp16 = ggml_get_to_fp16_cuda(K->type); + to_fp16(K_data, K_f16.ptr, ggml_nelements(K), main_stream); + + nb11 = nb11*bs*sizeof(half)/ts; + nb12 = nb12*bs*sizeof(half)/ts; + nb13 = nb13*bs*sizeof(half)/ts; + } else { + GGML_ASSERT(K->nb[0] == ts); + to_fp16_nc_cuda_t to_fp16 = ggml_get_to_fp16_nc_cuda(K->type); + const int64_t s01 = nb11 / ts; + const int64_t s02 = nb12 / ts; + const int64_t s03 = nb13 / ts; + to_fp16(K_data, K_f16.ptr, K->ne[0], K->ne[1], K->ne[2], K->ne[3], s01, s02, s03, main_stream); + + nb11 = K->ne[0] * sizeof(half); + nb12 = K->ne[1] * nb11; + nb13 = K->ne[2] * nb12; + } + K_data = (char *) K_f16.ptr; } if (V && need_f16_V && V->type != GGML_TYPE_F16) { - GGML_ASSERT(ggml_is_contiguously_allocated(V)); - V_f16.alloc(ggml_nelements(V)); - to_fp16_cuda_t to_fp16 = ggml_get_to_fp16_cuda(V->type); - to_fp16(V_data, V_f16.ptr, ggml_nelements(V), main_stream); - V_data = (char *) V_f16.ptr; - const size_t bs = ggml_blck_size(V->type); const size_t ts = ggml_type_size(V->type); - nb21 = nb21*bs*sizeof(half)/ts; - nb22 = nb22*bs*sizeof(half)/ts; - nb23 = nb23*bs*sizeof(half)/ts; - } + V_f16.alloc(ggml_nelements(V)); + if (ggml_is_contiguously_allocated(V)) { + to_fp16_cuda_t to_fp16 = ggml_get_to_fp16_cuda(V->type); + to_fp16(V_data, V_f16.ptr, ggml_nelements(V), main_stream); + V_data = (char *) V_f16.ptr; - int parallel_blocks = 1; + nb21 = nb21*bs*sizeof(half)/ts; + nb22 = nb22*bs*sizeof(half)/ts; + nb23 = nb23*bs*sizeof(half)/ts; + } else { + GGML_ASSERT(V->nb[0] == ts); + to_fp16_nc_cuda_t to_fp16 = ggml_get_to_fp16_nc_cuda(V->type); + const int64_t s01 = nb21 / ts; + const int64_t s02 = nb22 / ts; + const int64_t s03 = nb23 / ts; + to_fp16(V_data, V_f16.ptr, V->ne[0], V->ne[1], V->ne[2], V->ne[3], s01, s02, s03, main_stream); + + nb21 = V->ne[0] * sizeof(half); + nb22 = V->ne[1] * nb21; + nb23 = V->ne[2] * nb22; + } + V_data = (char *) V_f16.ptr; + } const int ntiles_x = ((Q->ne[1] + ncols1 - 1) / ncols1); const int ntiles_total = ntiles_x * (Q->ne[2] / ncols2) * Q->ne[3]; + // Optional optimization where the mask is scanned to determine whether part of the calculation can be skipped. + // Only worth the overhead if there is at lease one FATTN_KQ_STRIDE x FATTN_KQ_STRIDE square to be skipped or + // multiple sequences of possibly different lengths. + if (mask && (Q->ne[1] >= 1024 || Q->ne[3] > 1)) { + const int s31 = mask->nb[1] / sizeof(half2); + const int s33 = mask->nb[3] / sizeof(half2); + + const dim3 blocks_num_KV_max(ntiles_x, Q->ne[3], 1); + const dim3 block_dim_KV_max(FATTN_KQ_STRIDE/2, 1, 1); + + const int ne_KV_max = blocks_num_KV_max.x*blocks_num_KV_max.y; + const int iter_k = K->ne[1] / FATTN_KQ_STRIDE; + + KV_max.alloc(ne_KV_max); + flash_attn_mask_to_KV_max<<>> + ((const half2 *) mask->data, KV_max.ptr, iter_k, s31, s33); + CUDA_CHECK(cudaGetLastError()); + } + + int parallel_blocks = 1; + const dim3 block_dim(warp_size, nwarps, 1); int max_blocks_per_sm = 1; // Max. number of active blocks limited by occupancy. CUDA_CHECK(cudaOccupancyMaxActiveBlocksPerMultiprocessor(&max_blocks_per_sm, fattn_kernel, block_dim.x * block_dim.y * block_dim.z, nbytes_shared)); @@ -865,16 +942,15 @@ void launch_fattn( K_data, V_data, mask ? ((const char *) mask->data) : nullptr, + sinks ? ((const char *) sinks->data) : nullptr, + KV_max.ptr, !stream_k && parallel_blocks > 1 ? dst_tmp.ptr : (float *) KQV->data, dst_tmp_meta.ptr, scale, max_bias, m0, m1, n_head_log2, logit_softcap, - Q->ne[0], Q->ne[1], Q->ne[2], Q->ne[3], - K->ne[0], K->ne[1], K->ne[2], K->ne[3], - mask ? mask->ne[1] : 0, mask ? mask->ne[2] : 0, mask ? mask->ne[3] : 0, - mask ? mask->nb[1] : 0, mask ? mask->nb[2] : 0, mask ? mask->nb[3] : 0, - Q->nb[1], Q->nb[2], Q->nb[3], - nb11, nb12, nb13, + Q->ne[0], Q->ne[1], Q->ne[2], Q->ne[3], Q->nb[1], Q->nb[2], Q->nb[3], + K->ne[0], K->ne[1], K->ne[2], K->ne[3], nb11, nb12, nb13, nb21, nb22, nb23, - KQV->ne[0], KQV->ne[1], KQV->ne[2], KQV->ne[3] + mask ? mask->ne[1] : 0, mask ? mask->ne[2] : 0, mask ? mask->ne[3] : 0, + mask ? mask->nb[1] : 0, mask ? mask->nb[2] : 0, mask ? mask->nb[3] : 0 ); CUDA_CHECK(cudaGetLastError()); diff --git a/ggml/src/ggml-cuda/fattn-mma-f16.cuh b/ggml/src/ggml-cuda/fattn-mma-f16.cuh index 6fa2e77299..39731baaeb 100644 --- a/ggml/src/ggml-cuda/fattn-mma-f16.cuh +++ b/ggml/src/ggml-cuda/fattn-mma-f16.cuh @@ -392,7 +392,8 @@ static __device__ __forceinline__ void flash_attn_ext_f16_load_mask( } } -template +template static __device__ __forceinline__ void flash_attn_ext_f16_iter( const float2 * const __restrict__ Q_f2, const half2 * const __restrict__ K_h2, @@ -408,7 +409,6 @@ static __device__ __forceinline__ void flash_attn_ext_f16_iter( const int stride_K, const int stride_V, const int stride_mask, - const int jt, half2 * const __restrict__ tile_Q, half2 * const __restrict__ tile_K, half2 * const __restrict__ tile_V, @@ -418,7 +418,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_iter( float * const __restrict__ KQ_max, float * const __restrict__ KQ_rowsum, const int kb0) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE typedef fattn_mma_f16_config c; #ifdef CP_ASYNC_AVAILABLE @@ -455,7 +455,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_iter( cp_async_wait_all(); __syncthreads(); flash_attn_ext_f16_load_tile - (V_h2 + k_VKQ_0*stride_V, tile_V, nbatch_V2, stride_V); + (V_h2 + int64_t(k_VKQ_0)*stride_V, tile_V, nbatch_V2, stride_V); } else { constexpr bool use_cp_async = nstages == 1; if (ncols2 > 1 || mask_h2) { @@ -471,7 +471,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_iter( if (nstages <= 1) { constexpr bool use_cp_async = nstages == 1; flash_attn_ext_f16_load_tile - (K_h2 + k_VKQ_0*stride_K + k0_start, tile_K, k0_diff, stride_K); + (K_h2 + int64_t(k_VKQ_0)*stride_K + k0_start, tile_K, k0_diff, stride_K); if (use_cp_async) { cp_async_wait_all(); } @@ -715,7 +715,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_iter( (mask_h2 + (k_VKQ_0 + c::nbatch_fa)/2, tile_mask, stride_mask); } flash_attn_ext_f16_load_tile - (K_h2 + (k_VKQ_0 + c::nbatch_fa)*stride_K, tile_K, nbatch_K2, stride_K); + (K_h2 + int64_t(k_VKQ_0 + c::nbatch_fa)*stride_K, tile_K, nbatch_K2, stride_K); } } @@ -732,7 +732,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_iter( if (nstages <= 1 && i0_start < reusable_cutoff) { constexpr bool use_cp_async = nstages == 1; flash_attn_ext_f16_load_tile - (V_h2 + k_VKQ_0*stride_V + i0_start/2, tile_V, i0_diff/2, stride_V); + (V_h2 + int64_t(k_VKQ_0)*stride_V + i0_start/2, tile_V, i0_diff/2, stride_V); if (use_cp_async) { cp_async_wait_all(); } @@ -771,13 +771,12 @@ static __device__ __forceinline__ void flash_attn_ext_f16_iter( GGML_UNUSED(mask_h2); GGML_UNUSED(dstk); GGML_UNUSED(dstk_fixup); GGML_UNUSED(scale); GGML_UNUSED(slope); GGML_UNUSED(logit_softcap); GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(stride_K); GGML_UNUSED(stride_V); - GGML_UNUSED(stride_mask); GGML_UNUSED(jt); GGML_UNUSED(tile_K); - GGML_UNUSED(stride_mask); GGML_UNUSED(jt); GGML_UNUSED(tile_K); + GGML_UNUSED(stride_mask); GGML_UNUSED(tile_K); GGML_UNUSED(tile_V); GGML_UNUSED(tile_mask); GGML_UNUSED(Q_B); GGML_UNUSED(VKQ_C); GGML_UNUSED(KQ_max); GGML_UNUSED(KQ_rowsum); GGML_UNUSED(kb0); GGML_UNUSED(tile_Q); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } template @@ -786,6 +785,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_process_tile( const half2 * const __restrict__ K_h2, const half2 * const __restrict__ V_h2, const half2 * const __restrict__ mask_h2, + const float * const __restrict__ sinks_f, float2 * const __restrict__ dstk, float2 * const __restrict__ dstk_fixup, const float scale, @@ -801,7 +801,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_process_tile( const int jt, const int kb0_start, const int kb0_stop) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE //In this kernel Q, K, V are matrices while i, j, k are matrix indices. typedef fattn_mma_f16_config c; @@ -920,21 +920,22 @@ static __device__ __forceinline__ void flash_attn_ext_f16_process_tile( (mask_h2 + kb0_start*c::nbatch_fa/2, tile_mask, stride_mask); } flash_attn_ext_f16_load_tile - (K_h2 + kb0_start*c::nbatch_fa*stride_K, tile_K, nbatch_K2, stride_K); + (K_h2 + int64_t(kb0_start)*c::nbatch_fa*stride_K, tile_K, nbatch_K2, stride_K); } // Iterate over ne11 == previous tokens: - for (int kb0 = kb0_start; kb0 < kb0_stop-1; ++kb0) { + int kb0 = kb0_start; + for (; kb0 < kb0_stop-1; ++kb0) { constexpr bool last_iter = false; flash_attn_ext_f16_iter (Q_f2, K_h2, V_h2, mask_h2, dstk, dstk_fixup, scale, slope, logit_softcap, - ne01, ne02, stride_K, stride_V, stride_mask, jt, tile_Q, tile_K, tile_V, tile_mask, Q_B, VKQ_C, KQ_max, KQ_rowsum, kb0); + ne01, ne02, stride_K, stride_V, stride_mask, tile_Q, tile_K, tile_V, tile_mask, Q_B, VKQ_C, KQ_max, KQ_rowsum, kb0); } { // kb0_start is always < kb0_stop so the last iter can be executed unconditionally. constexpr bool last_iter = true; flash_attn_ext_f16_iter (Q_f2, K_h2, V_h2, mask_h2, dstk, dstk_fixup, scale, slope, logit_softcap, - ne01, ne02, stride_K, stride_V, stride_mask, jt, tile_Q, tile_K, tile_V, tile_mask, Q_B, VKQ_C, KQ_max, KQ_rowsum, kb0_stop-1); + ne01, ne02, stride_K, stride_V, stride_mask, tile_Q, tile_K, tile_V, tile_mask, Q_B, VKQ_C, KQ_max, KQ_rowsum, kb0); } // With multi-stage loading there is no __syncthreads at the end of the iter, @@ -957,6 +958,52 @@ static __device__ __forceinline__ void flash_attn_ext_f16_process_tile( } } + // If attention sinks are used, potentially re-scale if KQ_max is small. + // Also add the sink as a value to KQ_rowsum, this is done after synchonization of KQ_rowsum + // so it's being done unconditionally for every thread. + if (!is_fixup && (np == 1 || threadIdx.y % np == 0) && sinks_f) { + float KQ_max_scale[cols_per_thread]; +#pragma unroll + for (int col = 0; col < cols_per_thread; ++col) { + static_assert(ntiles == 1 || ntiles == 2, "ntiles > 2 not implemented"); + const int jc = ntiles == 1 ? 2*tile_C_VKQ::get_j(col/2) + col % 2 : tile_C_VKQ_16::get_i(col); + const float sink = sinks_f[jc % ncols2]; + + const float KQ_max_new = fmaxf(KQ_max[col], sink); + const float KQ_max_diff = KQ_max[col] - KQ_max_new; + KQ_max_scale[col] = expf(KQ_max_diff); + KQ_max[col] = KQ_max_new; + + *((uint32_t *) &KQ_max_scale[col]) *= KQ_max_diff >= SOFTMAX_FTZ_THRESHOLD; + + const float KQ_max_add = expf(sink - KQ_max_new); + KQ_rowsum[col] = KQ_max_scale[col]*KQ_rowsum[col] + KQ_max_add; + } + + if (ntiles == 1) { + const half2 KQ_max_scale_h2 = make_half2(KQ_max_scale[0], KQ_max_scale[1]); +#pragma unroll + for (int i = 0; i < DV/tile_C_VKQ::I; ++i) { +#pragma unroll + for (int l = 0; l < tile_C_VKQ::ne; ++l) { + VKQ_C[i].x[l] *= KQ_max_scale_h2; + } + } + } else { +#pragma unroll + for (int col = 0; col < cols_per_thread; ++col) { + const half2 KQ_max_scale_h2 = make_half2(KQ_max_scale[col], KQ_max_scale[col]); +#pragma unroll + for (int i = 0; i < DV/tile_C_VKQ_16::J; ++i) { +#pragma unroll + for (int l0 = 0; l0 < tile_C_VKQ_16::ne; l0 += 2) { + VKQ_C_16[i*ntiles/2 + col/2].x[l0 + col % 2] *= KQ_max_scale_h2; + } + } + } + } + } + // Combine VKQ accumulator values if np > 1. // It's also faster to do small writes to shared memory, then large write to VRAM than to do small writes to VRAM. // So also write VKQ accumulators to shared memory in column-major format if np == 1. @@ -1196,7 +1243,7 @@ static __device__ __forceinline__ void flash_attn_ext_f16_process_tile( GGML_UNUSED(stride_Q2); GGML_UNUSED(stride_K); GGML_UNUSED(stride_V); GGML_UNUSED(stride_mask); GGML_UNUSED(jt); GGML_UNUSED(kb0_start); GGML_UNUSED(kb0_stop); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } template @@ -1206,6 +1253,8 @@ static __global__ void flash_attn_ext_f16( const char * __restrict__ K, const char * __restrict__ V, const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, float * __restrict__ dst, float2 * __restrict__ dst_meta, const float scale, @@ -1214,34 +1263,14 @@ static __global__ void flash_attn_ext_f16( const float m1, const uint32_t n_head_log2, const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int ne33, - const int nb31, - const int nb32, - const int nb33, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { -#if defined(FLASH_ATTN_AVAILABLE) && defined(NEW_MMA_AVAILABLE) + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33) { +#if defined(FLASH_ATTN_AVAILABLE) && defined(TURING_MMA_AVAILABLE) // Skip unused kernel variants for faster compilation: if (use_logit_softcap && !(DKQ == 128 || DKQ == 256)) { @@ -1286,34 +1315,42 @@ static __global__ void flash_attn_ext_f16( // kb0 == k start index when in the output tile. int kb0_start = kbc % iter_k; int kb0_stop = min(iter_k, kb0_start + kbc_stop - kbc); + while (kbc < kbc_stop && kb0_stop == iter_k) { const int sequence = kbc / (iter_k*iter_j*(ne02/ncols2)); - const int head = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence) / (iter_k*iter_j); - const int jt = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence - iter_k*iter_j*head) / iter_k; // j index of current tile. + const int zt = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence) / (iter_k*iter_j); // head in units of ncols2 + const int jt = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence - iter_k*iter_j*zt) / iter_k; // j index of current tile. - const float2 * Q_f2 = (const float2 *) (Q + nb03*sequence + nb02*(head*ncols2)); - const half2 * K_h2 = (const half2 *) (K + nb13*sequence + nb12*(head*ncols2 / gqa_ratio)); + const int head0 = zt * ncols2; + + const float2 * Q_f2 = (const float2 *) (Q + nb03*sequence + nb02* head0); + const half2 * K_h2 = (const half2 *) (K + nb13*sequence + nb12*(head0 / gqa_ratio)); const half2 * mask_h2 = ncols2 == 1 && !mask ? nullptr : (const half2 *) (mask + nb33*(sequence % ne33) + nb31*jt*ncols1); - float2 * dstk = ((float2 *) dst) + (sequence*ne01*ne02 + head*ncols2) * (DV/2); + float2 * dstk = ((float2 *) dst) + (sequence*ne01*ne02 + head0) * (DV/2); - const half2 * V_h2 = mla ? K_h2 + (DKQ/2 - DV/2) : (const half2 *) (V + nb23*sequence + nb22*(head*ncols2 / gqa_ratio)); + const half2 * V_h2 = mla ? K_h2 + (DKQ/2 - DV/2) : (const half2 *) (V + nb23*sequence + nb22*(head0 / gqa_ratio)); + const float * sinks_f = sinks ? (const float *) sinks + head0 : nullptr; - const float slope = ncols2 == 1 ? get_alibi_slope(max_bias, head, n_head_log2, m0, m1) : 1.0f; + const float slope = ncols2 == 1 ? get_alibi_slope(max_bias, head0, n_head_log2, m0, m1) : 1.0f; const int kb0_start_kernel = kb0_start * kb_niter; - const int kb0_stop_kernel = kb0_stop * kb_niter; + int kb0_stop_kernel = kb0_stop * kb_niter; + + if (KV_max) { + kb0_stop_kernel = min(kb0_stop_kernel, KV_max[sequence*iter_j + jt] / c::nbatch_fa); + } constexpr bool is_fixup = false; // All but (potentially) the last iterations write their data to dst rather than the fixup buffer. if (kb0_start == 0) { constexpr bool needs_fixup = false; // CUDA block is working on an entire tile. flash_attn_ext_f16_process_tile - (Q_f2, K_h2, V_h2, mask_h2, dstk, dst_meta, scale, slope, logit_softcap, + (Q_f2, K_h2, V_h2, mask_h2, sinks_f, dstk, dst_meta, scale, slope, logit_softcap, ne01, ne02, stride_Q1, stride_Q2, stride_K, stride_V, stride_mask, jt, kb0_start_kernel, kb0_stop_kernel); } else { constexpr bool needs_fixup = true; // CUDA block is working on the beginning of a tile. flash_attn_ext_f16_process_tile - (Q_f2, K_h2, V_h2, mask_h2, dstk, dst_meta, scale, slope, logit_softcap, + (Q_f2, K_h2, V_h2, mask_h2, sinks_f, dstk, dst_meta, scale, slope, logit_softcap, ne01, ne02, stride_Q1, stride_Q2, stride_K, stride_V, stride_mask, jt, kb0_start_kernel, kb0_stop_kernel); } @@ -1329,40 +1366,48 @@ static __global__ void flash_attn_ext_f16( } const int sequence = kbc / (iter_k*iter_j*(ne02/ncols2)); - const int head = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence) / (iter_k*iter_j); - const int jt = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence - iter_k*iter_j*head) / iter_k; // j index of current tile. + const int zt = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence) / (iter_k*iter_j); // head in units of ncols2 + const int jt = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence - iter_k*iter_j*zt) / iter_k; // j index of current tile. - const float2 * Q_f2 = (const float2 *) (Q + nb03*sequence + nb02*(head*ncols2)); - const half2 * K_h2 = (const half2 *) (K + nb13*sequence + nb12*(head*ncols2 / gqa_ratio)); + const int head0 = zt * ncols2; + + const float2 * Q_f2 = (const float2 *) (Q + nb03*sequence + nb02* head0); + const half2 * K_h2 = (const half2 *) (K + nb13*sequence + nb12*(head0 / gqa_ratio)); const half2 * mask_h2 = ncols2 == 1 && !mask ? nullptr : (const half2 *) (mask + nb33*(sequence % ne33) + nb31*jt*ncols1); - float2 * dstk = ((float2 *) dst) + (sequence*ne01*ne02 + head*ncols2) * (DV/2); + float2 * dstk = ((float2 *) dst) + (sequence*ne01*ne02 + head0) * (DV/2); - const half2 * V_h2 = mla ? K_h2 + (DKQ/2 - DV/2) : (const half2 *) (V + nb23*sequence + nb22*(head*ncols2 / gqa_ratio)); + const half2 * V_h2 = mla ? K_h2 + (DKQ/2 - DV/2) : (const half2 *) (V + nb23*sequence + nb22*(head0 / gqa_ratio)); + const float * sinks_f = sinks ? (const float *) sinks + head0 : nullptr; - const float slope = ncols2 == 1 ? get_alibi_slope(max_bias, head, n_head_log2, m0, m1) : 1.0f; + const float slope = ncols2 == 1 ? get_alibi_slope(max_bias, head0, n_head_log2, m0, m1) : 1.0f; const int kb0_start_kernel = kb0_start * kb_niter; - const int kb0_stop_kernel = kb0_stop * kb_niter; + int kb0_stop_kernel = kb0_stop * kb_niter; + + if (KV_max) { + kb0_stop_kernel = min(kb0_stop_kernel, KV_max[sequence*iter_j + jt] / c::nbatch_fa); + } constexpr bool is_fixup = true; // Last index writes its data to fixup buffer to avoid data races with other blocks. constexpr bool needs_fixup = false; flash_attn_ext_f16_process_tile - (Q_f2, K_h2, V_h2, mask_h2, dstk, dst_meta, scale, slope, logit_softcap, + (Q_f2, K_h2, V_h2, mask_h2, sinks_f, dstk, dst_meta, scale, slope, logit_softcap, ne01, ne02, stride_Q1, stride_Q2, stride_K, stride_V, stride_mask, jt, kb0_start_kernel, kb0_stop_kernel); #else - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); - GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); GGML_UNUSED(ne00); - GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(ne03); GGML_UNUSED(ne10); - GGML_UNUSED(ne11); GGML_UNUSED(ne12); GGML_UNUSED(ne13); GGML_UNUSED(ne31); GGML_UNUSED(ne32); - GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); - GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); GGML_UNUSED(nb21); - GGML_UNUSED(nb22); GGML_UNUSED(nb23); GGML_UNUSED(ne0); GGML_UNUSED(ne1); - GGML_UNUSED(ne2); GGML_UNUSED(ne3); + GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); GGML_UNUSED(sinks); + GGML_UNUSED(dst); GGML_UNUSED(dst_meta); + GGML_UNUSED(scale); GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); + GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); + GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(ne03); + GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); + GGML_UNUSED(ne10); GGML_UNUSED(ne11); GGML_UNUSED(ne12); GGML_UNUSED(ne13); + GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); + GGML_UNUSED(nb21); GGML_UNUSED(nb22); GGML_UNUSED(nb23); + GGML_UNUSED(ne31); GGML_UNUSED(ne32); GGML_UNUSED(ne33); + GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb33); NO_DEVICE_CODE; -#endif // defined(FLASH_ATTN_AVAILABLE) && defined(NEW_MMA_AVAILABLE) +#endif // defined(FLASH_ATTN_AVAILABLE) && defined(TURING_MMA_AVAILABLE) } template @@ -1412,24 +1457,24 @@ void ggml_cuda_flash_attn_ext_mma_f16_case(ggml_backend_cuda_context & ctx, ggml constexpr bool use_logit_softcap = false; fattn_kernel = flash_attn_ext_f16; -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) static bool shared_memory_limit_raised[GGML_CUDA_MAX_DEVICES] = {false}; if (!shared_memory_limit_raised[id]) { CUDA_CHECK(cudaFuncSetAttribute(fattn_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, nbytes_shared_total)); shared_memory_limit_raised[id] = true; } -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) } else { constexpr bool use_logit_softcap = true; fattn_kernel = flash_attn_ext_f16; -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) static bool shared_memory_limit_raised[GGML_CUDA_MAX_DEVICES] = {false}; if (!shared_memory_limit_raised[id]) { CUDA_CHECK(cudaFuncSetAttribute(fattn_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, nbytes_shared_total)); shared_memory_limit_raised[id] = true; } -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) } launch_fattn diff --git a/ggml/src/ggml-cuda/fattn-tile-f16.cu b/ggml/src/ggml-cuda/fattn-tile-f16.cu index 1f14132884..1e23f8f79c 100644 --- a/ggml/src/ggml-cuda/fattn-tile-f16.cu +++ b/ggml/src/ggml-cuda/fattn-tile-f16.cu @@ -5,14 +5,16 @@ #define FATTN_KQ_STRIDE_TILE_F16 64 template // D == head size -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#if !defined(GGML_USE_HIP) __launch_bounds__(nwarps*WARP_SIZE, 2) -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#endif // !defined(GGML_USE_HIP) static __global__ void flash_attn_tile_ext_f16( const char * __restrict__ Q, const char * __restrict__ K, const char * __restrict__ V, const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, float * __restrict__ dst, float2 * __restrict__ dst_meta, const float scale, @@ -21,33 +23,13 @@ static __global__ void flash_attn_tile_ext_f16( const float m1, const uint32_t n_head_log2, const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int ne33, - const int nb31, - const int nb32, - const int nb33, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33) { #if defined(FLASH_ATTN_AVAILABLE) && defined(FP16_AVAILABLE) // Skip unused kernel variants for faster compilation: @@ -67,10 +49,11 @@ static __global__ void flash_attn_tile_ext_f16( const int sequence = blockIdx.z / ne02; const int head = blockIdx.z - sequence*ne02; const int gqa_ratio = ne02 / ne12; // With grouped query attention there are > 1 Q matrices per K, V matrix. - const float2 * Q_f2 = (const float2 *) (Q + nb03* sequence + nb02* head + nb01*ic0); - const half2 * K_h2 = (const half2 *) (K + nb13* sequence + nb12*(head / gqa_ratio)); - const half2 * V_h2 = (const half2 *) (V + nb13* sequence + nb12*(head / gqa_ratio)); // K and V have same shape - const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + const float2 * Q_f2 = (const float2 *) (Q + nb03* sequence + nb02* head + nb01*ic0); + const half2 * K_h2 = (const half2 *) (K + nb13* sequence + nb12*(head / gqa_ratio)); + const half2 * V_h2 = (const half2 *) (V + nb13* sequence + nb12*(head / gqa_ratio)); // K and V have same shape + const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + const float * sinksf = (const float *) (sinks); const int stride_KV2 = nb11 / sizeof(half2); @@ -110,7 +93,8 @@ static __global__ void flash_attn_tile_ext_f16( __syncthreads(); - for (int k_VKQ_0 = blockIdx.y*FATTN_KQ_STRIDE_TILE_F16; k_VKQ_0 < ne11; k_VKQ_0 += gridDim.y*FATTN_KQ_STRIDE_TILE_F16) { + const int k_VKQ_max = KV_max ? KV_max[sequence*gridDim.x + blockIdx.x] : ne11; + for (int k_VKQ_0 = blockIdx.y*FATTN_KQ_STRIDE_TILE_F16; k_VKQ_0 < k_VKQ_max; k_VKQ_0 += gridDim.y*FATTN_KQ_STRIDE_TILE_F16) { // Calculate KQ tile and keep track of new maximum KQ values: half kqmax_new[ncols/nwarps]; @@ -127,7 +111,7 @@ static __global__ void flash_attn_tile_ext_f16( for (int k_KQ_0 = 0; k_KQ_0 < D/2; k_KQ_0 += WARP_SIZE) { const int k_KQ = k_KQ_0 + threadIdx.x; - KV_tmp[i_KQ][k_KQ] = K_h2[(k_VKQ_0 + i_KQ)*stride_KV2 + k_KQ]; + KV_tmp[i_KQ][k_KQ] = K_h2[int64_t(k_VKQ_0 + i_KQ)*stride_KV2 + k_KQ]; } } @@ -221,7 +205,7 @@ static __global__ void flash_attn_tile_ext_f16( for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { const int i = i0 + threadIdx.x; - KV_tmp[k][i] = V_h2[(k_VKQ_0 + k)*stride_KV2 + i]; + KV_tmp[k][i] = V_h2[int64_t(k_VKQ_0 + k)*stride_KV2 + i]; } } @@ -259,6 +243,31 @@ static __global__ void flash_attn_tile_ext_f16( __syncthreads(); } + //Attention sink: adjust running max and sum once per head + if (sinksf && blockIdx.y == 0) { + const half sink = __float2half(sinksf[head]); + +#pragma unroll + for (int j0 = 0; j0 < ncols; j0 += nwarps) { + half kqmax_new_j = fmaxf(kqmax[j0/nwarps], sink); + kqmax_new_j = warp_reduce_max(kqmax_new_j); + + const half2 KQ_max_scale = __half2half2(hexp(kqmax[j0/nwarps] - kqmax_new_j)); + kqmax[j0/nwarps] = kqmax_new_j; + + const half val = hexp(sink - kqmax[j0/nwarps]); + kqsum[j0/nwarps] = kqsum[j0/nwarps] * KQ_max_scale; + if (threadIdx.x == 0) { + kqsum[j0/nwarps].x = __hadd(kqsum[j0/nwarps].x, val); + } + +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { + VKQ[j0/nwarps][i0/WARP_SIZE] *= KQ_max_scale; + } + } + } + float2 * dst2 = (float2 *) dst; #pragma unroll @@ -290,7 +299,7 @@ static __global__ void flash_attn_tile_ext_f16( } } #else - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); + GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); GGML_UNUSED(sinks); GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); @@ -300,8 +309,7 @@ static __global__ void flash_attn_tile_ext_f16( GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb33); GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); GGML_UNUSED(nb21); GGML_UNUSED(nb22); - GGML_UNUSED(nb23); GGML_UNUSED(ne0); GGML_UNUSED(ne1); - GGML_UNUSED(ne2); GGML_UNUSED(ne3); + GGML_UNUSED(nb23); NO_DEVICE_CODE; #endif // defined(FLASH_ATTN_AVAILABLE) && defined(FP16_AVAILABLE) } diff --git a/ggml/src/ggml-cuda/fattn-tile-f32.cu b/ggml/src/ggml-cuda/fattn-tile-f32.cu index a4965583ce..c58194937d 100644 --- a/ggml/src/ggml-cuda/fattn-tile-f32.cu +++ b/ggml/src/ggml-cuda/fattn-tile-f32.cu @@ -5,14 +5,16 @@ #define FATTN_KQ_STRIDE_TILE_F32 32 template // D == head size -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#if !defined(GGML_USE_HIP) __launch_bounds__(nwarps*WARP_SIZE, 2) -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#endif // !defined(GGML_USE_HIP) static __global__ void flash_attn_tile_ext_f32( const char * __restrict__ Q, const char * __restrict__ K, const char * __restrict__ V, const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, float * __restrict__ dst, float2 * __restrict__ dst_meta, const float scale, @@ -21,33 +23,13 @@ static __global__ void flash_attn_tile_ext_f32( const float m1, const uint32_t n_head_log2, const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int ne33, - const int nb31, - const int nb32, - const int nb33, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33) { #ifdef FLASH_ATTN_AVAILABLE // Skip unused kernel variants for faster compilation: @@ -56,18 +38,17 @@ static __global__ void flash_attn_tile_ext_f32( return; #endif // FP16_MMA_AVAILABLE if (use_logit_softcap && !(D == 128 || D == 256)) { - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); + GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); GGML_UNUSED(sinks); + GGML_UNUSED(dst); GGML_UNUSED(dst_meta); + GGML_UNUSED(scale); GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); - GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); - GGML_UNUSED(ne03); GGML_UNUSED(ne10); GGML_UNUSED(ne11); - GGML_UNUSED(ne12); GGML_UNUSED(ne13); GGML_UNUSED(ne31); GGML_UNUSED(ne32); - GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb01); GGML_UNUSED(nb02); - GGML_UNUSED(nb03); GGML_UNUSED(nb11); GGML_UNUSED(nb12); - GGML_UNUSED(nb13); GGML_UNUSED(nb21); GGML_UNUSED(nb22); - GGML_UNUSED(nb23); GGML_UNUSED(ne0); GGML_UNUSED(ne1); - GGML_UNUSED(ne2); GGML_UNUSED(ne3); + GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(ne03); + GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); + GGML_UNUSED(ne10); GGML_UNUSED(ne11); GGML_UNUSED(ne12); GGML_UNUSED(ne13); + GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); + GGML_UNUSED(nb21); GGML_UNUSED(nb22); GGML_UNUSED(nb23); + GGML_UNUSED(ne31); GGML_UNUSED(ne32); GGML_UNUSED(ne33); + GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb33); NO_DEVICE_CODE; return; } @@ -79,10 +60,11 @@ static __global__ void flash_attn_tile_ext_f32( const int sequence = blockIdx.z / ne02; const int head = blockIdx.z - sequence*ne02; const int gqa_ratio = ne02 / ne12; // With grouped query attention there are > 1 Q matrices per K, V matrix. - const float2 * Q_f2 = (const float2 *) (Q + nb03* sequence + nb02* head + nb01*ic0); - const half2 * K_h2 = (const half2 *) (K + nb13* sequence + nb12*(head / gqa_ratio)); - const half2 * V_h2 = (const half2 *) (V + nb13* sequence + nb12*(head / gqa_ratio)); // K and V have same shape - const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + const float2 * Q_f2 = (const float2 *) (Q + nb03* sequence + nb02* head + nb01*ic0); + const half2 * K_h2 = (const half2 *) (K + nb13* sequence + nb12*(head / gqa_ratio)); + const half2 * V_h2 = (const half2 *) (V + nb13* sequence + nb12*(head / gqa_ratio)); // K and V have same shape + const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + const float * sinksf = (const float *) (sinks); const int stride_KV2 = nb11 / sizeof(half2); @@ -120,7 +102,8 @@ static __global__ void flash_attn_tile_ext_f32( __syncthreads(); - for (int k_VKQ_0 = blockIdx.y*FATTN_KQ_STRIDE_TILE_F32; k_VKQ_0 < ne11; k_VKQ_0 += gridDim.y*FATTN_KQ_STRIDE_TILE_F32) { + const int k_VKQ_max = KV_max ? KV_max[sequence*gridDim.x + blockIdx.x] : ne11; + for (int k_VKQ_0 = blockIdx.y*FATTN_KQ_STRIDE_TILE_F32; k_VKQ_0 < k_VKQ_max; k_VKQ_0 += gridDim.y*FATTN_KQ_STRIDE_TILE_F32) { // Calculate KQ tile and keep track of new maximum KQ values: float kqmax_new[ncols/nwarps]; @@ -135,7 +118,7 @@ static __global__ void flash_attn_tile_ext_f32( #pragma unroll for (int k_KQ_0 = 0; k_KQ_0 < D; k_KQ_0 += 2*WARP_SIZE) { - const half2 tmp = K_h2[(k_VKQ_0 + i_KQ)*stride_KV2 + k_KQ_0/2 + threadIdx.x]; + const half2 tmp = K_h2[int64_t(k_VKQ_0 + i_KQ)*stride_KV2 + k_KQ_0/2 + threadIdx.x]; KV_tmp[i_KQ][k_KQ_0 + 0*WARP_SIZE + threadIdx.x] = __low2float(tmp); KV_tmp[i_KQ][k_KQ_0 + 1*WARP_SIZE + threadIdx.x] = __high2float(tmp); } @@ -231,8 +214,9 @@ static __global__ void flash_attn_tile_ext_f32( for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { const int i = i0 + threadIdx.x; - KV_tmp2[k*(D/2) + i].x = __low2float(V_h2[(k_VKQ_0 + k)*stride_KV2 + i]); - KV_tmp2[k*(D/2) + i].y = __high2float(V_h2[(k_VKQ_0 + k)*stride_KV2 + i]); + const half2 tmp = V_h2[int64_t(k_VKQ_0 + k)*stride_KV2 + i]; + KV_tmp2[k*(D/2) + i].x = __low2float(tmp); + KV_tmp2[k*(D/2) + i].y = __high2float(tmp); } } @@ -269,6 +253,33 @@ static __global__ void flash_attn_tile_ext_f32( __syncthreads(); } + + //Attention sink: adjust running max and sum once per head + if (sinksf && blockIdx.y == 0) { + const float sink = sinksf[head]; + +#pragma unroll + for (int j0 = 0; j0 < ncols; j0 += nwarps) { + float kqmax_new_j = fmaxf(kqmax[j0/nwarps], sink); + kqmax_new_j = warp_reduce_max(kqmax_new_j); + + const float KQ_max_scale = expf(kqmax[j0/nwarps] - kqmax_new_j); + kqmax[j0/nwarps] = kqmax_new_j; + + const float val = expf(sink - kqmax[j0/nwarps]); + kqsum[j0/nwarps] = kqsum[j0/nwarps] * KQ_max_scale; + if (threadIdx.x == 0) { + kqsum[j0/nwarps] += val; + } + +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { + VKQ[j0/nwarps][i0/WARP_SIZE].x *= KQ_max_scale; + VKQ[j0/nwarps][i0/WARP_SIZE].y *= KQ_max_scale; + } + } + } + float2 * dst2 = (float2 *) dst; #pragma unroll @@ -302,17 +313,16 @@ static __global__ void flash_attn_tile_ext_f32( } #else GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); + GGML_UNUSED(dst); GGML_UNUSED(dst_meta); + GGML_UNUSED(scale); GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(ne03); - GGML_UNUSED(ne10); GGML_UNUSED(ne11); GGML_UNUSED(ne12); GGML_UNUSED(ne13); - GGML_UNUSED(ne31); GGML_UNUSED(ne32); - GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); + GGML_UNUSED(ne10); GGML_UNUSED(ne11); GGML_UNUSED(ne12); GGML_UNUSED(ne13); GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); GGML_UNUSED(nb21); GGML_UNUSED(nb22); GGML_UNUSED(nb23); - GGML_UNUSED(ne0); GGML_UNUSED(ne1); GGML_UNUSED(ne2); GGML_UNUSED(ne3); + GGML_UNUSED(ne31); GGML_UNUSED(ne32); GGML_UNUSED(ne33); + GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb33); NO_DEVICE_CODE; #endif // FLASH_ATTN_AVAILABLE } diff --git a/ggml/src/ggml-cuda/fattn-vec-f16.cuh b/ggml/src/ggml-cuda/fattn-vec-f16.cuh index b2d469938a..b05f682cd3 100644 --- a/ggml/src/ggml-cuda/fattn-vec-f16.cuh +++ b/ggml/src/ggml-cuda/fattn-vec-f16.cuh @@ -1,6 +1,12 @@ #include "common.cuh" #include "fattn-common.cuh" +// Currenlty llvm with the amdgcn target dose not support unrolling loops +// that contain a break that can not be resolved at compile time. +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpass-failed" +#endif // __clang__ template // D == head size #ifndef GGML_USE_HIP __launch_bounds__(D, 1) @@ -10,6 +16,8 @@ static __global__ void flash_attn_vec_ext_f16( const char * __restrict__ K, const char * __restrict__ V, const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, float * __restrict__ dst, float2 * __restrict__ dst_meta, const float scale, @@ -18,33 +26,13 @@ static __global__ void flash_attn_vec_ext_f16( const float m1, const uint32_t n_head_log2, const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int ne33, - const int nb31, - const int nb32, - const int nb33, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33) { #if defined(FLASH_ATTN_AVAILABLE) && defined(FP16_AVAILABLE) // Skip unused kernel variants for faster compilation: @@ -74,7 +62,8 @@ static __global__ void flash_attn_vec_ext_f16( K += nb13*sequence + nb12*(head / gqa_ratio); V += nb23*sequence + nb22*(head / gqa_ratio); - const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + const float * sinksf = (const float *) (sinks); const float slopef = get_alibi_slope(max_bias, head, n_head_log2, m0, m1); const half slopeh = __float2half(slopef); @@ -88,11 +77,12 @@ static __global__ void flash_attn_vec_ext_f16( half2 * KQ2 = (half2 *) KQ; half kqmax[ncols]; + half kqsum[ncols]; #pragma unroll for (int j = 0; j < ncols; ++j) { kqmax[j] = -HALF_MAX_HALF; + kqsum[j] = 0.0f; } - half kqsum[ncols] = {0.0f}; __shared__ half kqmax_shared[ncols][WARP_SIZE]; __shared__ half kqsum_shared[ncols][WARP_SIZE]; @@ -191,37 +181,22 @@ static __global__ void flash_attn_vec_ext_f16( half2 VKQ[ncols] = {{0.0f, 0.0f}}; - for (int k_VKQ_0 = blockIdx.y*D; k_VKQ_0 < ne11; k_VKQ_0 += gridDim.y*D) { + const int k_VKQ_max = KV_max ? KV_max[sequence*gridDim.x + blockIdx.x] : ne11; + K += blockIdx.y*D * nb11; + V += blockIdx.y*D * nb21; + maskh += blockIdx.y*D; + for (int k_VKQ_0 = blockIdx.y*D; k_VKQ_0 < k_VKQ_max; k_VKQ_0 += gridDim.y*D, + // Increment pointers after each loop: + K += gridDim.y*D*nb11, V += gridDim.y*D*nb21, maskh += gridDim.y*D) { + // Calculate KQ tile and keep track of new maximum KQ values: if (mask) { #pragma unroll for (int j = 0; j < ncols; ++j) { - maskh_shared[j*D + tid] = slopeh*maskh[j*ne11 + k_VKQ_0 + tid]; + maskh_shared[j*D + tid] = slopeh*maskh[j*ne11 + tid]; } - __syncthreads(); - - // When using multiple parallel sequences in llama.cpp, some KV slices can be fully masked out. - // In such cases, skip the KV slice. - // On AMD __all_sync would not work correctly because it assumes a warp size of 64. -#ifndef GGML_USE_HIP - bool skip = true; -#pragma unroll - for (int j = 0; j < ncols; ++j) { -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - const float2 tmp = __half22float2(((const half2 *) maskh_shared)[j*(D/2) + i]); - skip = skip && isinf(tmp.x) && isinf(tmp.y); - } - } - if (__all_sync(0xFFFFFFFF, skip)) { - __syncthreads(); - continue; - } -#endif // GGML_USE_HIP } // For unknown reasons using a half array of size 1 for kqmax_new causes a performance regression, @@ -244,7 +219,7 @@ static __global__ void flash_attn_vec_ext_f16( #pragma unroll for (int j = 0; j < ncols; ++j) { - half sum = vec_dot_KQ(K + (k_VKQ_0 + i_KQ)*nb11, Q_h2[j], Q_i32[j], Q_ds[j]); + half sum = vec_dot_KQ(K + i_KQ*nb11, Q_h2[j], Q_i32[j], Q_ds[j]); sum = warp_reduce_sum((float)sum); if (use_logit_softcap) { @@ -300,8 +275,8 @@ static __global__ void flash_attn_vec_ext_f16( } half2 V_k; - reinterpret_cast(V_k.x) = dequantize_1_v(V + (k_VKQ_0 + k0 + 0)*nb21, tid); - reinterpret_cast(V_k.y) = dequantize_1_v(V + (k_VKQ_0 + k0 + 1)*nb21, tid); + reinterpret_cast(V_k.x) = dequantize_1_v(V + (k0 + 0)*nb21, tid); + reinterpret_cast(V_k.y) = dequantize_1_v(V + (k0 + 1)*nb21, tid); #pragma unroll for (int j = 0; j < ncols; ++j) { VKQ[j] += V_k*KQ2[j*(D/2) + k0/2]; @@ -311,6 +286,39 @@ static __global__ void flash_attn_vec_ext_f16( __syncthreads(); } + if (sinksf && blockIdx.y == 0) { + const half sink = __float2half(sinksf[head]); + +#pragma unroll + for (int j = 0; j < ncols; ++j) { + if (threadIdx.x == 0) { + kqmax_shared[j][threadIdx.y] = fmaxf(kqmax[j], sink); + } + } + + __syncthreads(); + +#pragma unroll + for (int j = 0; j < ncols; ++j) { + half kqmax_new_j = kqmax_shared[j][threadIdx.x]; + kqmax_new_j = warp_reduce_max(kqmax_new_j); + + const half KQ_max_scale = hexp(kqmax[j] - kqmax_new_j); + kqmax[j] = kqmax_new_j; + + const half val = hexp(sink - kqmax[j]); + kqsum[j] = kqsum[j]*KQ_max_scale; + + if (tid == 0) { + kqsum[j] += val; + } + + VKQ[j] *= __half2half2(KQ_max_scale); + } + + __syncthreads(); + } + #pragma unroll for (int j = 0; j < ncols; ++j) { kqsum[j] = warp_reduce_sum((float)kqsum[j]); @@ -341,21 +349,23 @@ static __global__ void flash_attn_vec_ext_f16( dst_meta[((sequence*ne01 + ic0 + tid)*ne02 + head)*gridDim.y + blockIdx.y] = make_float2(kqmax[tid], kqsum[tid]); } #else - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); + GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); GGML_UNUSED(sinks); + GGML_UNUSED(dst); GGML_UNUSED(dst_meta); + GGML_UNUSED(scale); GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); - GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); - GGML_UNUSED(ne03); GGML_UNUSED(ne10); GGML_UNUSED(ne11); - GGML_UNUSED(ne12); GGML_UNUSED(ne13); GGML_UNUSED(ne31); GGML_UNUSED(ne32); GGML_UNUSED(ne32); - GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb33); GGML_UNUSED(nb01); GGML_UNUSED(nb02); - GGML_UNUSED(nb03); GGML_UNUSED(nb11); GGML_UNUSED(nb12); - GGML_UNUSED(nb13); GGML_UNUSED(nb21); GGML_UNUSED(nb22); - GGML_UNUSED(nb23); GGML_UNUSED(ne0); GGML_UNUSED(ne1); - GGML_UNUSED(ne2); GGML_UNUSED(ne3); + GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(ne03); + GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); + GGML_UNUSED(ne10); GGML_UNUSED(ne11); GGML_UNUSED(ne12); GGML_UNUSED(ne13); + GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); + GGML_UNUSED(nb21); GGML_UNUSED(nb22); GGML_UNUSED(nb23); + GGML_UNUSED(ne31); GGML_UNUSED(ne32); GGML_UNUSED(ne33); + GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb33); NO_DEVICE_CODE; #endif // defined(FLASH_ATTN_AVAILABLE) && defined(FP16_AVAILABLE) } +#ifdef __clang__ +#pragma clang diagnostic pop +#endif // __clang__ template void ggml_cuda_flash_attn_ext_vec_f16_case_impl(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { diff --git a/ggml/src/ggml-cuda/fattn-vec-f32.cuh b/ggml/src/ggml-cuda/fattn-vec-f32.cuh index 405b6f5106..d6d0bfb744 100644 --- a/ggml/src/ggml-cuda/fattn-vec-f32.cuh +++ b/ggml/src/ggml-cuda/fattn-vec-f32.cuh @@ -1,6 +1,12 @@ #include "common.cuh" #include "fattn-common.cuh" +// Currenlty llvm with the amdgcn target dose not support unrolling loops +// that contain a break that can not be resolved at compile time. +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpass-failed" +#endif // __clang__ template // D == head size #ifndef GGML_USE_HIP __launch_bounds__(D, 1) @@ -10,6 +16,8 @@ static __global__ void flash_attn_vec_ext_f32( const char * __restrict__ K, const char * __restrict__ V, const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, float * __restrict__ dst, float2 * __restrict__ dst_meta, const float scale, @@ -18,33 +26,13 @@ static __global__ void flash_attn_vec_ext_f32( const float m1, const uint32_t n_head_log2, const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int ne33, - const int nb31, - const int nb32, - const int nb33, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33) { #ifdef FLASH_ATTN_AVAILABLE // Skip unused kernel variants for faster compilation: @@ -59,8 +47,7 @@ static __global__ void flash_attn_vec_ext_f32( GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb33); GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); GGML_UNUSED(nb21); GGML_UNUSED(nb22); - GGML_UNUSED(nb23); GGML_UNUSED(ne0); GGML_UNUSED(ne1); - GGML_UNUSED(ne2); GGML_UNUSED(ne3); + GGML_UNUSED(nb23); NO_DEVICE_CODE; return; } @@ -86,7 +73,8 @@ static __global__ void flash_attn_vec_ext_f32( K += nb13*sequence + nb12*(head / gqa_ratio); V += nb23*sequence + nb22*(head / gqa_ratio); - const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + const float * sinksf = (const float *) (sinks); const float slope = get_alibi_slope(max_bias, head, n_head_log2, m0, m1); @@ -102,11 +90,12 @@ static __global__ void flash_attn_vec_ext_f32( } float kqmax[ncols]; + float kqsum[ncols]; #pragma unroll for (int j = 0; j < ncols; ++j) { kqmax[j] = -FLT_MAX/2.0f; + kqsum[j] = 0.0f; } - float kqsum[ncols] = {0.0f}; __shared__ float kqmax_shared[ncols][WARP_SIZE]; __shared__ float kqsum_shared[ncols][WARP_SIZE]; @@ -198,36 +187,22 @@ static __global__ void flash_attn_vec_ext_f32( float VKQ[ncols] = {0.0f}; - for (int k_VKQ_0 = blockIdx.y*D; k_VKQ_0 < ne11; k_VKQ_0 += gridDim.y*D) { + const int k_VKQ_max = KV_max ? KV_max[sequence*gridDim.x + blockIdx.x] : ne11; + K += blockIdx.y*D * nb11; + V += blockIdx.y*D * nb21; + maskh += blockIdx.y*D; + for (int k_VKQ_0 = blockIdx.y*D; k_VKQ_0 < k_VKQ_max; k_VKQ_0 += gridDim.y*D, + // Increment pointers after each loop: + K += gridDim.y*D*nb11, V += gridDim.y*D*nb21, maskh += gridDim.y*D) { + // Calculate KQ tile and keep track of new maximum KQ values: if (mask) { #pragma unroll for (int j = 0; j < ncols; ++j) { - maskf_shared[j*D + tid] = slope*__half2float(maskh[j*ne11 + k_VKQ_0 + tid]); + maskf_shared[j*D + tid] = slope*__half2float(maskh[j*ne11 + tid]); } - __syncthreads(); - - // When using multiple parallel sequences in llama.cpp, some KV slices can be fully masked out. - // In such cases, skip the KV slice. - // On AMD __all_sync would not work correctly because it assumes a warp size of 64. -#ifndef GGML_USE_HIP - bool skip = true; -#pragma unroll - for (int j = 0; j < ncols; ++j) { -#pragma unroll - for (int i0 = 0; i0 < D; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - skip = skip && isinf(maskf_shared[j*D + i]); - } - } - if (__all_sync(0xFFFFFFFF, skip)) { - __syncthreads(); - continue; - } -#endif // GGML_USE_HIP } float kqmax_new_arr[ncols]; @@ -246,7 +221,7 @@ static __global__ void flash_attn_vec_ext_f32( #pragma unroll for (int j = 0; j < ncols; ++j) { - float sum = vec_dot_KQ(K + (k_VKQ_0 + i_KQ)*nb11, Q_f2[j], Q_i32[j], Q_ds[j]); + float sum = vec_dot_KQ(K + i_KQ*nb11, Q_f2[j], Q_i32[j], Q_ds[j]); sum = warp_reduce_sum(sum); if (use_logit_softcap) { @@ -297,7 +272,7 @@ static __global__ void flash_attn_vec_ext_f32( break; } - const float V_ki = dequantize_1_v(V + (k_VKQ_0 + k)*nb21, tid); + const float V_ki = dequantize_1_v(V + k*nb21, tid); #pragma unroll for (int j = 0; j < ncols; ++j) { VKQ[j] += V_ki*KQ[j*D + k]; @@ -307,6 +282,39 @@ static __global__ void flash_attn_vec_ext_f32( __syncthreads(); } + if (sinksf && blockIdx.y == 0) { + const float sink = sinksf[head]; + +#pragma unroll + for (int j = 0; j < ncols; ++j) { + if (threadIdx.x == 0) { + kqmax_shared[j][threadIdx.y] = fmaxf(kqmax[j], sink); + } + } + + __syncthreads(); + +#pragma unroll + for (int j = 0; j < ncols; ++j) { + float kqmax_new_j = kqmax_shared[j][threadIdx.x]; + kqmax_new_j = warp_reduce_max(kqmax_new_j); + + const float KQ_max_scale = expf(kqmax[j] - kqmax_new_j); + kqmax[j] = kqmax_new_j; + + const float val = expf(sink - kqmax[j]); + kqsum[j] = kqsum[j]*KQ_max_scale; + + if (tid == 0) { + kqsum[j] += val; + } + + VKQ[j] *= KQ_max_scale; + } + + __syncthreads(); + } + #pragma unroll for (int j = 0; j < ncols; ++j) { kqsum[j] = warp_reduce_sum(kqsum[j]); @@ -348,10 +356,12 @@ static __global__ void flash_attn_vec_ext_f32( GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); GGML_UNUSED(nb21); GGML_UNUSED(nb22); GGML_UNUSED(nb23); - GGML_UNUSED(ne0); GGML_UNUSED(ne1); GGML_UNUSED(ne2); GGML_UNUSED(ne3); NO_DEVICE_CODE; #endif // FLASH_ATTN_AVAILABLE } +#ifdef __clang__ +#pragma clang diagnostic pop +#endif // __clang__ template void ggml_cuda_flash_attn_ext_vec_f32_case_impl(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { diff --git a/ggml/src/ggml-cuda/fattn-wmma-f16.cu b/ggml/src/ggml-cuda/fattn-wmma-f16.cu index 741b8781d2..6bc7943ccd 100644 --- a/ggml/src/ggml-cuda/fattn-wmma-f16.cu +++ b/ggml/src/ggml-cuda/fattn-wmma-f16.cu @@ -7,7 +7,7 @@ #include "fattn-wmma-f16.cuh" #ifdef FP16_MMA_AVAILABLE -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#if !defined(GGML_USE_HIP) #include #ifdef GGML_USE_MUSA namespace wmma = mtmusa::wmma; @@ -15,10 +15,9 @@ namespace wmma = mtmusa::wmma; namespace wmma = nvcuda::wmma; #endif // GGML_USE_MUSA #elif defined(GGML_HIP_ROCWMMA_FATTN) && defined(FP16_MMA_AVAILABLE) -#undef HIP_ENABLE_WARP_SYNC_BUILTINS // conflicts with rocWMMA headers #include namespace wmma = rocwmma; -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#endif // !defined(GGML_USE_HIP) #endif // FP16_MMA_AVAILABLE // D == head size, VKQ_stride == num VKQ rows calculated in parallel: @@ -29,6 +28,8 @@ static __global__ void flash_attn_ext_f16( const char * __restrict__ K, const char * __restrict__ V, const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, float * __restrict__ dst, float2 * __restrict__ dst_meta, const float scale, @@ -37,33 +38,13 @@ static __global__ void flash_attn_ext_f16( const float m1, const uint32_t n_head_log2, const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int ne33, - const int nb31, - const int nb32, - const int nb33, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33) { #if defined(FLASH_ATTN_AVAILABLE) && (__CUDA_ARCH__ == GGML_CUDA_CC_VOLTA || (defined(GGML_HIP_ROCWMMA_FATTN) && defined(FP16_MMA_AVAILABLE))) // Skip unused kernel variants for faster compilation: if (use_logit_softcap && !(D == 128 || D == 256)) { @@ -100,11 +81,12 @@ static __global__ void flash_attn_ext_f16( const int sequence = blockIdx.z / ne02; const int head = blockIdx.z - sequence*ne02; const int gqa_ratio = ne02 / ne12; // With grouped query attention there are > 1 Q matrices per K, V matrix. - const float * Q_f = (const float *) (Q + nb03* sequence + nb02* head + nb01*ic0); - const half * K_h = (const half *) (K + nb13* sequence + nb12*(head / gqa_ratio)); - const half * V_h = (const half *) (V + nb13* sequence + nb12*(head / gqa_ratio)); // K and V have same shape - const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); - const half2 * mask2 = (const half2 *) maskh; + const float * Q_f = (const float *) (Q + nb03* sequence + nb02* head + nb01*ic0); + const half * K_h = (const half *) (K + nb13* sequence + nb12*(head / gqa_ratio)); + const half * V_h = (const half *) (V + nb13* sequence + nb12*(head / gqa_ratio)); // K and V have same shape + const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + const half2 * mask2 = (const half2 *) maskh; + const float * sinksf = (const float *) sinks; const int stride_Q = nb01 / sizeof(float); const int stride_KV = nb11 / sizeof(half); @@ -185,7 +167,8 @@ static __global__ void flash_attn_ext_f16( __syncthreads(); // Iterate over ne11 == previous tokens: - for (int k_VKQ_0 = blockIdx.y*FATTN_KQ_STRIDE; k_VKQ_0 < ne11; k_VKQ_0 += gridDim.y*FATTN_KQ_STRIDE) { + const int k_VKQ_max = KV_max ? KV_max[sequence*gridDim.x + blockIdx.x] : ne11; + for (int k_VKQ_0 = blockIdx.y*FATTN_KQ_STRIDE; k_VKQ_0 < k_VKQ_max; k_VKQ_0 += gridDim.y*FATTN_KQ_STRIDE) { // Calculate tile of KQ: #pragma unroll for (int i_KQ_0 = 0; i_KQ_0 < FATTN_KQ_STRIDE; i_KQ_0 += KQ_stride_tc) { @@ -197,7 +180,7 @@ static __global__ void flash_attn_ext_f16( #pragma unroll for (int k_KQ_0 = 0; k_KQ_0 < D; k_KQ_0 += 16) { frag_a_K K_a; - wmma::load_matrix_sync(K_a, K_h + (k_VKQ_0 + i_KQ_0 + frag_m*threadIdx.y)*stride_KV + k_KQ_0, stride_KV); + wmma::load_matrix_sync(K_a, K_h + int64_t(k_VKQ_0 + i_KQ_0 + frag_m*threadIdx.y)*stride_KV + k_KQ_0, stride_KV); #pragma unroll for (int j = 0; j < ncols/frag_n; ++j) { wmma::mma_sync(KQ_c[j], K_a, Q_b[k_KQ_0/16][j], KQ_c[j]); @@ -344,7 +327,7 @@ static __global__ void flash_attn_ext_f16( const int k = k0 + (threadIdx.y % VKQ_ratio)*16; frag_a_V v_a; - wmma::load_matrix_sync(v_a, V_h + (k_VKQ_0 + k)*stride_KV + i_VKQ_0 + frag_m*(threadIdx.y/VKQ_ratio), stride_KV); + wmma::load_matrix_sync(v_a, V_h + int64_t(k_VKQ_0 + k)*stride_KV + i_VKQ_0 + frag_m*(threadIdx.y/VKQ_ratio), stride_KV); #pragma unroll for (int j = 0; j < ncols/frag_n; ++j) { wmma::mma_sync(VKQ_c[i_VKQ_0/VKQ_stride][j], v_a, KQ_b[k0/(VKQ_ratio*16)][j], VKQ_c[i_VKQ_0/VKQ_stride][j]); @@ -398,6 +381,53 @@ static __global__ void flash_attn_ext_f16( __syncthreads(); } + // Apply attention sinks + if (sinksf && blockIdx.y == 0) { + const float sinkf = sinksf[head]; + const half sinkh = __float2half(sinkf); + +#pragma unroll + for (int j0 = 0; j0 < ncols; j0 += nwarps) { + const int j = j0 + threadIdx.y; + + if (std::is_same::value) { + float kqmax_new = fmaxf(KQ_max_f[j0/nwarps], sinkf); + + const float KQ_max_scale = expf(KQ_max_f[j0/nwarps] - kqmax_new); + KQ_max_f[j0/nwarps] = kqmax_new; + + KQ_rowsum_f[j0/nwarps] = KQ_rowsum_f[j0/nwarps] * KQ_max_scale + expf(sinkf - KQ_max_f[j0/nwarps]); + + const half2 scale_h2 = make_half2(KQ_max_scale, KQ_max_scale); +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size) { + const int i = i0 + threadIdx.x; + if (i0 + warp_size > D/2 && i >= D/2) break; + VKQ2[j*(D_padded/2) + i] *= scale_h2; + } + } else { + half kqmax_old = __low2half(KQ_max_h2[j0/nwarps]); + half kqmax_new = fmaxf(kqmax_old, sinkh); + KQ_max_h2[j0/nwarps] = __half2half2(kqmax_new); + + const half KQ_max_scale_h = hexp(kqmax_old - kqmax_new); + const half2 KQ_max_scale = __half2half2(KQ_max_scale_h); + + KQ_rowsum_h2[j0/nwarps] = KQ_rowsum_h2[j0/nwarps] * KQ_max_scale; + const half val = hexp(sinkh - kqmax_new); + KQ_rowsum_h2[j0/nwarps].x = __hadd(KQ_rowsum_h2[j0/nwarps].x, val); + +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size) { + const int i = i0 + threadIdx.x; + if (i0 + warp_size > D/2 && i >= D/2) break; + VKQ2[j*(D_padded/2) + i] *= KQ_max_scale; + } + } + } + + __syncthreads(); + } #pragma unroll for (int j0 = 0; j0 < ncols; j0 += nwarps) { const int j_VKQ = j0 + threadIdx.y; @@ -441,7 +471,7 @@ static __global__ void flash_attn_ext_f16( dst_meta[j_dst_unrolled] = dst_meta_val; } #else - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); + GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); GGML_UNUSED(sinks); GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); @@ -451,7 +481,6 @@ static __global__ void flash_attn_ext_f16( GGML_UNUSED(nb32); GGML_UNUSED(nb33); GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); GGML_UNUSED(nb21); GGML_UNUSED(nb22); GGML_UNUSED(nb23); - GGML_UNUSED(ne0); GGML_UNUSED(ne1); GGML_UNUSED(ne2); GGML_UNUSED(ne3); NO_DEVICE_CODE; #endif // defined(FLASH_ATTN_AVAILABLE) && (__CUDA_ARCH__ == GGML_CUDA_CC_VOLTA || (defined(GGML_HIP_ROCWMMA_FATTN) && defined(FP16_MMA_AVAILABLE))) } @@ -567,7 +596,7 @@ void ggml_cuda_flash_attn_ext_wmma_f16(ggml_backend_cuda_context & ctx, ggml_ten return; } -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#if !defined(GGML_USE_HIP) if (Q->ne[1] <= 8 && Q->ne[0] % warp_size == 0) { constexpr int cols_per_block = 8; switch (Q->ne[0]) { @@ -589,7 +618,7 @@ void ggml_cuda_flash_attn_ext_wmma_f16(ggml_backend_cuda_context & ctx, ggml_ten } return; } -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#endif // !defined(GGML_USE_HIP) if (Q->ne[1] <= 32) { constexpr int cols_per_block = 16; diff --git a/ggml/src/ggml-cuda/fattn.cu b/ggml/src/ggml-cuda/fattn.cu index 6bc0096cc6..22e90d0e7b 100644 --- a/ggml/src/ggml-cuda/fattn.cu +++ b/ggml/src/ggml-cuda/fattn.cu @@ -269,33 +269,23 @@ static void ggml_cuda_flash_attn_ext_vec_f32(ggml_backend_cuda_context & ctx, gg } void ggml_cuda_flash_attn_ext(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - const ggml_tensor * KQV = dst; - const ggml_tensor * Q = dst->src[0]; - const ggml_tensor * K = dst->src[1]; - const ggml_tensor * V = dst->src[2]; - const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * KQV = dst; + const ggml_tensor * Q = dst->src[0]; + const ggml_tensor * K = dst->src[1]; + const ggml_tensor * V = dst->src[2]; + const ggml_tensor * mask = dst->src[3]; ggml_cuda_set_device(ctx.device); const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; const int warp_size = ggml_cuda_info().devices[ggml_cuda_get_device()].warp_size; const enum ggml_prec prec = ggml_flash_attn_ext_get_prec(KQV); - if (GGML_CUDA_CC_IS_AMD(cc)) { #if defined(GGML_HIP_ROCWMMA_FATTN) - if (fp16_mma_available(cc)) { - ggml_cuda_flash_attn_ext_wmma_f16(ctx, dst); - return; - } -#endif // defined(GGML_HIP_ROCWMMA_FATTN) - - // On AMD the tile kernels perform poorly, use the vec kernel instead: - if (prec == GGML_PREC_DEFAULT && fast_fp16_available(cc)) { - ggml_cuda_flash_attn_ext_vec_f16(ctx, dst); - } else { - ggml_cuda_flash_attn_ext_vec_f32(ctx, dst); - } + if (GGML_CUDA_CC_IS_AMD(cc) && fp16_mma_available(cc)) { + ggml_cuda_flash_attn_ext_wmma_f16(ctx, dst); return; } +#endif // defined(GGML_HIP_ROCWMMA_FATTN) if (!fast_fp16_available(cc)) { if (Q->ne[1] <= 8 || Q->ne[0] == 256) { @@ -325,7 +315,9 @@ void ggml_cuda_flash_attn_ext(ggml_backend_cuda_context & ctx, ggml_tensor * dst const bool gqa_opt_applies = ((Q->ne[2] / K->ne[2]) % 2 == 0) && mask; // The mma-based kernels have GQA-specific optimizations const bool mma_needs_data_conversion = K->type != GGML_TYPE_F16 || V->type != GGML_TYPE_F16; - const bool mma_faster_for_bs1 = new_mma_available(cc) && gqa_opt_applies && cc < GGML_CUDA_CC_ADA_LOVELACE && !mma_needs_data_conversion; + const bool mma_faster_for_rtx4000 = Q->ne[3] > 1 || (Q->ne[2] > 4*K->ne[2] && K->ne[1] >= 8192); + const bool mma_faster_for_bs1 = turing_mma_available(cc) && gqa_opt_applies && !mma_needs_data_conversion && + (cc < GGML_CUDA_CC_ADA_LOVELACE || mma_faster_for_rtx4000); const bool can_use_vector_kernel = Q->ne[0] <= 256 && Q->ne[0] % (2*warp_size) == 0; if (Q->ne[1] == 1 && can_use_vector_kernel && !mma_faster_for_bs1) { if (prec == GGML_PREC_DEFAULT) { @@ -337,7 +329,7 @@ void ggml_cuda_flash_attn_ext(ggml_backend_cuda_context & ctx, ggml_tensor * dst } // The MMA implementation needs Turing or newer, use the old WMMA code for Volta: - if (fp16_mma_available(cc) && !new_mma_available(cc)) { + if (fp16_mma_available(cc) && !turing_mma_available(cc)) { ggml_cuda_flash_attn_ext_wmma_f16(ctx, dst); return; } diff --git a/ggml/src/ggml-cuda/getrows.cu b/ggml/src/ggml-cuda/getrows.cu index f77b2629a1..68d3254fbe 100644 --- a/ggml/src/ggml-cuda/getrows.cu +++ b/ggml/src/ggml-cuda/getrows.cu @@ -1,5 +1,6 @@ #include "getrows.cuh" #include "dequantize.cuh" +#include "convert.cuh" template static __global__ void k_get_rows( @@ -34,8 +35,8 @@ static __global__ void k_get_rows( dfloat2 v; dequantize_kernel(src0_row, ib, iqs, v); - dst_row[iybs + iqs + 0] = float(v.x); - dst_row[iybs + iqs + y_offset] = float(v.y); + dst_row[iybs + iqs + 0] = ggml_cuda_cast(v.x); + dst_row[iybs + iqs + y_offset] = ggml_cuda_cast(v.y); } template @@ -62,7 +63,7 @@ static __global__ void k_get_rows_float( dst_t * dst_row = dst + i10*s1 + i11*s2 + i12*s3; const src0_t * src0_row = (const src0_t *)((const char *) src0 + i01*nb01 + i11*nb02 + i12*nb03); - dst_row[i00] = float(src0_row[i00]); + dst_row[i00] = ggml_cuda_cast(src0_row[i00]); } template diff --git a/ggml/src/ggml-cuda/ggml-cuda.cu b/ggml/src/ggml-cuda/ggml-cuda.cu index dfc50ef0da..d6402a8daa 100644 --- a/ggml/src/ggml-cuda/ggml-cuda.cu +++ b/ggml/src/ggml-cuda/ggml-cuda.cu @@ -4,6 +4,7 @@ #include "ggml-cuda/common.cuh" #include "ggml-cuda/acc.cuh" +#include "ggml-cuda/add-id.cuh" #include "ggml-cuda/arange.cuh" #include "ggml-cuda/argmax.cuh" #include "ggml-cuda/argsort.cuh" @@ -21,17 +22,21 @@ #include "ggml-cuda/fattn.cuh" #include "ggml-cuda/getrows.cuh" #include "ggml-cuda/im2col.cuh" +#include "ggml-cuda/mmf.cuh" #include "ggml-cuda/mmq.cuh" -#include "ggml-cuda/mmv.cuh" +#include "ggml-cuda/mmvf.cuh" #include "ggml-cuda/mmvq.cuh" #include "ggml-cuda/norm.cuh" #include "ggml-cuda/opt-step-adamw.cuh" +#include "ggml-cuda/opt-step-sgd.cuh" #include "ggml-cuda/out-prod.cuh" #include "ggml-cuda/pad.cuh" #include "ggml-cuda/pool2d.cuh" #include "ggml-cuda/quantize.cuh" #include "ggml-cuda/rope.cuh" +#include "ggml-cuda/roll.cuh" #include "ggml-cuda/scale.cuh" +#include "ggml-cuda/softcap.cuh" #include "ggml-cuda/softmax.cuh" #include "ggml-cuda/ssm-conv.cuh" #include "ggml-cuda/ssm-scan.cuh" @@ -55,6 +60,7 @@ #include #include #include +#include #include #include #include @@ -125,7 +131,7 @@ static cudaError_t ggml_cuda_device_malloc(void ** ptr, size_t size, int device) return err; } -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) static int ggml_cuda_parse_id(char devName[]) { // A list of possible Target IDs can be found under the rocclr/clr repo in device.cpp // these values are not stable so this is susceptible to breakage @@ -172,33 +178,9 @@ static int ggml_cuda_parse_id(char devName[]) { archNum += archMinor; return archNum; } -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#endif // defined(GGML_USE_HIP) static ggml_cuda_device_info ggml_cuda_init() { -#ifdef __HIP_PLATFORM_AMD__ - // Workaround for a rocBLAS bug when using multiple graphics cards: - // https://github.com/ROCmSoftwarePlatform/rocBLAS/issues/1346 - { - int major_version = 0; - size_t version_length = 0; - if (rocblas_get_version_string_size(&version_length) == rocblas_status_success) { - std::vector version(version_length+1, '\0'); - if (rocblas_get_version_string(version.data(), version.size()) == rocblas_status_success) { - version.resize(::strlen(version.data())); - int parsed_value = 0; - if (std::from_chars(version.data(), version.data() + version.size(), parsed_value).ec == std::errc()) { - major_version = parsed_value; - } - } - } - if (major_version < 4) { - GGML_LOG_DEBUG(GGML_CUDA_NAME " calling rocblas_initialize as a workaround for a rocBLAS bug\n"); - rocblas_initialize(); - CUDA_CHECK(cudaDeviceSynchronize()); - } - } -#endif - ggml_cuda_device_info info = {}; cudaError_t err = cudaGetDeviceCount(&info.device_count); @@ -248,7 +230,7 @@ static ggml_cuda_device_info ggml_cuda_init() { info.devices[id].nsm = prop.multiProcessorCount; info.devices[id].smpb = prop.sharedMemPerBlock; info.devices[id].warp_size = prop.warpSize; -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) info.devices[id].smpbo = prop.sharedMemPerBlock; info.devices[id].cc = ggml_cuda_parse_id(prop.gcnArchName); @@ -278,7 +260,7 @@ static ggml_cuda_device_info ggml_cuda_init() { info.devices[id].cc = 100*prop.major + 10*prop.minor; GGML_LOG_INFO(" Device %d: %s, compute capability %d.%d, VMM: %s\n", id, prop.name, prop.major, prop.minor, device_vmm ? "yes" : "no"); -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#endif // defined(GGML_USE_HIP) } for (int id = 0; id < info.device_count; ++id) { @@ -1849,6 +1831,9 @@ static void ggml_cuda_mul_mat_batched_cublas_impl(ggml_backend_cuda_context & ct ggml_cuda_pool_alloc src0_alloc(ctx.pool()); ggml_cuda_pool_alloc src1_alloc(ctx.pool()); + bool is_src0_cont_2 = ggml_is_contiguous_2(src0); + bool is_src1_cont_2 = ggml_is_contiguous_2(src1); + // Handle src0 src0_ptr = (const cuda_t *) src0->data; @@ -1867,6 +1852,8 @@ static void ggml_cuda_mul_mat_batched_cublas_impl(ggml_backend_cuda_context & ct s11 = ne10; s12 = ne11*s11; s13 = ne12*s12; + + is_src1_cont_2 = true; } // Setup destination buffer @@ -1915,15 +1902,19 @@ static void ggml_cuda_mul_mat_batched_cublas_impl(ggml_backend_cuda_context & ct const int64_t r2 = ne12/ne02; const int64_t r3 = ne13/ne03; - if (r2 == 1 && r3 == 1 && ggml_is_contiguous_2(src0) && ggml_is_contiguous_2(src1)) { + if (r2 == 1 && r3 == 1 && is_src0_cont_2 && is_src1_cont_2) { + // with a [0, 2, 1, 3] perm. and ne02==1 the matrix strides need to be determined from dim 3: + const int64_t sma = ne02 == 1 ? nb03/nb00 : nb02/nb00; + const int64_t smb = ne12 == 1 ? s13 : s12; + // there is no broadcast and src0, src1 are contiguous across dims 2, 3 // use cublasGemmStridedBatchedEx CUBLAS_CHECK( cublasGemmStridedBatchedEx(ctx.cublas_handle(), CUBLAS_OP_T, CUBLAS_OP_N, ne01, ne11, ne10, - alpha, src0_ptr, cu_data_type_a, nb01/nb00, nb02/nb00, // strideA - src1_ptr, cu_data_type_b, s11, s12, // strideB - beta, dst_t, cu_data_type, ne0, ne1*ne0, // strideC + alpha, src0_ptr, cu_data_type_a, nb01/nb00, sma, // strideA + src1_ptr, cu_data_type_b, s11, smb, // strideB + beta, dst_t, cu_data_type, ne0, ne1*ne0, // strideC ne12*ne13, cu_compute_type, CUBLAS_GEMM_DEFAULT_TENSOR_OP)); @@ -1995,7 +1986,9 @@ static void ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor const bool bad_padding_clear = ggml_backend_buffer_get_usage(src0->buffer) == GGML_BACKEND_BUFFER_USAGE_COMPUTE && ggml_nbytes(src0) != ggml_backend_buffer_get_alloc_size(src0->buffer, src0) && src0->view_src; - bool use_mul_mat_vec = (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16 || src0->type == GGML_TYPE_BF16) + bool use_mul_mat_vec_f = (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16 || src0->type == GGML_TYPE_BF16) + && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32; + bool use_mul_mat_f = !ggml_is_quantized(src0->type) && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32; bool use_mul_mat_vec_q = ggml_is_quantized(src0->type) && !bad_padding_clear && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32 @@ -2015,14 +2008,18 @@ static void ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor } const int cc = ggml_cuda_info().devices[id].cc; + const int warp_size = ggml_cuda_info().devices[id].warp_size; use_mul_mat_q = use_mul_mat_q && ggml_cuda_should_use_mmq(src0->type, cc, src1->ne[1]); - use_mul_mat_vec = use_mul_mat_vec && ggml_cuda_should_use_mmv(src0->type, cc, src0->ne, src1->ne[1]); + use_mul_mat_f = use_mul_mat_f && ggml_cuda_should_use_mmf(src0->type, cc, warp_size, src0->ne, src1->ne[1]); + use_mul_mat_vec_f = use_mul_mat_vec_f && ggml_cuda_should_use_mmvf(src0->type, cc, src0->ne, src1->ne[1]); any_gpus_with_slow_fp16 = any_gpus_with_slow_fp16 || !fast_fp16_hardware_available(cc); } } else { const int cc = ggml_cuda_info().devices[ctx.device].cc; + const int warp_size = ggml_cuda_info().devices[ctx.device].warp_size; use_mul_mat_q = use_mul_mat_q && ggml_cuda_should_use_mmq(src0->type, cc, src1->ne[1]); - use_mul_mat_vec = use_mul_mat_vec && ggml_cuda_should_use_mmv(src0->type, cc, src0->ne, src1->ne[1]); + use_mul_mat_f = use_mul_mat_f && ggml_cuda_should_use_mmf(src0->type, cc, warp_size, src0->ne, src1->ne[1]); + use_mul_mat_vec_f = use_mul_mat_vec_f && ggml_cuda_should_use_mmvf(src0->type, cc, src0->ne, src1->ne[1]); any_gpus_with_slow_fp16 = any_gpus_with_slow_fp16 || !fast_fp16_hardware_available(cc); } @@ -2035,15 +2032,17 @@ static void ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor //printf("src1 is contiguous %d, transposed %d, type = %s, name = %s\n", ggml_is_contiguous(src1), ggml_is_transposed(src1), ggml_type_name(src1->type), src1->name); //TODO update for generic tensor parallelism - const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; + const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; bool use_batched_cublas_f16 = src0->type == GGML_TYPE_F16 && (src1->type == GGML_TYPE_F16 || !any_gpus_with_slow_fp16); bool use_batched_cublas_bf16 = src0->type == GGML_TYPE_BF16 && bf16_mma_hardware_available(cc); bool use_batched_cublas_f32 = src0->type == GGML_TYPE_F32; - if (!split && use_mul_mat_vec) { + if (!split && use_mul_mat_vec_f) { // the custom F16 vector kernel can be used over batched cuBLAS GEMM // but this is only faster for GPUs without tensor cores or with a thin src0 matrix (particularly KQV in attention) - ggml_cuda_mul_mat_vec(ctx, src0, src1, nullptr, dst); + ggml_cuda_mul_mat_vec_f(ctx, src0, src1, nullptr, dst); + } else if (!split && use_mul_mat_f) { + ggml_cuda_mul_mat_f(ctx, src0, src1, nullptr, dst); } else if (!split && use_mul_mat_vec_q) { ggml_cuda_mul_mat_vec_q(ctx, src0, src1, nullptr, dst); } else if (!split && use_mul_mat_q) { @@ -2052,8 +2051,8 @@ static void ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor && !ggml_is_transposed(src0) && !ggml_is_transposed(src1) && src1->ne[2]*src1->ne[3] > 1) { // general KQ + KQV multi-batch without FlashAttention ggml_cuda_mul_mat_batched_cublas(ctx, src0, src1, dst); - } else if (use_mul_mat_vec) { - ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_vec, nullptr); + } else if (use_mul_mat_vec_f) { + ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_vec_f, nullptr); } else if (use_mul_mat_vec_q) { ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_vec_q, quantize_row_q8_1_cuda); } else if (use_mul_mat_q) { @@ -2081,7 +2080,7 @@ static void ggml_cuda_mul_mat_id(ggml_backend_cuda_context & ctx, ggml_tensor * if (ggml_is_quantized(src0->type)) { ggml_cuda_mul_mat_vec_q(ctx, src0, src1, ids, dst); } else { - ggml_cuda_mul_mat_vec(ctx, src0, src1, ids, dst); + ggml_cuda_mul_mat_vec_f(ctx, src0, src1, ids, dst); } return; } @@ -2247,6 +2246,9 @@ static bool ggml_cuda_compute_forward(ggml_backend_cuda_context & ctx, struct gg case GGML_OP_ADD1: // TODO: more efficient implementation ggml_cuda_op_add(ctx, dst); break; + case GGML_OP_ADD_ID: + ggml_cuda_op_add_id(ctx, dst); + break; case GGML_OP_SUB: ggml_cuda_op_sub(ctx, dst); break; @@ -2321,6 +2323,9 @@ static bool ggml_cuda_compute_forward(ggml_backend_cuda_context & ctx, struct gg case GGML_GLU_OP_SWIGLU: ggml_cuda_op_swiglu(ctx, dst); break; + case GGML_GLU_OP_SWIGLU_OAI: + ggml_cuda_op_swiglu_oai(ctx, dst); + break; case GGML_GLU_OP_GEGLU_ERF: ggml_cuda_op_geglu_erf(ctx, dst); break; @@ -2418,6 +2423,9 @@ static bool ggml_cuda_compute_forward(ggml_backend_cuda_context & ctx, struct gg case GGML_OP_ROPE_BACK: ggml_cuda_op_rope_back(ctx, dst); break; + case GGML_OP_ROLL: + ggml_cuda_op_roll(ctx, dst); + break; case GGML_OP_IM2COL: ggml_cuda_op_im2col(ctx, dst); break; @@ -2472,6 +2480,9 @@ static bool ggml_cuda_compute_forward(ggml_backend_cuda_context & ctx, struct gg case GGML_OP_OPT_STEP_ADAMW: ggml_cuda_opt_step_adamw(ctx, dst); break; + case GGML_OP_OPT_STEP_SGD: + ggml_cuda_opt_step_sgd(ctx, dst); + break; default: return false; } @@ -2592,6 +2603,9 @@ static bool check_node_graph_compatibility_and_refresh_copy_ops(ggml_backend_cud const std::string gemma3n_per_layer_proj_src0_name = "inp_per_layer_selected"; const std::string gemma3n_per_layer_proj_src1_name = "per_layer_proj"; + const std::string ffn_moe_gate_bias_prefix = "ffn_moe_gate_biased"; + const std::string ffn_moe_up_bias_prefix = "ffn_moe_up_biased"; + const std::string ffn_moe_down_bias_prefix = "ffn_moe_down_biased"; for (int i = 0; i < cgraph->n_nodes; i++) { ggml_tensor * node = cgraph->nodes[i]; @@ -2614,7 +2628,13 @@ static bool check_node_graph_compatibility_and_refresh_copy_ops(ggml_backend_cud #endif } - if (node->op == GGML_OP_ADD && node->src[1] && node->src[1]->ne[1] > 1 && (node->src[0] ? node->src[0]->name != gemma3n_per_layer_proj_src0_name : true) && (node->src[1] ? node->src[1]->name != gemma3n_per_layer_proj_src1_name : true)) { + if (node->op == GGML_OP_ADD && + node->src[1] && node->src[1]->ne[1] > 1 && + (node->src[0] ? node->src[0]->name != gemma3n_per_layer_proj_src0_name : true) && + (node->src[1] ? node->src[1]->name != gemma3n_per_layer_proj_src1_name : true) && + strncmp(node->name, ffn_moe_gate_bias_prefix.c_str(), ffn_moe_gate_bias_prefix.size()) != 0 && + strncmp(node->name, ffn_moe_up_bias_prefix.c_str(), ffn_moe_up_bias_prefix.size()) != 0 && + strncmp(node->name, ffn_moe_down_bias_prefix.c_str(), ffn_moe_down_bias_prefix.size()) != 0) { // disable CUDA graphs for batch size > 1 for now while excluding the matrix-matrix addition as part of Gemma3n's `project_per_layer_input` operation // by means of matching node names. See // https://github.com/ggml-org/llama.cpp/blob/f9a31eea06a859e34cecb88b4d020c7f03d86cc4/src/llama-model.cpp#L10199-L10241 and @@ -2765,6 +2785,67 @@ static void update_cuda_graph_executable(ggml_backend_cuda_context * cuda_ctx) { } #endif +static bool ggml_cuda_can_fuse(const struct ggml_cgraph * cgraph, int node_idx, std::initializer_list ops, std::initializer_list unary_ops) { +#ifndef NDEBUG + const size_t num_unary = std::count(ops.begin(), ops.end(), GGML_OP_UNARY); + GGML_ASSERT(unary_ops.size() == num_unary); +#endif + + if (!ggml_can_fuse(cgraph, node_idx, ops)) { + return false; + } + + if (ops.size() == 2 && ops.begin()[0] == GGML_OP_RMS_NORM && ops.begin()[1] == GGML_OP_MUL) { + const ggml_tensor *rms_norm = cgraph->nodes[node_idx]; + const ggml_tensor *mul = cgraph->nodes[node_idx+1]; + + GGML_ASSERT(rms_norm->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(rms_norm->type == GGML_TYPE_F32); + + //rms norm only supports F32 + if (mul->src[0]->type != GGML_TYPE_F32 || + mul->src[1]->type != GGML_TYPE_F32 || + mul->type != GGML_TYPE_F32) { + return false; + } + + //if rms norm is the B operand, then we don't handle broadcast + if (rms_norm == mul->src[1] && !ggml_are_same_shape(mul->src[0], rms_norm->src[1])) { + return false; + } + + //rms_norm kernel assumes contigous rows + if (!ggml_is_contiguous_rows(mul->src[0]) || !ggml_is_contiguous_rows(mul->src[1])) { + return false; + } + + return true; + } + + if (ops.size() == 3 && ops.begin()[0] == GGML_OP_SCALE && ops.begin()[1] == GGML_OP_UNARY && ops.begin()[2] == GGML_OP_SCALE + && unary_ops.size() == 1 && unary_ops.begin()[0] == GGML_UNARY_OP_TANH) { + const ggml_tensor *scale = cgraph->nodes[node_idx]; + const ggml_tensor *tanh = cgraph->nodes[node_idx+1]; + const ggml_tensor *scale2 = cgraph->nodes[node_idx+2]; + + GGML_ASSERT(scale->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(scale->type == GGML_TYPE_F32); + + if (ggml_get_unary_op(tanh) != GGML_UNARY_OP_TANH) { + return false; + } + + // Check for bias + if (ggml_get_op_params_f32(scale, 1) != 0.0f || ggml_get_op_params_f32(scale2, 1) != 0.0f) { + return false; + } + + return true; + } + + return false; +} + static void evaluate_and_capture_cuda_graph(ggml_backend_cuda_context * cuda_ctx, ggml_cgraph * cgraph, bool & graph_evaluated_or_captured, bool & use_cuda_graph, bool & cuda_graph_update_required) { // flag used to determine whether it is an integrated_gpu @@ -2774,6 +2855,7 @@ static void evaluate_and_capture_cuda_graph(ggml_backend_cuda_context * cuda_ctx // Only perform the graph execution if CUDA graphs are not enabled, or we are capturing the graph. // With the use of CUDA graphs, the execution will be performed by the graph launch. if (!use_cuda_graph || cuda_graph_update_required) { + for (int i = 0; i < cgraph->n_nodes; i++) { ggml_tensor * node = cgraph->nodes[i]; @@ -2781,6 +2863,20 @@ static void evaluate_and_capture_cuda_graph(ggml_backend_cuda_context * cuda_ctx continue; } + static bool disable_fusion = (getenv("GGML_CUDA_DISABLE_FUSION") != nullptr); + if (!disable_fusion) { + if (ggml_cuda_can_fuse(cgraph, i, { GGML_OP_RMS_NORM, GGML_OP_MUL }, {})) { + ggml_cuda_op_rms_norm_fused(*cuda_ctx, node, cgraph->nodes[i+1]); + i++; + continue; + } + + if (ggml_cuda_can_fuse(cgraph, i, { GGML_OP_SCALE, GGML_OP_UNARY, GGML_OP_SCALE }, { GGML_UNARY_OP_TANH })) { + i += 2; + ggml_cuda_op_softcap(*cuda_ctx, cgraph->nodes[i], node); + continue; + } + } #ifndef NDEBUG assert(node->buffer->buft == ggml_backend_cuda_buffer_type(cuda_ctx->device)); for (int j = 0; j < GGML_MAX_SRC; j++) { @@ -3136,6 +3232,7 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g case GGML_GLU_OP_REGLU: case GGML_GLU_OP_GEGLU: case GGML_GLU_OP_SWIGLU: + case GGML_GLU_OP_SWIGLU_OAI: case GGML_GLU_OP_GEGLU_ERF: case GGML_GLU_OP_GEGLU_QUICK: return ggml_is_contiguous_1(op->src[0]); @@ -3186,6 +3283,7 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g case GGML_TYPE_Q5_0: case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -3242,13 +3340,9 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g { ggml_type src0_type = op->src[0]->type; ggml_type src1_type = op->src[1]->type; - if (src0_type == GGML_TYPE_F32 && src1_type == GGML_TYPE_F32) { - return true; - } - if (src0_type == GGML_TYPE_F32 && src1_type == GGML_TYPE_BF16) { - return true; - } - if (src0_type == GGML_TYPE_F32 && src1_type == GGML_TYPE_F16) { + if ((src0_type == GGML_TYPE_F32 || src0_type == GGML_TYPE_BF16 || src0_type == GGML_TYPE_F16) && + (src1_type == GGML_TYPE_F32 || src1_type == GGML_TYPE_BF16 || src1_type == GGML_TYPE_F16) + ) { return true; } if (src0_type == GGML_TYPE_F32 && src1_type == GGML_TYPE_Q8_0) { @@ -3284,12 +3378,6 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g if (src0_type == GGML_TYPE_F32 && src1_type == GGML_TYPE_IQ4_NL) { return true; } - if (src0_type == GGML_TYPE_F16 && src1_type == GGML_TYPE_F16) { - return true; - } - if (src0_type == GGML_TYPE_F16 && src1_type == GGML_TYPE_F32) { - return true; - } if (src0_type == src1_type && ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1])) { return true; } @@ -3342,6 +3430,7 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g case GGML_OP_PERMUTE: case GGML_OP_TRANSPOSE: case GGML_OP_ADD: + case GGML_OP_ADD_ID: case GGML_OP_ADD1: case GGML_OP_SUB: case GGML_OP_MUL: @@ -3370,7 +3459,7 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g return op->src[0]->ne[1] % 128 == 0; } case GGML_OP_CONT: - return op->src[0]->type != GGML_TYPE_BF16; + return true; case GGML_OP_DIAG_MASK_INF: return true; case GGML_OP_SOFT_MAX: @@ -3380,6 +3469,11 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g memcpy(&max_bias, (const float *) op->op_params + 1, sizeof(float)); return max_bias == 0.0f; } + case GGML_OP_ROLL: + if(op->src[0]->type == GGML_TYPE_F32) { + return true; + } + return false; case GGML_OP_ROPE: case GGML_OP_ROPE_BACK: { return op->src[0]->nb[0] == ggml_type_size(op->src[0]->type) && ggml_is_contiguous_2(op->src[0]); @@ -3411,12 +3505,17 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g #endif // FLASH_ATTN_AVAILABLE if (op->src[1]->ne[0] != op->src[2]->ne[0]) { const int cc = ggml_cuda_info().devices[dev_ctx->device].cc; - if (!new_mma_available(cc)) { + if (!turing_mma_available(cc)) { return false; } const int gqa_ratio = op->src[0]->ne[2] / op->src[1]->ne[2]; return op->src[1]->ne[0] == 576 && op->src[2]->ne[0] == 512 && op->src[3] && gqa_ratio % 16 == 0; } + // TODO: more general-purpose attention sink support [TAG_ATTN_SINKS] + if (op->src[4] && !fp16_mma_available(ggml_cuda_info().devices[dev_ctx->device].cc) + && op->src[0]->ne[0] != 64 && op->src[0]->ne[0] != 128) { + return false; + } if (op->src[0]->ne[0] == 192) { return false; } @@ -3441,6 +3540,7 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g case GGML_OP_CROSS_ENTROPY_LOSS: case GGML_OP_CROSS_ENTROPY_LOSS_BACK: case GGML_OP_OPT_STEP_ADAMW: + case GGML_OP_OPT_STEP_SGD: return true; default: return false; @@ -3680,10 +3780,10 @@ ggml_backend_t ggml_backend_cuda_init(int device) { } ggml_backend_t cuda_backend = new ggml_backend { - /* .guid = */ ggml_backend_cuda_guid(), - /* .interface = */ ggml_backend_cuda_interface, - /* .device = */ ggml_backend_reg_dev_get(ggml_backend_cuda_reg(), device), - /* .context = */ ctx, + /* .guid = */ ggml_backend_cuda_guid(), + /* .iface = */ ggml_backend_cuda_interface, + /* .device = */ ggml_backend_reg_dev_get(ggml_backend_cuda_reg(), device), + /* .context = */ ctx, }; return cuda_backend; diff --git a/ggml/src/ggml-cuda/im2col.cu b/ggml/src/ggml-cuda/im2col.cu index 86a54e42bb..16bb9bec97 100644 --- a/ggml/src/ggml-cuda/im2col.cu +++ b/ggml/src/ggml-cuda/im2col.cu @@ -1,65 +1,76 @@ #include "im2col.cuh" +#define MAX_GRIDDIM_Z 65535 + template static __global__ void im2col_kernel( - const float * x, T * dst, int64_t batch_offset, - int64_t offset_delta, int64_t IC, int64_t IW, int64_t IH, int64_t OH, int64_t OW, int64_t KW, int64_t KH, int64_t pelements, int64_t CHW, + const float * x, T * dst, + int64_t IC, int64_t IW, int64_t IH, int64_t OH, int64_t OW, int64_t KW, int64_t KH, + int64_t IC_IH_IW, int64_t IH_IW, int64_t N_OH, int64_t KH_KW, int64_t IC_KH_KW, int s0, int s1, int p0, int p1, int d0, int d1) { const int64_t i = threadIdx.x + blockIdx.x * blockDim.x; - if (i >= pelements) { + if (i >= IC_KH_KW) { return; } - const int64_t ksize = OW * (KH > 1 ? KW : 1); - const int64_t kx = i / ksize; - const int64_t kd = kx * ksize; - const int64_t ky = (i - kd) / OW; - const int64_t ix = i % OW; + const int64_t iic = i / (KH_KW); + const int64_t rem = i - iic * KH_KW; + const int64_t ikh = rem / KW; + const int64_t ikw = rem - ikh * KW; - const int64_t oh = blockIdx.y; - const int64_t batch = blockIdx.z / IC; - const int64_t ic = blockIdx.z % IC; + const int64_t iow = blockIdx.y; + for (int64_t iz = blockIdx.z; iz < N_OH; iz+=MAX_GRIDDIM_Z) { + const int64_t in = iz / OH; + const int64_t ioh = iz - in * OH; - const int64_t iiw = ix * s0 + kx * d0 - p0; - const int64_t iih = oh * s1 + ky * d1 - p1; + const int64_t iiw = iow * s0 + ikw * d0 - p0; + const int64_t iih = ioh * s1 + ikh * d1 - p1; - const int64_t offset_dst = - ((batch * OH + oh) * OW + ix) * CHW + - (ic * (KW * KH) + ky * KW + kx); + const int64_t offset_dst = + ((in * OH + ioh) * OW + iow) * IC_KH_KW + iic * KH_KW + ikh * KW + ikw; - if (iih < 0 || iih >= IH || iiw < 0 || iiw >= IW) { - dst[offset_dst] = 0.0f; - } else { - const int64_t offset_src = ic * offset_delta + batch * batch_offset; - dst[offset_dst] = x[offset_src + iih * IW + iiw]; + if (iih < 0 || iih >= IH || iiw < 0 || iiw >= IW) { + dst[offset_dst] = 0.0f; + } else { + const int64_t offset_src = iic * IC_IH_IW + in * IH_IW; + dst[offset_dst] = x[offset_src + iih * IW + iiw]; + } } + + GGML_UNUSED(IC); + GGML_UNUSED(KH); } +// im2col: [N, IC, IH, IW] => [N, OH, OW, IC*KH*KW] template static void im2col_cuda(const float * x, T* dst, int64_t IW, int64_t IH, int64_t OW, int64_t OH, int64_t KW, int64_t KH, int64_t IC, - int64_t batch, int64_t batch_offset, int64_t offset_delta, + int64_t N, int64_t IC_IH_IW, int64_t IH_IW, int s0,int s1,int p0,int p1,int d0,int d1, cudaStream_t stream) { - const int parallel_elements = OW * KW * KH; - const int num_blocks = (parallel_elements + CUDA_IM2COL_BLOCK_SIZE - 1) / CUDA_IM2COL_BLOCK_SIZE; - dim3 block_nums(num_blocks, OH, batch * IC); - im2col_kernel<<>>(x, dst, batch_offset, offset_delta, IC, IW, IH, OH, OW, KW, KH, parallel_elements, (IC * KH * KW), s0, s1, p0, p1, d0, d1); + const int64_t IC_KH_KW = IC * KH * KW; + const int64_t num_blocks = (IC_KH_KW + CUDA_IM2COL_BLOCK_SIZE - 1) / CUDA_IM2COL_BLOCK_SIZE; + const int64_t N_OH = N * OH; + const int64_t KH_KW = KW*KH; + dim3 block_nums(num_blocks, OW, MIN(N_OH, MAX_GRIDDIM_Z)); + im2col_kernel<<>>(x, dst, IC, IW, IH, OH, OW, KW, KH, + IC_IH_IW, IH_IW, N_OH, KH_KW, IC_KH_KW, + s0, s1, p0, p1, d0, d1); } static void im2col_cuda_f16(const float * x, half * dst, int64_t IW, int64_t IH, int64_t OW, int64_t OH, int64_t KW, int64_t KH, int64_t IC, - int64_t batch, int64_t batch_offset, int64_t offset_delta, + int64_t N, int64_t IC_IH_IW, int64_t IH_IW, int s0,int s1,int p0,int p1,int d0,int d1, cudaStream_t stream) { - im2col_cuda(x, dst, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, offset_delta, s0, s1, p0, p1, d0, d1, stream); + im2col_cuda(x, dst, IW, IH, OW, OH, KW, KH, IC, N, IC_IH_IW, IH_IW, s0, s1, p0, p1, d0, d1, stream); } static void im2col_cuda_f32(const float * x, float * dst, int64_t IW, int64_t IH, int64_t OW, int64_t OH, int64_t KW, int64_t KH, int64_t IC, - int64_t batch, int64_t batch_offset, int64_t offset_delta, + int64_t N, int64_t IC_IH_IW, int64_t IH_IW, int s0,int s1,int p0,int p1,int d0,int d1, cudaStream_t stream) { - im2col_cuda(x, dst, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, offset_delta, s0, s1, p0, p1, d0, d1, stream); + im2col_cuda(x, dst, IW, IH, OW, OH, KW, KH, IC, N, IC_IH_IW, IH_IW, s0, s1, p0, p1, d0, d1, stream); } void ggml_cuda_op_im2col(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { @@ -91,13 +102,13 @@ void ggml_cuda_op_im2col(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const int64_t OH = is_2D ? dst->ne[2] : 1; const int64_t OW = dst->ne[1]; - const size_t delta_offset = src1->nb[is_2D ? 2 : 1] / 4; // nb is byte offset, src is type float32 - const int64_t batch = src1->ne[is_2D ? 3 : 2]; - const size_t batch_offset = src1->nb[is_2D ? 3 : 2] / 4; // nb is byte offset, src is type float32 + const int64_t IC_IH_IW = src1->nb[is_2D ? 2 : 1] / 4; // nb is byte offset, src is type float32 + const int64_t N = src1->ne[is_2D ? 3 : 2]; + const int64_t IH_IW = src1->nb[is_2D ? 3 : 2] / 4; // nb is byte offset, src is type float32 if(dst->type == GGML_TYPE_F16) { - im2col_cuda_f16(src1_d, (half *) dst_d, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, delta_offset, s0, s1, p0, p1, d0, d1, stream); + im2col_cuda_f16(src1_d, (half *) dst_d, IW, IH, OW, OH, KW, KH, IC, N, IC_IH_IW, IH_IW, s0, s1, p0, p1, d0, d1, stream); } else { - im2col_cuda_f32(src1_d, (float *) dst_d, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, delta_offset, s0, s1, p0, p1, d0, d1, stream); + im2col_cuda_f32(src1_d, (float *) dst_d, IW, IH, OW, OH, KW, KH, IC, N, IC_IH_IW, IH_IW, s0, s1, p0, p1, d0, d1, stream); } } diff --git a/ggml/src/ggml-cuda/mean.cu b/ggml/src/ggml-cuda/mean.cu index 4b238a3998..347abc1866 100644 --- a/ggml/src/ggml-cuda/mean.cu +++ b/ggml/src/ggml-cuda/mean.cu @@ -1,4 +1,14 @@ #include "mean.cuh" +#include "reduce_rows.cuh" + +#ifdef GGML_CUDA_USE_CUB +#include +using namespace cub; +#endif // GGML_CUDA_USE_CUB + +template __global__ void divide_by_count(T * result, size_t count) { + *result /= static_cast(count); +} void ggml_cuda_op_mean(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; @@ -13,7 +23,51 @@ void ggml_cuda_op_mean(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const int64_t ncols = src0->ne[0]; const int64_t nrows = ggml_nrows(src0); - const dim3 block_dims(WARP_SIZE, 1, 1); +// Special case for reducing vectors +#ifdef GGML_CUDA_USE_CUB +#ifdef USE_CUDA_GRAPH + cudaStreamCaptureStatus iscapturing; + CUDA_CHECK(cudaStreamIsCapturing(stream, &iscapturing)); +#endif // USE_CUDA_GRAPH + if ((nrows == 1) && +#ifdef USE_CUDA_GRAPH + // CUDA_GRAPHS_DISABLED + ((ncols > 65536) && + ((ctx.cuda_graph->instance == nullptr) && (iscapturing == cudaStreamCaptureStatusNone) || + ctx.cuda_graph->disable_due_to_gpu_arch || ctx.cuda_graph->disable_due_to_too_many_updates || + ctx.cuda_graph->disable_due_to_failed_graph_capture)) || + // CUDA_GRAPHS ENABLED + ((ncols > 32768) && + !((ctx.cuda_graph->instance == nullptr) && (iscapturing == cudaStreamCaptureStatusNone) || + ctx.cuda_graph->disable_due_to_gpu_arch || ctx.cuda_graph->disable_due_to_too_many_updates || + ctx.cuda_graph->disable_due_to_failed_graph_capture))) { +#else + (ncols > 65536)) { +#endif // USE_CUDA_GRAPH + // Single row - use device-wide reduction + size_t tmp_size = 0; + ggml_cuda_pool & pool = ctx.pool(); + + DeviceReduce::Sum(nullptr, tmp_size, src0_d, dst_d, ncols, stream); + + ggml_cuda_pool_alloc tmp_alloc(pool, tmp_size); + DeviceReduce::Sum(tmp_alloc.ptr, tmp_size, src0_d, dst_d, ncols, stream); + + // Divide by ncols + divide_by_count<<<1, 1, 0, stream>>>(dst_d, ncols); + return; + } +#endif // GGML_CUDA_USE_CUB + const dim3 block_nums(nrows, 1, 1); - reduce_rows_f32<<>>(src0_d, dst_d, ncols); + + const int id = ggml_cuda_get_device(); + const int nsm = ggml_cuda_info().devices[id].nsm; + if ((nrows / nsm) < 2) { + const dim3 block_dims(512, 1, 1); + reduce_rows_f32<<>>(src0_d, dst_d, ncols); + } else { + const dim3 block_dims(ncols < 1024 ? 32 : 128, 1, 1); + reduce_rows_f32<<>>(src0_d, dst_d, ncols); + } } diff --git a/ggml/src/ggml-cuda/mma.cuh b/ggml/src/ggml-cuda/mma.cuh index 2af63355a1..83ee16b27d 100644 --- a/ggml/src/ggml-cuda/mma.cuh +++ b/ggml/src/ggml-cuda/mma.cuh @@ -12,7 +12,8 @@ // The methods get_i and get_j can be used to get the physical 32 bit index of the lth element of a thread within a tile. // All matrix tiles have ne physical 32 bit elements per warp. // -// As described in the documentation, all pointers for load_ldmatrix must be to shared memory and aligned to 16 bytes. +// As described in the PTX documentation, all pointers for load_ldmatrix must be to shared memory and aligned to 16 bytes. +// The API in this file also assumes that the pointers for load_generic are aligned to 16 bytes, unaligned pointers are considered undefined behavior. #include "common.cuh" @@ -22,13 +23,13 @@ static __device__ __forceinline__ int ggml_cuda_movmatrix(const int x) { int ret = 0; -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE asm("movmatrix.sync.aligned.m8n8.trans.b16 %0, %1;" : "=r"(ret) : "r"(x)); #else GGML_UNUSED(x); NO_DEVICE_CODE; -#endif // defined(NEW_MMA_AVAILABLE) +#endif // defined(TURING_MMA_AVAILABLE) return ret; } @@ -66,7 +67,44 @@ namespace ggml_cuda_mma { struct tile { static constexpr int I = I_; static constexpr int J = J_; - static constexpr int ne = I * J / WARP_SIZE; + +#if defined(GGML_USE_HIP) + static constexpr int ne = I * J / 64; + T x[ne] = {0}; + + static __device__ __forceinline__ int get_i(const int l) { + if constexpr (I == 64 && J == 2) { // Special tile size to load <16, 4> as <16, 8> + return threadIdx.x % 16; + } else if constexpr (I == 16 && J == 8) { + return threadIdx.x % 16; + } else if constexpr (I == 32 && J == 4) { + return threadIdx.x % 32; + } else if constexpr (I == 16 && J == 16) { + return 4 * (threadIdx.x / 16) + l; + } else if constexpr (I == 32 && J == 32) { + return 4 * (threadIdx.x / 32) + 8 * (l / 4) + (l % 4); + } else { + static_assert(I == -1 && J == -1, "template specialization not implemented"); + } + } + + static __device__ __forceinline__ int get_j(const int l) { + if constexpr (I == 64 && J == 2) { // Special tile size to load <16, 4> as <16, 8> + return (2 * ((threadIdx.x / 16) % 2) + l); + } else if constexpr (I == 16 && J == 8) { + return 2 * (threadIdx.x / 16) + l; + } else if constexpr (I == 32 && J == 4) { + return 2 * (threadIdx.x / 32) + l; + } else if constexpr (I == 16 && J == 16) { + return threadIdx.x % 16; + } else if constexpr (I == 32 && J == 32) { + return threadIdx.x % 32; + } else { + static_assert(I == -1 && J == -1, "template specialization not implemented"); + } + } +#else + static constexpr int ne = I * J / 32; T x[ne] = {0}; static __device__ __forceinline__ int get_i(const int l) { @@ -94,6 +132,7 @@ namespace ggml_cuda_mma { static_assert(I == -1 && J == -1, "template specialization not implemented"); } } +#endif // defined(GGML_USE_HIP) }; template @@ -128,6 +167,38 @@ namespace ggml_cuda_mma { } }; + template + struct tile { + static constexpr int I = I_; + static constexpr int J = J_; + static constexpr int ne = I * J / WARP_SIZE; + nv_bfloat162 x[ne] = {{0.0f, 0.0f}}; + + static __device__ __forceinline__ int get_i(const int l) { + if constexpr (I == 8 && J == 8) { + return threadIdx.x / 4; + } else if constexpr (I == 16 && J == 4) { + return l * 8 + threadIdx.x / 4; + } else if constexpr (I == 16 && J == 8) { + return (l % 2) * 8 + threadIdx.x / 4; + } else { + static_assert(I == -1 && J == -1, "template specialization not implemented"); + } + } + + static __device__ __forceinline__ int get_j(const int l) { + if constexpr (I == 8 && J == 8) { + return l * 4 + threadIdx.x % 4; + } else if constexpr (I == 16 && J == 4) { + return threadIdx.x % 4; + } else if constexpr (I == 16 && J == 8) { + return (l / 2) * 4 + threadIdx.x % 4; + } else { + static_assert(I == -1 && J == -1, "template specialization not implemented"); + } + } + }; + template static __device__ __forceinline__ tile get_half2(const tile & tile_float) { tile ret; @@ -148,16 +219,29 @@ namespace ggml_cuda_mma { template static __device__ __forceinline__ void load_generic(tile & t, const T * __restrict__ xs0, const int stride) { +#if defined(AMD_MFMA_AVAILABLE) + if constexpr (I == 64 && J == 2) { // Special tile size to load <16, 4> as <16, 8> +#pragma unroll + for (int l = 0; l < t.ne; ++l) { + t.x[l] = xs0[t.get_i(l)*stride + t.get_j(l)]; + } + } else { + int64_t * xi = (int64_t *) t.x; + const int64_t * xs = (int64_t *) ((const int *) xs0 + (threadIdx.x % t.I) * stride + 2 * (threadIdx.x / t.I)); + xi[0] = xs[0]; + } +#else #pragma unroll for (int l = 0; l < t.ne; ++l) { t.x[l] = xs0[t.get_i(l)*stride + t.get_j(l)]; } +#endif // defined(AMD_MFMA_AVAILABLE) } template static __device__ __forceinline__ void load_ldmatrix( tile<8, 8, T> & t, const T * __restrict__ xs0, const int stride) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE int * xi = (int *) t.x; const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride + ((threadIdx.x / t.I) * (t.J / 2)) % t.J; asm volatile("ldmatrix.sync.aligned.m8n8.x2.b16 {%0, %1}, [%2];" @@ -165,13 +249,13 @@ namespace ggml_cuda_mma { : "l"(xs)); #else load_generic(t, xs0, stride); -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } template static __device__ __forceinline__ void load_ldmatrix( tile<16, 4, T> & t, const T * __restrict__ xs0, const int stride) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE int * xi = (int *) t.x; const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride; asm volatile("ldmatrix.sync.aligned.m8n8.x2.b16 {%0, %1}, [%2];" @@ -180,13 +264,13 @@ namespace ggml_cuda_mma { #else load_generic(xs0, stride); GGML_UNUSED(t); -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } template static __device__ __forceinline__ void load_ldmatrix( tile<16, 8, T> & t, const T * __restrict__ xs0, const int stride) { -#ifdef NEW_MMA_AVAILABLE +#if defined(TURING_MMA_AVAILABLE) int * xi = (int * ) t.x; const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride + (threadIdx.x / t.I) * (t.J / 2); asm volatile("ldmatrix.sync.aligned.m8n8.x4.b16 {%0, %1, %2, %3}, [%4];" @@ -194,13 +278,13 @@ namespace ggml_cuda_mma { : "l"(xs)); #else load_generic(t, xs0, stride); -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } template static __device__ __forceinline__ void load_ldmatrix_trans( tile<16, 8, T> & t, const T * __restrict__ xs0, const int stride) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE int * xi = (int * ) t.x; const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride + (threadIdx.x / t.I) * (t.J / 2); asm volatile("ldmatrix.sync.aligned.m8n8.x4.trans.b16 {%0, %1, %2, %3}, [%4];" @@ -211,12 +295,12 @@ namespace ggml_cuda_mma { GGML_UNUSED(xs0); GGML_UNUSED(stride); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 8, int> & D, const tile<16, 4, int> & A, const tile<8, 4, int> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE #if __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE asm("mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32 {%0, %1, %2, %3}, {%4, %5}, {%6}, {%0, %1, %2, %3};" : "+r"(D.x[0]), "+r"(D.x[1]), "+r"(D.x[2]), "+r"(D.x[3]) @@ -235,12 +319,12 @@ namespace ggml_cuda_mma { GGML_UNUSED(A); GGML_UNUSED(B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 8, int> & D, const tile<16, 8, int> & A, const tile<8, 8, int> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE #if __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE asm("mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};" : "+r"(D.x[0]), "+r"(D.x[1]), "+r"(D.x[2]), "+r"(D.x[3]) @@ -265,12 +349,12 @@ namespace ggml_cuda_mma { GGML_UNUSED(A); GGML_UNUSED(B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 4, half2> & D, const tile<16, 8, half2> & A, const tile<8, 8, half2> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE const int * Axi = (const int *) A.x; const int * Bxi = (const int *) B.x; int * Dxi = (int *) D.x; @@ -292,12 +376,12 @@ namespace ggml_cuda_mma { GGML_UNUSED(A); GGML_UNUSED(B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 8, half2> & D, const tile<16, 8, half2> & A, const tile<16, 8, half2> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE const int * Axi = (const int *) A.x; const int * Bxi = (const int *) B.x; int * Dxi = (int *) D.x; @@ -328,12 +412,29 @@ namespace ggml_cuda_mma { GGML_UNUSED(A); GGML_UNUSED(B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE + } + + static __device__ __forceinline__ void mma( + tile<16, 8, float> & D, const tile<16, 8, float> & A, const tile<8, 8, float> & B) { +#ifdef AMPERE_MMA_AVAILABLE + const int * Axi = (const int *) A.x; + const int * Bxi = (const int *) B.x; + int * Dxi = (int *) D.x; + asm("mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};" + : "+r"(Dxi[0]), "+r"(Dxi[1]), "+r"(Dxi[2]), "+r"(Dxi[3]) + : "r"(Axi[0]), "r"(Axi[1]), "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[0]), "r"(Bxi[1])); +#else + GGML_UNUSED(D); + GGML_UNUSED(A); + GGML_UNUSED(B); + NO_DEVICE_CODE; +#endif // AMPERE_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 8, float> & D, const tile<16, 8, half2> & A, const tile<8, 8, half2> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE const int * Axi = (const int *) A.x; const int * Bxi = (const int *) B.x; int * Dxi = (int *) D.x; @@ -355,12 +456,29 @@ namespace ggml_cuda_mma { GGML_UNUSED(A); GGML_UNUSED(B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE + } + + static __device__ __forceinline__ void mma( + tile<16, 8, float> & D, const tile<16, 8, nv_bfloat162> & A, const tile<8, 8, nv_bfloat162> & B) { +#ifdef AMPERE_MMA_AVAILABLE + const int * Axi = (const int *) A.x; + const int * Bxi = (const int *) B.x; + int * Dxi = (int *) D.x; + asm("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};" + : "+r"(Dxi[0]), "+r"(Dxi[1]), "+r"(Dxi[2]), "+r"(Dxi[3]) + : "r"(Axi[0]), "r"(Axi[1]), "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[0]), "r"(Bxi[1])); +#else + GGML_UNUSED(D); + GGML_UNUSED(A); + GGML_UNUSED(B); + NO_DEVICE_CODE; +#endif // AMPERE_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 16, float> & D, const tile<16, 8, half2> & A, const tile<16, 8, half2> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE const int * Axi = (const int *) A.x; const int * Bxi = (const int *) B.x; int * Dxi = (int *) D.x; @@ -391,6 +509,62 @@ namespace ggml_cuda_mma { GGML_UNUSED(A); GGML_UNUSED(B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE + } + + static __device__ __forceinline__ void mma( + tile<16, 16, int> & D, const tile<16, 8, int> & A, const tile<16, 8, int> & B) { +#if defined(AMD_MFMA_AVAILABLE) + using int32x4_t = __attribute__((__vector_size__(4 * sizeof(int)))) int; + int32x4_t * acc = (int32x4_t *) D.x; +#if defined(CDNA3) + acc[0] = __builtin_amdgcn_mfma_i32_16x16x32_i8(((int64_t *) A.x)[0], + ((int64_t *) B.x)[0], + acc[0], + 0, 0, 0); +#elif defined(CDNA2) || defined(CDNA) + acc[0] = __builtin_amdgcn_mfma_i32_16x16x16i8(A.x[0], + B.x[0], + acc[0], + 0, 0, 0); + acc[0] = __builtin_amdgcn_mfma_i32_16x16x16i8(A.x[1], + B.x[1], + acc[0], + 0, 0, 0); +#endif // defined(CDNA3) +#else + GGML_UNUSED(D); + GGML_UNUSED(A); + GGML_UNUSED(B); + NO_DEVICE_CODE; +#endif // AMD_MFMA_AVAILABLE + } + + static __device__ __forceinline__ void mma( + tile<32, 32, int> & D, const tile<32, 4, int> & A, const tile<32, 4, int> & B) { +#if defined(AMD_MFMA_AVAILABLE) + using int32x16_t = __attribute__((__vector_size__(16 * sizeof(int)))) int; + int32x16_t * acc = (int32x16_t *) D.x; +#if defined(CDNA3) + acc[0] = __builtin_amdgcn_mfma_i32_32x32x16_i8(((int64_t *) A.x)[0], + ((int64_t *) B.x)[0], + acc[0], + 0, 0, 0); +#elif defined(CDNA2) || defined(CDNA) + acc[0] = __builtin_amdgcn_mfma_i32_32x32x8i8(A.x[0], + B.x[0], + acc[0], + 0, 0, 0); + acc[0] = __builtin_amdgcn_mfma_i32_32x32x8i8(A.x[1], + B.x[1], + acc[0], + 0, 0, 0); +#endif // defined(CDNA3) +#else + GGML_UNUSED(D); + GGML_UNUSED(A); + GGML_UNUSED(B); + NO_DEVICE_CODE; +#endif // AMD_MFMA_AVAILABLE } } diff --git a/ggml/src/ggml-cuda/mmf.cu b/ggml/src/ggml-cuda/mmf.cu new file mode 100644 index 0000000000..1437367e87 --- /dev/null +++ b/ggml/src/ggml-cuda/mmf.cu @@ -0,0 +1,431 @@ +#include "ggml.h" +#include "common.cuh" +#include "mma.cuh" +#include "mmf.cuh" + +using namespace ggml_cuda_mma; + +#define MMF_ROWS_PER_BLOCK 32 + +template +__launch_bounds__(ggml_cuda_get_physical_warp_size()*nwarps, 1) +static __global__ void mul_mat_f( + const T * __restrict__ x, const float * __restrict__ y, const int32_t * __restrict__ ids, float * __restrict__ dst, + const int ncols, const int nchannels_y, const int stride_row, const int stride_col_y, const int stride_col_dst, + const int channel_ratio, const int stride_channel_x, const int stride_channel_y, const int stride_channel_dst, + const int sample_ratio, const int stride_sample_x, const int stride_sample_y, const int stride_sample_dst) { +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) + typedef tile<16, 8, T> tile_A; + typedef tile< 8, 8, T> tile_B; + typedef tile<16, 8, float> tile_C; + + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + constexpr int tile_k_padded = warp_size + 4; + constexpr int ntA = rows_per_block / tile_A::I; + constexpr int ntB = (cols_per_block + tile_B::I - 1) / tile_B::I; + + const int row0 = blockIdx.x * rows_per_block; + const int channel_dst = blockIdx.y; + const int channel_x = channel_dst / channel_ratio; + const int channel_y = channel_dst; + const int sample_dst = blockIdx.z; + const int sample_x = sample_dst / sample_ratio; + const int sample_y = sample_dst; + + x += int64_t(sample_x) *stride_sample_x + channel_x *stride_channel_x + row0*stride_row ; + y += int64_t(sample_y) *stride_sample_y + channel_y *stride_channel_y; + dst += int64_t(sample_dst)*stride_sample_dst + channel_dst*stride_channel_dst; + + const float2 * y2 = (const float2 *) y; + + extern __shared__ char data_mmv[]; + + tile_C C[ntA][ntB]; + + T * tile_xy = (T *) data_mmv + threadIdx.y*(tile_A::I * tile_k_padded); + + for (int col = threadIdx.y*warp_size + threadIdx.x; col < ncols; col += nwarps*warp_size) { + tile_A A[ntA][warp_size / tile_A::J]; +#pragma unroll + for (int itA = 0; itA < ntA; ++itA) { +#pragma unroll + for (int i = 0; i < tile_A::I; ++i) { + tile_xy[i*tile_k_padded + threadIdx.x] = x[(itA*tile_A::I + i)*stride_row + col]; + } +#pragma unroll + for (int k0 = 0; k0 < warp_size; k0 += tile_A::J) { + load_ldmatrix(A[itA][k0/tile_A::J], tile_xy + k0, tile_k_padded); + } + } + +#pragma unroll + for (int itB = 0; itB < ntB; ++itB) { + if constexpr (std::is_same_v) { +#pragma unroll + for (int j0 = 0; j0 < tile_B::I; ++j0) { + const int j = j0 + itB*tile_B::I; + + tile_xy[j0*tile_k_padded + threadIdx.x] = j < cols_per_block ? y[j*stride_col_y + col] : 0.0f; + } + } else if constexpr (std::is_same_v || std::is_same_v) { +#pragma unroll + for (int j0 = 0; j0 < tile_B::I; ++j0) { + const int j = j0 + itB*tile_B::I; + + const float2 tmp = j < cols_per_block ? y2[j*stride_col_y + col] : make_float2(0.0f, 0.0f); + tile_xy[j0*tile_k_padded + threadIdx.x] = {tmp.x, tmp.y}; + } + } else { + static_assert(std::is_same_v, "unsupported type"); + } +#pragma unroll + for (int k0 = 0; k0 < warp_size; k0 += tile_B::J) { + tile_B B; + load_ldmatrix(B, tile_xy + k0, tile_k_padded); +#pragma unroll + for (int itA = 0; itA < ntA; ++itA) { + mma(C[itA][itB], A[itA][k0/tile_B::J], B); + } + } + } + } + + float * buf_iw = (float *) data_mmv; + constexpr int kiw = nwarps*rows_per_block + 4; + + if (nwarps > 1) { + __syncthreads(); + } +#pragma unroll + for (int itB = 0; itB < ntB; ++itB) { +#pragma unroll + for (int itA = 0; itA < ntA; ++itA) { +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = threadIdx.y*rows_per_block + itA*tile_C::I + tile_C::get_i(l); + const int j = itB*tile_C::J + tile_C::get_j(l); + buf_iw[j*kiw + i] = C[itA][itB].x[l]; + } + } + } + + if (nwarps > 1) { + __syncthreads(); + } + +#pragma unroll + for (int j0 = 0; j0 < cols_per_block; j0 += nwarps) { + const int j = j0 + threadIdx.y; + + if (j0 + nwarps > cols_per_block && j >= cols_per_block) { + return; + } + + float sum = 0.0f; + static_assert(rows_per_block == warp_size, "need loop/check"); +#pragma unroll + for (int i0 = 0; i0 < nwarps*rows_per_block; i0 += rows_per_block) { + const int i = i0 + threadIdx.x; + + sum += buf_iw[j*kiw + i]; + } + dst[j*stride_col_dst + row0 + threadIdx.x] = sum; + } +#else + NO_DEVICE_CODE; + GGML_UNUSED(x); GGML_UNUSED(y); GGML_UNUSED(ids); GGML_UNUSED(dst); + GGML_UNUSED(ncols); GGML_UNUSED(nchannels_y); GGML_UNUSED(stride_row); GGML_UNUSED(stride_col_y); GGML_UNUSED(stride_col_dst); + GGML_UNUSED(channel_ratio); GGML_UNUSED(stride_channel_x); GGML_UNUSED(stride_channel_y); GGML_UNUSED(stride_channel_dst); + GGML_UNUSED(sample_ratio); GGML_UNUSED(stride_sample_x); GGML_UNUSED(stride_sample_y); GGML_UNUSED(stride_sample_dst); +#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) +} + +template +static void mul_mat_f_cuda( + const T * x, const float * y, const int32_t * ids, float * dst, + const int64_t ncols_x, const int64_t nrows_x, + const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, + const int64_t nchannels_x, const int64_t nchannels_y, const int64_t nchannels_dst, + const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x, + const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, + cudaStream_t stream) { + typedef tile<16, 8, T> tile_A; + typedef tile< 8, 8, T> tile_B; + typedef tile<16, 8, float> tile_C; + + GGML_ASSERT(!ids && "mul_mat_id not implemented"); + + GGML_ASSERT(ncols_x % 2 == 0); + GGML_ASSERT(stride_row % 2 == 0); + GGML_ASSERT(stride_col_y % 2 == 0); + GGML_ASSERT(ids || nchannels_dst % nchannels_x == 0); + GGML_ASSERT( nsamples_dst % nsamples_x == 0); + const int64_t channel_ratio = nchannels_dst / nchannels_x; + const int64_t sample_ratio = nsamples_dst / nsamples_x; + + const int device = ggml_cuda_get_device(); + const int warp_size = ggml_cuda_info().devices[device].warp_size; + + int64_t nwarps_best = 1; + int64_t niter_best = (ncols_x + warp_size*2 - 1) / (warp_size*2); + int64_t max_block_size = 256; + for (int64_t nwarps = 2; nwarps <= max_block_size/warp_size; nwarps++) { + const int64_t niter = (ncols_x + nwarps*warp_size*2 - 1) / (nwarps*warp_size*2); + if (niter < niter_best) { + niter_best = niter; + nwarps_best = nwarps; + } + } + + constexpr int rows_per_block = MMF_ROWS_PER_BLOCK; + const int nbytes_shared_iter = nwarps_best * tile_A::I * (warp_size + 4) * 4; + const int nbytes_shared_combine = GGML_PAD(cols_per_block, tile_B::I) * (nwarps_best*rows_per_block + 4) * 4; + const int nbytes_shared = std::max(nbytes_shared_iter, nbytes_shared_combine); + const dim3 block_nums(nrows_x/rows_per_block, nchannels_dst, nsamples_dst); + const dim3 block_dims(warp_size, nwarps_best, 1); + switch (nwarps_best) { + case 1: { + mul_mat_f<<>> + (x, y, ids, dst, ncols_x, nchannels_y, stride_row, stride_col_y, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 2: { + mul_mat_f<<>> + (x, y, ids, dst, ncols_x, nchannels_y, stride_row, stride_col_y, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 3: { + mul_mat_f<<>> + (x, y, ids, dst, ncols_x, nchannels_y, stride_row, stride_col_y, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 4: { + mul_mat_f<<>> + (x, y, ids, dst, ncols_x, nchannels_y, stride_row, stride_col_y, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 5: { + mul_mat_f<<>> + (x, y, ids, dst, ncols_x, nchannels_y, stride_row, stride_col_y, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 6: { + mul_mat_f<<>> + (x, y, ids, dst, ncols_x, nchannels_y, stride_row, stride_col_y, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 7: { + mul_mat_f<<>> + (x, y, ids, dst, ncols_x, nchannels_y, stride_row, stride_col_y, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 8: { + mul_mat_f<<>> + (x, y, ids, dst, ncols_x, nchannels_y, stride_row, stride_col_y, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + default: { + GGML_ABORT("fatal error"); + } break; + } +} + +template +static void mul_mat_f_switch_cols_per_block( + const T * x, const float * y, const int32_t * ids, float * dst, + const int64_t ncols_x, const int64_t nrows_x, const int64_t ncols_dst, + const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, + const int64_t nchannels_x, const int64_t nchannels_y, const int64_t nchannels_dst, + const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x, + const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, + cudaStream_t stream) { + switch (ncols_dst) { + case 1: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 2: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 3: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 4: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 5: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 6: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 7: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 8: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 9: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 10: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 11: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 12: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 13: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 14: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 15: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 16: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + default: { + GGML_ABORT("fatal error"); + } break; + } +} + +void ggml_cuda_mul_mat_f(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst) { + GGML_ASSERT( src1->type == GGML_TYPE_F32); + GGML_ASSERT(!ids || ids->type == GGML_TYPE_I32); + GGML_ASSERT( dst->type == GGML_TYPE_F32); + + GGML_TENSOR_BINARY_OP_LOCALS; + + const size_t ts_src0 = ggml_type_size(src0->type); + const size_t ts_src1 = ggml_type_size(src1->type); + const size_t ts_dst = ggml_type_size(dst->type); + + GGML_ASSERT(ne13 == ne3); + + GGML_ASSERT( nb00 == ts_src0); + GGML_ASSERT( nb10 == ts_src1); + GGML_ASSERT(!ids || ids->nb[0] == ggml_type_size(ids->type)); + GGML_ASSERT( nb0 == ts_dst); + + const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; + const enum ggml_prec prec = fast_fp16_available(cc) ? ggml_prec(dst->op_params[0]) : GGML_PREC_F32; + + const float * src1_d = (const float *) src1->data; + const int32_t * ids_d = ids ? (const int32_t *) ids->data : nullptr; + float * dst_d = (float *) dst->data; + + const int64_t s01 = src0->nb[1] / ts_src0; + const int64_t s11 = src1->nb[1] / ts_src1; + const int64_t s1 = dst->nb[1] / ts_dst; + const int64_t s02 = src0->nb[2] / ts_src0; + const int64_t s12 = src1->nb[2] / ts_src1; + const int64_t s2 = dst->nb[2] / ts_dst; + const int64_t s03 = src0->nb[3] / ts_src0; + const int64_t s13 = src1->nb[3] / ts_src1; + const int64_t s3 = dst->nb[3] / ts_dst; + + // For MUL_MAT_ID the memory layout is different than for MUL_MAT: + const int64_t ncols_dst = ids ? ne2 : ne1; + const int64_t nchannels_y = ids ? ne11 : ne12; + const int64_t nchannels_dst = ids ? ne1 : ne2; + const int64_t stride_channel_dst = ids ? s1 : s2; + const int64_t stride_channel_y = ids ? s11 : s12; + + GGML_ASSERT(!ids || ncols_dst == 1); + + switch (src0->type) { + case GGML_TYPE_F32: { + const float * src0_d = (const float *) src0->data; + constexpr int vals_per_T = 1; + mul_mat_f_switch_cols_per_block( + src0_d, src1_d, ids_d, dst_d, ne00/vals_per_T, ne01, ncols_dst, s01/vals_per_T, s11/vals_per_T, s1, + ne02, nchannels_y, nchannels_dst, s02/vals_per_T, stride_channel_y, stride_channel_dst, + ne03, ne3, s03/vals_per_T, s13, s3, ctx.stream()); + } break; + case GGML_TYPE_F16: { + const half2 * src0_d = (const half2 *) src0->data; + constexpr int vals_per_T = 2; + mul_mat_f_switch_cols_per_block( + src0_d, src1_d, ids_d, dst_d, ne00/vals_per_T, ne01, ncols_dst, s01/vals_per_T, s11/vals_per_T, s1, + ne02, nchannels_y, nchannels_dst, s02/vals_per_T, stride_channel_y, stride_channel_dst, + ne03, ne3, s03/vals_per_T, s13, s3, ctx.stream()); + } break; + case GGML_TYPE_BF16: { + const nv_bfloat162 * src0_d = (const nv_bfloat162 *) src0->data; + constexpr int vals_per_T = 2; + mul_mat_f_switch_cols_per_block( + src0_d, src1_d, ids_d, dst_d, ne00/vals_per_T, ne01, ncols_dst, s01/vals_per_T, s11/vals_per_T, s1, + ne02, nchannels_y, nchannels_dst, s02/vals_per_T, stride_channel_y, stride_channel_dst, + ne03, ne3, s03/vals_per_T, s13, s3, ctx.stream()); + } break; + default: + GGML_ABORT("unsupported type: %s", ggml_type_name(src0->type)); + } +} + +bool ggml_cuda_should_use_mmf(enum ggml_type type, int cc, int warp_size, const int64_t * src0_ne, int64_t ne11) { + if (src0_ne[0] % (warp_size * (4/ggml_type_size(type))) != 0) { + return false; + } + if (src0_ne[1] % MMF_ROWS_PER_BLOCK != 0) { + return false; + } + if (ne11 > 16) { + return false; + } + switch (type) { + case GGML_TYPE_F32: + return ampere_mma_available(cc); + case GGML_TYPE_F16: + return turing_mma_available(cc); + case GGML_TYPE_BF16: + return ampere_mma_available(cc); + default: + return false; + } +} diff --git a/ggml/src/ggml-cuda/mmf.cuh b/ggml/src/ggml-cuda/mmf.cuh new file mode 100644 index 0000000000..785f9f211c --- /dev/null +++ b/ggml/src/ggml-cuda/mmf.cuh @@ -0,0 +1,5 @@ +#include "common.cuh" + +void ggml_cuda_mul_mat_f(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst); + +bool ggml_cuda_should_use_mmf(enum ggml_type type, int cc, int warp_size, const int64_t * scr0_ne, int64_t ne11); diff --git a/ggml/src/ggml-cuda/mmq.cu b/ggml/src/ggml-cuda/mmq.cu index 2db5b4ab0f..384ee7615f 100644 --- a/ggml/src/ggml-cuda/mmq.cu +++ b/ggml/src/ggml-cuda/mmq.cu @@ -20,6 +20,9 @@ static void ggml_cuda_mul_mat_q_switch_type(ggml_backend_cuda_context & ctx, con case GGML_TYPE_Q8_0: mul_mat_q_case(ctx, args, stream); break; + case GGML_TYPE_MXFP4: + mul_mat_q_case(ctx, args, stream); + break; case GGML_TYPE_Q2_K: mul_mat_q_case(ctx, args, stream); break; @@ -109,7 +112,8 @@ void ggml_cuda_mul_mat_q( const int64_t s03 = src0->nb[3] / ts_src0; const int64_t s3 = dst->nb[3] / ts_dst; - const bool use_stream_k = GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA; + const bool use_stream_k = (GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA) + || GGML_CUDA_CC_IS_CDNA(cc); if (!ids) { const size_t nbytes_src1_q8_1 = ne13*ne12 * ne11*ne10_padded * sizeof(block_q8_1)/QK8_1 + @@ -250,8 +254,9 @@ void ggml_cuda_op_mul_mat_q( // The stream-k decomposition is only faster for recent NVIDIA GPUs. // Also its fixup needs to allocate a temporary buffer in the memory pool. // There are multiple parallel CUDA streams for src1_ncols != ne11 which would introduce a race condition for this buffer. - const bool use_stream_k = GGML_CUDA_CC_IS_NVIDIA(cc) && - ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA && src1_ncols == ne11; + const bool use_stream_k = ((GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA) + || GGML_CUDA_CC_IS_CDNA(cc)) + && src1_ncols == ne11; const mmq_args args = { src0_dd_i, src0->type, (const int *) src1_ddq_i, nullptr, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride01, ne11, nrows_dst, @@ -280,6 +285,7 @@ bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11) { case GGML_TYPE_Q5_0: case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -304,7 +310,7 @@ bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11) { return false; } - if (new_mma_available(cc)) { + if (turing_mma_available(cc)) { return true; } @@ -320,5 +326,21 @@ bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11) { return !fp16_mma_hardware_available(cc) || ne11 < MMQ_DP4A_MAX_BATCH_SIZE; } + if (amd_mfma_available(cc)) { + // As of ROCM 7.0 rocblas/tensile performs very poorly on CDNA3 and hipblaslt (via ROCBLAS_USE_HIPBLASLT) + // performs better but is currently suffering from a crash on this architecture. + // TODO: Revisit when hipblaslt is fixed on CDNA3 + if (GGML_CUDA_CC_IS_CDNA3(cc)) { + return true; + } + if (ne11 <= 128 || type == GGML_TYPE_Q4_0 || type == GGML_TYPE_Q4_1 || type == GGML_TYPE_Q5_0 || type == GGML_TYPE_Q5_1) { + return true; + } + if (ne11 <= 256 && (type == GGML_TYPE_Q4_K || type == GGML_TYPE_Q5_K)) { + return true; + } + return false; + } + return (!GGML_CUDA_CC_IS_RDNA4(cc) && !GGML_CUDA_CC_IS_RDNA3(cc) && !GGML_CUDA_CC_IS_CDNA(cc)) || ne11 < MMQ_DP4A_MAX_BATCH_SIZE; } diff --git a/ggml/src/ggml-cuda/mmq.cuh b/ggml/src/ggml-cuda/mmq.cuh index 9696a32046..96129bd831 100644 --- a/ggml/src/ggml-cuda/mmq.cuh +++ b/ggml/src/ggml-cuda/mmq.cuh @@ -58,6 +58,8 @@ static mmq_q8_1_ds_layout mmq_get_q8_1_ds_layout(const ggml_type type_x) { return MMQ_Q8_1_DS_LAYOUT_DS4; case GGML_TYPE_Q8_0: return MMQ_Q8_1_DS_LAYOUT_D4; + case GGML_TYPE_MXFP4: + return MMQ_Q8_1_DS_LAYOUT_D4; case GGML_TYPE_Q2_K: return MMQ_Q8_1_DS_LAYOUT_D2S6; case GGML_TYPE_Q3_K: @@ -90,7 +92,7 @@ struct tile_x_sizes { }; static int get_mmq_x_max_host(const int cc) { - return new_mma_available(cc) ? 128 : + return (amd_mfma_available(cc) || turing_mma_available(cc)) ? 128 : GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA ? #ifdef GGML_CUDA_FORCE_MMQ 128 : 64; @@ -100,13 +102,13 @@ static int get_mmq_x_max_host(const int cc) { } static constexpr __device__ int get_mmq_x_max_device() { -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) return 128; -#else // NEW_MMA_AVAILABLE +#else // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) - return 128; -#else // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) + return 64; +#else // defined(GGML_USE_HIP) #if __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA #ifdef GGML_CUDA_FORCE_MMQ @@ -115,12 +117,11 @@ static constexpr __device__ int get_mmq_x_max_device() { return MMQ_DP4A_MAX_BATCH_SIZE; #endif // GGML_CUDA_FORCE_MMQ #else // __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA - return 64; #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) -#endif // NEW_MMA_AVAILABLE +#endif // defined(GGML_USE_HIP) +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } static int get_mmq_y_host(const int cc) { @@ -129,7 +130,7 @@ static int get_mmq_y_host(const int cc) { } static constexpr __device__ int get_mmq_y_device() { -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) #if defined(RDNA1) return 64; #else @@ -141,19 +142,28 @@ static constexpr __device__ int get_mmq_y_device() { #else return 64; #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#endif // defined(GGML_USE_HIP) } -#define MMQ_DP4A_TXS_Q4_0 tile_x_sizes{mmq_y*WARP_SIZE + mmq_y, mmq_y*WARP_SIZE/QI4_0 + mmq_y/QI4_0, 0} -#define MMQ_DP4A_TXS_Q4_1 tile_x_sizes{mmq_y*WARP_SIZE + mmq_y, mmq_y*WARP_SIZE/QI4_1 + mmq_y/QI4_1, 0} -#define MMQ_DP4A_TXS_Q8_0 tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE*2/QI8_0 + mmq_y/(QI8_0/2), 0} -#define MMQ_DP4A_TXS_Q8_0_16 tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE*4/QI8_0 + mmq_y/(QI8_0/4), 0} -#define MMQ_DP4A_TXS_Q8_1 tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE*2/QI8_1 + mmq_y/(QI8_1/2), 0} -#define MMQ_DP4A_TXS_Q2_K tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE + mmq_y, 0} -#define MMQ_DP4A_TXS_Q3_K tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y, mmq_y*WARP_SIZE/8 + mmq_y/8} -#define MMQ_DP4A_TXS_Q4_K tile_x_sizes{mmq_y*WARP_SIZE + mmq_y, mmq_y*WARP_SIZE/QI4_K, mmq_y*WARP_SIZE/8 + mmq_y/8} -#define MMQ_DP4A_TXS_Q5_K tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE/QI5_K + mmq_y/QI5_K, mmq_y*WARP_SIZE/8 + mmq_y/8} -#define MMQ_DP4A_TXS_Q6_K tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE/QI6_K + mmq_y/QI6_K, mmq_y*WARP_SIZE/8 + mmq_y/8} +// Decouple shared memory tile sizes from WARP_SIZE to allow for different warp sizes. +// The K dimension of the tiles has either, +// 1*MMQ_TILE_NE_K==32 (always for TILE_Y_K) or 2*MMQ_TILE_NE_K==64 (typically for TILE_X_K), +// 32 bit elements for the quantized data (does not include scales). +// In other words, the size of the quantized data in the K dimension is a multiple of MMQ_TILE_NE_K. +// The final tile size in K direction is padded to avoid shared memory bank conflicts, +// in terms of 32 bit elements that means K % 2 == 1 for dp4a or K % 8 == 4 for mma. +#define MMQ_TILE_NE_K 32 + +#define MMQ_DP4A_TXS_Q4_0 tile_x_sizes{mmq_y*MMQ_TILE_NE_K + mmq_y, mmq_y*MMQ_TILE_NE_K/QI4_0 + mmq_y/QI4_0, 0} +#define MMQ_DP4A_TXS_Q4_1 tile_x_sizes{mmq_y*MMQ_TILE_NE_K + mmq_y, mmq_y*MMQ_TILE_NE_K/QI4_1 + mmq_y/QI4_1, 0} +#define MMQ_DP4A_TXS_Q8_0 tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K*2/QI8_0 + mmq_y/(QI8_0/2), 0} +#define MMQ_DP4A_TXS_Q8_0_16 tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K*4/QI8_0 + mmq_y/(QI8_0/4), 0} +#define MMQ_DP4A_TXS_Q8_1 tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K*2/QI8_1 + mmq_y/(QI8_1/2), 0} +#define MMQ_DP4A_TXS_Q2_K tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K + mmq_y, 0} +#define MMQ_DP4A_TXS_Q3_K tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y, mmq_y*MMQ_TILE_NE_K/8 + mmq_y/8} +#define MMQ_DP4A_TXS_Q4_K tile_x_sizes{mmq_y*MMQ_TILE_NE_K + mmq_y, mmq_y*MMQ_TILE_NE_K/QI4_K, mmq_y*MMQ_TILE_NE_K/8 + mmq_y/8} +#define MMQ_DP4A_TXS_Q5_K tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K/QI5_K + mmq_y/QI5_K, mmq_y*MMQ_TILE_NE_K/8 + mmq_y/8} +#define MMQ_DP4A_TXS_Q6_K tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K/QI6_K + mmq_y/QI6_K, mmq_y*MMQ_TILE_NE_K/8 + mmq_y/8} static constexpr __host__ __device__ tile_x_sizes mmq_get_dp4a_tile_x_sizes(ggml_type type, int mmq_y) { switch (type) { @@ -162,6 +172,7 @@ static constexpr __host__ __device__ tile_x_sizes mmq_get_dp4a_tile_x_sizes(ggml case GGML_TYPE_Q5_0: return MMQ_DP4A_TXS_Q8_0; case GGML_TYPE_Q5_1: return MMQ_DP4A_TXS_Q8_1; case GGML_TYPE_Q8_0: return MMQ_DP4A_TXS_Q8_0; + case GGML_TYPE_MXFP4: return MMQ_DP4A_TXS_Q8_1; case GGML_TYPE_Q2_K: return MMQ_DP4A_TXS_Q2_K; case GGML_TYPE_Q3_K: return MMQ_DP4A_TXS_Q3_K; case GGML_TYPE_Q4_K: return MMQ_DP4A_TXS_Q4_K; @@ -179,11 +190,11 @@ static constexpr __host__ __device__ tile_x_sizes mmq_get_dp4a_tile_x_sizes(ggml } } -#define MMQ_MMA_TILE_X_K_Q8_0 (2*WARP_SIZE + 2*WARP_SIZE/QI8_0 + 4) -#define MMQ_MMA_TILE_X_K_Q8_1 (2*WARP_SIZE + 2*WARP_SIZE/QI8_0 + 4) -#define MMQ_MMA_TILE_X_K_Q2_K (2*WARP_SIZE + WARP_SIZE + 4) -#define MMQ_MMA_TILE_X_K_Q3_K (2*WARP_SIZE + WARP_SIZE/2 + 4) -#define MMQ_MMA_TILE_X_K_Q6_K (2*WARP_SIZE + WARP_SIZE/QI6_K + WARP_SIZE/8 + 7) +#define MMQ_MMA_TILE_X_K_Q8_0 (2*MMQ_TILE_NE_K + 2*MMQ_TILE_NE_K/QI8_0 + 4) +#define MMQ_MMA_TILE_X_K_Q8_1 (2*MMQ_TILE_NE_K + 2*MMQ_TILE_NE_K/QI8_0 + 4) +#define MMQ_MMA_TILE_X_K_Q2_K (2*MMQ_TILE_NE_K + MMQ_TILE_NE_K + 4) +#define MMQ_MMA_TILE_X_K_Q3_K (2*MMQ_TILE_NE_K + MMQ_TILE_NE_K/2 + 4) +#define MMQ_MMA_TILE_X_K_Q6_K (2*MMQ_TILE_NE_K + MMQ_TILE_NE_K/QI6_K + MMQ_TILE_NE_K/8 + 7) static_assert(MMQ_MMA_TILE_X_K_Q8_0 % 8 == 4, "Wrong padding."); static_assert(MMQ_MMA_TILE_X_K_Q8_1 % 8 == 4, "Wrong padding."); @@ -198,6 +209,7 @@ static constexpr __host__ __device__ int mmq_get_mma_tile_x_k(ggml_type type) { case GGML_TYPE_Q5_0: return MMQ_MMA_TILE_X_K_Q8_0; case GGML_TYPE_Q5_1: return MMQ_MMA_TILE_X_K_Q8_1; case GGML_TYPE_Q8_0: return MMQ_MMA_TILE_X_K_Q8_0; + case GGML_TYPE_MXFP4: return MMQ_MMA_TILE_X_K_Q8_1; case GGML_TYPE_Q2_K: return MMQ_MMA_TILE_X_K_Q2_K; case GGML_TYPE_Q3_K: return MMQ_MMA_TILE_X_K_Q3_K; case GGML_TYPE_Q4_K: return MMQ_MMA_TILE_X_K_Q8_1; @@ -215,42 +227,76 @@ static constexpr __host__ __device__ int mmq_get_mma_tile_x_k(ggml_type type) { } } -#define MMQ_TILE_Y_K (WARP_SIZE + WARP_SIZE/QI8_1) +// block_q8_1_mmq has (128 8-bit ints == 32 32-bit ints + 4 32-bit scales) +#define MMQ_TILE_Y_K (MMQ_TILE_NE_K + MMQ_TILE_NE_K/QI8_1) static int mmq_get_granularity_host(const int mmq_x, const int cc) { - return new_mma_available(cc) && mmq_x >= 48 ? 16 : 8; + if (amd_mfma_available(cc)) { + return mmq_x >= 128 ? 32 : 16; + } else if (turing_mma_available(cc) && mmq_x >= 48) { + return 16; + } else { + return 8; + } } -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) +static constexpr __device__ int mmq_get_granularity_device(const int mmq_x) { + return mmq_x >= 128 ? 32 : 16; +} +#elif defined(TURING_MMA_AVAILABLE) static constexpr __device__ int mmq_get_granularity_device(const int mmq_x) { return mmq_x >= 48 ? 16 : 8; } #else -static constexpr __device__ int mmq_get_granularity_device(const int /* mmq_x */) { +static constexpr __device__ int mmq_get_granularity_device(const int /*mmq_x*/) { return 8; } -#endif // NEW_MMA_AVAILABLE +#endif // AMD_MFMA_AVAILABLE + +#if defined(GGML_USE_HIP) +static int mmq_get_nwarps_host(const int cc, const int warp_size) { + return amd_mfma_available(cc) ? 8 : 256/warp_size; +} +#else +static int mmq_get_nwarps_host(const int /*cc*/, const int warp_size) { + return 256/warp_size; +} +#endif // (GGML_USE_HIP) + +static constexpr __device__ int mmq_get_nwarps_device() { +#if defined(AMD_MFMA_AVAILABLE) + return 8; +#else + return 256/ggml_cuda_get_physical_warp_size(); +#endif // AMD_MFMA_AVAILABLE +} // ------------------------------------------------------------ -template static __device__ __forceinline__ void load_tiles_q4_0( +template static __device__ __forceinline__ void load_tiles_q4_0( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + 2*WARP_SIZE); + float * x_df = (float *) (x_qs + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_0, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI4_0; - const int kqsx = threadIdx.x % QI4_0; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR4_0); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI4_0; + const int kqsx = txi % QI4_0; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -259,20 +305,21 @@ template static __device__ __forceinlin const block_q4_0 * bxi = (const block_q4_0 *) x + kbx0 + i*stride + kbx; const int qs0 = get_int_b2(bxi->qs, kqsx); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kbx*(2*QI4_0) + kqsx + 0] = __vsubss4((qs0 >> 0) & 0x0F0F0F0F, 0x08080808); x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kbx*(2*QI4_0) + kqsx + QI4_0] = __vsubss4((qs0 >> 4) & 0x0F0F0F0F, 0x08080808); #else - x_qs[i*(WARP_SIZE + 1) + threadIdx.x] = qs0; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(MMQ_TILE_NE_K + 1) + txi] = qs0; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI4_0; + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI4_0; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; const int kbxd = threadIdx.x % blocks_per_tile_x_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI4_0) { - int i = i0 + threadIdx.y * QI4_0 + threadIdx.x / blocks_per_tile_x_row; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; if (need_check) { i = min(i, i_max); @@ -280,17 +327,19 @@ template static __device__ __forceinlin const block_q4_0 * bxi = (const block_q4_0 *) x + kbx0 + i*stride + kbxd; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = bxi->d; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = bxi->d; #else - x_df[i*(WARP_SIZE/QI4_0) + i/QI4_0 + kbxd] = bxi->d; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/QI4_0) + i/QI4_0 + kbxd] = bxi->d; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void vec_dot_q4_0_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_0, mmq_y); const int * x_qs = (const int *) x; @@ -299,7 +348,7 @@ static __device__ __forceinline__ void vec_dot_q4_0_q8_1_dp4a( const half2 * y_ds = (const half2 *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR4_0*VDR_Q4_0_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR4_0*VDR_Q4_0_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -307,7 +356,7 @@ static __device__ __forceinline__ void vec_dot_q4_0_q8_1_dp4a( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; const int kyqs = QI8_1 * ((k01/2) / (QI8_1/2)) + (k01/2) % (QI8_1/2); @@ -320,32 +369,37 @@ static __device__ __forceinline__ void vec_dot_q4_0_q8_1_dp4a( u[2*l+1] = y_qs[j*MMQ_TILE_Y_K + kyqs + (l + QI4_0)]; } - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q4_0_q8_1_impl - (&x_qs[i*(WARP_SIZE + 1) + k0/QR4_0], u, - x_df[i*(WARP_SIZE/QI4_0) + i/QI4_0 + k0/(QR4_0*QI4_0)], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q4_0_q8_1_impl + (&x_qs[i*(MMQ_TILE_NE_K + 1) + k0/QR4_0], u, + x_df[i*(MMQ_TILE_NE_K/QI4_0) + i/QI4_0 + k0/(QR4_0*QI4_0)], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template static __device__ __forceinline__ void load_tiles_q4_1( +template static __device__ __forceinline__ void load_tiles_q4_1( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_dm = (half2 *) (x_qs + 2*WARP_SIZE); + half2 * x_dm = (half2 *) (x_qs + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_1, mmq_y); int * x_qs = (int *) x_tile; half2 * x_dm = (half2 *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI4_1; - const int kqsx = threadIdx.x % QI4_1; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR4_1); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI4_1; + const int kqsx = txi % QI4_1; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -354,20 +408,21 @@ template static __device__ __forceinlin const block_q4_1 * bxi = (const block_q4_1 *) x + kbx0 + i*stride + kbx; const int qs0 = get_int_b4(bxi->qs, kqsx); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kbx*(2*QI4_1) + kqsx + 0] = (qs0 >> 0) & 0x0F0F0F0F; x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kbx*(2*QI4_1) + kqsx + QI4_1] = (qs0 >> 4) & 0x0F0F0F0F; #else - x_qs[i*(WARP_SIZE + 1) + threadIdx.x] = qs0; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(MMQ_TILE_NE_K + 1) + txi] = qs0; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI4_1; + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI4_1; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; const int kbxd = threadIdx.x % blocks_per_tile_x_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI4_1) { - int i = i0 + threadIdx.y * QI4_1 + threadIdx.x / blocks_per_tile_x_row; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; if (need_check) { i = min(i, i_max); @@ -375,17 +430,19 @@ template static __device__ __forceinlin const block_q4_1 * bxi = (const block_q4_1 *) x + kbx0 + i*stride + kbxd; -#ifdef NEW_MMA_AVAILABLE - x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + kbxd] = bxi->dm; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + kbxd] = bxi->dm; #else - x_dm[i*(WARP_SIZE/QI4_1) + i/QI4_1 + kbxd] = bxi->dm; -#endif // NEW_MMA_AVAILABLE + x_dm[i*(MMQ_TILE_NE_K/QI4_1) + i/QI4_1 + kbxd] = bxi->dm; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void vec_dot_q4_1_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_1, mmq_y); const int * x_qs = (const int *) x; @@ -394,7 +451,7 @@ static __device__ __forceinline__ void vec_dot_q4_1_q8_1_dp4a( const half2 * y_ds = (const half2 *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR4_1*VDR_Q4_1_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR4_1*VDR_Q4_1_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -402,7 +459,7 @@ static __device__ __forceinline__ void vec_dot_q4_1_q8_1_dp4a( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; const int kyqs = QI8_1 * ((k01/2) / (QI8_1/2)) + (k01/2) % (QI8_1/2); @@ -415,32 +472,37 @@ static __device__ __forceinline__ void vec_dot_q4_1_q8_1_dp4a( u[2*l+1] = y_qs[j*MMQ_TILE_Y_K + kyqs + (l + QI4_1)]; } - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q4_1_q8_1_impl - (&x_qs[i*(WARP_SIZE + 1) + k0/QR4_1], u, - x_dm[i*(WARP_SIZE/QI4_1) + i/QI4_1 + k0/(QR4_1*QI4_1)], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q4_1_q8_1_impl + (&x_qs[i*(MMQ_TILE_NE_K + 1) + k0/QR4_1], u, + x_dm[i*(MMQ_TILE_NE_K/QI4_1) + i/QI4_1 + k0/(QR4_1*QI4_1)], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template static __device__ __forceinline__ void load_tiles_q5_0( +template static __device__ __forceinline__ void load_tiles_q5_0( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q5_0, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI5_0; - const int kqsx = threadIdx.x % QI5_0; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR5_0); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI5_0; + const int kqsx = txi % QI5_0; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -449,7 +511,7 @@ template static __device__ __forceinlin const block_q5_0 * bxi = (const block_q5_0 *) x + kbx0 + i*stride + kbx; const int ql = get_int_b2(bxi->qs, kqsx); - const int qh = get_int_b2(bxi->qh, 0) >> (4 * (threadIdx.x % QI5_0)); + const int qh = get_int_b2(bxi->qh, 0) >> (4 * kqsx); int qs0 = (ql >> 0) & 0x0F0F0F0F; qs0 |= (qh << 4) & 0x00000010; // 0 -> 4 @@ -465,21 +527,22 @@ template static __device__ __forceinlin qs1 |= (qh << 9) & 0x10000000; // 19 -> 28 qs1 = __vsubss4(qs1, 0x10101010); // subtract 16 -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kbx*(2*QI5_0) + kqsx + 0] = qs0; x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kbx*(2*QI5_0) + kqsx + QI5_0] = qs1; #else - x_qs[i*(2*WARP_SIZE + 1) + kbx*(2*QI5_0) + kqsx + 0] = qs0; - x_qs[i*(2*WARP_SIZE + 1) + kbx*(2*QI5_0) + kqsx + QI5_0] = qs1; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kbx*(2*QI5_0) + kqsx + 0] = qs0; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kbx*(2*QI5_0) + kqsx + QI5_0] = qs1; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI5_0; + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI5_0; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; const int kbxd = threadIdx.x % blocks_per_tile_x_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI5_0) { - int i = i0 + threadIdx.y * QI5_0 + threadIdx.x / blocks_per_tile_x_row; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; if (need_check) { i = min(i, i_max); @@ -487,32 +550,37 @@ template static __device__ __forceinlin const block_q5_0 * bxi = (const block_q5_0 *) x + kbx0 + i*stride + kbxd; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = bxi->d; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = bxi->d; #else - x_df[i*(WARP_SIZE/QI5_0) + i/QI5_0 + kbxd] = bxi->d; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/QI5_0) + i/QI5_0 + kbxd] = bxi->d; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_q5_1( +template static __device__ __forceinline__ void load_tiles_q5_1( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_dm = (half2 *) (x_qs + 2*WARP_SIZE); + half2 * x_dm = (half2 *) (x_qs + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q5_1, mmq_y); int * x_qs = (int *) x_tile; half2 * x_dm = (half2 *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI5_1; - const int kqsx = threadIdx.x % QI5_1; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR5_1); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI5_1; + const int kqsx = txi % QI5_1; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -521,7 +589,7 @@ template static __device__ __forceinlin const block_q5_1 * bxi = (const block_q5_1 *) x + kbx0 + i*stride + kbx; const int ql = get_int_b4(bxi->qs, kqsx); - const int qh = get_int_b4(bxi->qh, 0) >> (4 * (threadIdx.x % QI5_1)); + const int qh = get_int_b4(bxi->qh, 0) >> (4 * kqsx); int qs0 = (ql >> 0) & 0x0F0F0F0F; qs0 |= (qh << 4) & 0x00000010; // 0 -> 4 @@ -535,21 +603,22 @@ template static __device__ __forceinlin qs1 |= (qh << 2) & 0x00100000; // 18 -> 20 qs1 |= (qh << 9) & 0x10000000; // 19 -> 28 -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kbx*(2*QI5_1) + kqsx + 0] = qs0; x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kbx*(2*QI5_1) + kqsx + QI5_1] = qs1; #else - x_qs[i*(2*WARP_SIZE + 1) + kbx*(2*QI5_1) + kqsx + 0] = qs0; - x_qs[i*(2*WARP_SIZE + 1) + kbx*(2*QI5_1) + kqsx + QI5_1] = qs1; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kbx*(2*QI5_1) + kqsx + 0] = qs0; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kbx*(2*QI5_1) + kqsx + QI5_1] = qs1; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI5_1; + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI5_1; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; const int kbxd = threadIdx.x % blocks_per_tile_x_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI5_1) { - int i = i0 + threadIdx.y * QI5_1 + threadIdx.x / blocks_per_tile_x_row; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; if (need_check) { i = min(i, i_max); @@ -557,32 +626,38 @@ template static __device__ __forceinlin const block_q5_1 * bxi = (const block_q5_1 *) x + kbx0 + i*stride + kbxd; -#ifdef NEW_MMA_AVAILABLE - x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + kbxd] = bxi->dm; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + kbxd] = bxi->dm; #else - x_dm[i*(WARP_SIZE/QI5_1) + i/QI5_1 + kbxd] = bxi->dm; -#endif // NEW_MMA_AVAILABLE + x_dm[i*(MMQ_TILE_NE_K/QI5_1) + i/QI5_1 + kbxd] = bxi->dm; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_q8_0( +template static __device__ __forceinline__ void load_tiles_q8_0( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_tile + 2*WARP_SIZE); + float * x_df = (float *) (x_tile + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q8_0, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI8_0; - const int kqsx = threadIdx.x % QI8_0; + // MMQ_ITER_K / (4 * QR8_0) == 64 required. but NV has only 32 threads per warp + constexpr int threads_per_row = 32; + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI8_0; + const int kqsx = txi % QI8_0; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -590,21 +665,22 @@ template static __device__ __forceinlin const block_q8_0 * bxi = (const block_q8_0 *) x + kbx0 + i*stride + kbx; -#ifdef NEW_MMA_AVAILABLE - x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 0 + threadIdx.x] = get_int_b2(bxi[0].qs, kqsx); - x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + WARP_SIZE + threadIdx.x] = get_int_b2(bxi[WARP_SIZE/QI8_0].qs, kqsx); +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 0 + txi] = get_int_b2(bxi[0].qs, kqsx); + x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + MMQ_TILE_NE_K + txi] = get_int_b2(bxi[MMQ_TILE_NE_K/QI8_0].qs, kqsx); #else - x_qs[i*(2*WARP_SIZE + 1) + 0 + threadIdx.x] = get_int_b2(bxi[0].qs, kqsx); - x_qs[i*(2*WARP_SIZE + 1) + WARP_SIZE + threadIdx.x] = get_int_b2(bxi[WARP_SIZE/QI8_0].qs, kqsx); -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 0 + txi] = get_int_b2(bxi[0].qs, kqsx); + x_qs[i*(2*MMQ_TILE_NE_K + 1) + MMQ_TILE_NE_K + txi] = get_int_b2(bxi[MMQ_TILE_NE_K/QI8_0].qs, kqsx); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = 2*WARP_SIZE / QI8_0; + constexpr int blocks_per_tile_x_row = 2*MMQ_TILE_NE_K / QI8_0; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; const int kbxd = threadIdx.x % blocks_per_tile_x_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI8_0/2) { - int i = i0 + threadIdx.y * (QI8_0/2) + threadIdx.x / blocks_per_tile_x_row; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; if (need_check) { i = min(i, i_max); @@ -612,17 +688,84 @@ template static __device__ __forceinlin const block_q8_0 * bxi = (const block_q8_0 *) x + kbx0 + i*stride + kbxd; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = bxi->d; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = bxi->d; #else - x_df[i*(2*WARP_SIZE/QI8_0) + i/(QI8_0/2) + kbxd] = bxi->d; -#endif // NEW_MMA_AVAILABLE + x_df[i*(2*MMQ_TILE_NE_K/QI8_0) + i/(QI8_0/2) + kbxd] = bxi->d; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void load_tiles_mxfp4( + const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + int * x_qs = (int *) x_tile; + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); +#else + constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_MXFP4, mmq_y); + int * x_qs = (int *) x_tile; + float * x_df = (float *) (x_qs + txs.qs); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR_MXFP4); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI_MXFP4; + const int kqsx = txi % QI_MXFP4; + +#pragma unroll + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); + + if (need_check) { + i = min(i, i_max); + } + + const block_mxfp4 * bxi = (const block_mxfp4 *) x + kbx0 + i*stride + kbx; + + const int aux_q4 = get_int_b1(bxi->qs, kqsx); + const int2 v = get_int_from_table_16(aux_q4, kvalues_mxfp4); + const int k0 = kbx * (2 * QI_MXFP4) + kqsx; + +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + k0 + 0] = v.x; + x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + k0 + QI_MXFP4] = v.y; +#else + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + 0] = v.x; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + QI_MXFP4] = v.y; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + } + + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI_MXFP4; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; + const int kbxd = threadIdx.x % blocks_per_tile_x_row; + +#pragma unroll + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; + + if (need_check) { + i = min(i, i_max); + } + + const block_mxfp4 * bxi = (const block_mxfp4 *) x + kbx0 + i*stride + kbxd; + +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_1 + kbxd] = ggml_cuda_e8m0_to_fp32(bxi->e)*0.5f; +#else + x_df[i*(MMQ_TILE_NE_K/QI_MXFP4) + i/QI_MXFP4 + kbxd] = ggml_cuda_e8m0_to_fp32(bxi->e)*0.5f; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + } +} + +template static __device__ __forceinline__ void vec_dot_q8_0_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q8_0, mmq_y); const int * x_qs = (const int *) x; @@ -631,7 +774,7 @@ static __device__ __forceinline__ void vec_dot_q8_0_q8_1_dp4a( const float * y_df = (const float *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += VDR_Q8_0_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += VDR_Q8_0_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -639,21 +782,76 @@ static __device__ __forceinline__ void vec_dot_q8_0_q8_1_dp4a( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q8_0_q8_1_impl - (&x_qs[i*(2*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k0 % WARP_SIZE], - x_df[i*(2*WARP_SIZE/QI8_0) + i/(QI8_0/2) + k0/QI8_0], y_df[j*MMQ_TILE_Y_K + (k0/QI8_1) % (WARP_SIZE/QI8_1)]); + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q8_0_q8_1_impl + (&x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k0 % MMQ_TILE_NE_K], + x_df[i*(2*MMQ_TILE_NE_K/QI8_0) + i/(QI8_0/2) + k0/QI8_0], y_df[j*MMQ_TILE_Y_K + (k0/QI8_1) % (MMQ_TILE_NE_K/QI8_1)]); } } } } -template +template static __device__ __forceinline__ void vec_dot_q8_0_q8_1_mma( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { +#if defined(AMD_MFMA_AVAILABLE) + typedef tile<16, 8, int> tile_A; + typedef tile<16, 8, int> tile_B; + typedef tile<16, 16, int> tile_C; + constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int rows_per_warp = granularity; + constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. + + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); + + const int * x_qs = (const int *) x; + const float * x_df = (const float *) x_qs + 2*MMQ_TILE_NE_K; + const int * y_qs = (const int *) y + 4; + const float * y_df = (const float *) y; + const half2 * y_ds = (const half2 *) y; + + const int i0 = (threadIdx.y / ntx) * rows_per_warp; + + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_0) { + const int k0 = k00 + k01; + + tile_A A[ntx]; +#pragma unroll + for (int n = 0; n < ntx; ++n) { + load_generic(A[n], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q8_0 + k0, MMQ_MMA_TILE_X_K_Q8_0); + } + +#pragma unroll + for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { + tile_B B; + load_generic(B, y_qs + j0*MMQ_TILE_Y_K + k01, MMQ_TILE_Y_K); + + float dB; + const int j = j0 + tile_C::get_j(0); + if (ds_layout == MMQ_Q8_1_DS_LAYOUT_D4) { + dB = y_df[j*MMQ_TILE_Y_K + k01/QI8_1]; + } else { + dB = __low2float(y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); + } + +#pragma unroll + for (int n = 0; n < ntx; ++n) { + tile_C C; + mma(C, A[n], B); + +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = i0 + n*tile_A::I + tile_C::get_i(l); + const float dA = x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + k0/QI8_0]; + sum[(j0/tile_C::J + n)*tile_C::ne + l] += C.x[l]*dA*dB; + } + } + } + } +#else typedef tile<16, 8, int> tile_A; typedef tile< 8, 8, int> tile_B; typedef tile<16, 8, int> tile_C; @@ -662,23 +860,23 @@ static __device__ __forceinline__ void vec_dot_q8_0_q8_1_mma( constexpr int rows_per_warp = 2 * granularity; constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. - y += (threadIdx.y % ntx) * (tile_B::I*MMQ_TILE_Y_K); + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); const int * x_qs = (const int *) x; - const float * x_df = (const float *) x_qs + 2*WARP_SIZE; + const float * x_df = (const float *) x_qs + 2*MMQ_TILE_NE_K; const int * y_qs = (const int *) y + 4; const float * y_df = (const float *) y; const half2 * y_ds = (const half2 *) y; - tile_A A[ntx][WARP_SIZE/QI8_0]; - float dA[ntx][tile_C::ne/2][WARP_SIZE/QI8_0]; + tile_A A[ntx][MMQ_TILE_NE_K/QI8_0]; + float dA[ntx][tile_C::ne/2][MMQ_TILE_NE_K/QI8_0]; const int i0 = (threadIdx.y/ntx)*rows_per_warp; #pragma unroll for (int n = 0; n < ntx; ++n) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_0) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_0) { const int k0 = k00 + k01; load_ldmatrix(A[n][k01/QI8_0], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q8_0 + k0, MMQ_MMA_TILE_X_K_Q8_0); @@ -689,7 +887,7 @@ static __device__ __forceinline__ void vec_dot_q8_0_q8_1_mma( const int i = i0 + n*tile_A::I + tile_C::get_i(2*l); #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_0) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_0) { const int k0 = k00 + k01; dA[n][l][k01/QI8_0] = x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + k0/QI8_0]; @@ -700,7 +898,7 @@ static __device__ __forceinline__ void vec_dot_q8_0_q8_1_mma( #pragma unroll for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_0) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_0) { tile_B B; float dB[tile_C::ne/2]; @@ -729,11 +927,14 @@ static __device__ __forceinline__ void vec_dot_q8_0_q8_1_mma( } } } +#endif // defined(AMD_MFMA_AVAILABLE) } -template +template static __device__ __forceinline__ void vec_dot_q8_1_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q5_1, mmq_y); const int * x_qs = (const int *) x; @@ -742,7 +943,7 @@ static __device__ __forceinline__ void vec_dot_q8_1_q8_1_dp4a( const half2 * y_ds = (const half2 *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += VDR_Q8_0_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += VDR_Q8_0_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -750,45 +951,95 @@ static __device__ __forceinline__ void vec_dot_q8_1_q8_1_dp4a( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q8_1_q8_1_impl - (&x_qs[i*(2*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], - x_dm[i*(WARP_SIZE/QI5_1) + i/QI5_1 + k0/QI8_1], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q8_1_q8_1_impl + (&x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], + x_dm[i*(MMQ_TILE_NE_K/QI5_1) + i/QI5_1 + k0/QI8_1], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template +template static __device__ __forceinline__ void vec_dot_q8_1_q8_1_mma( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { +#if defined(AMD_MFMA_AVAILABLE) + typedef tile<16, 8, int> tile_A; + typedef tile<16, 8, int> tile_B; + typedef tile<16, 16, int> tile_C; - typedef tile<16, 8, int> tile_A; - typedef tile< 8, 8, int> tile_B; - typedef tile<16, 8, int> tile_C; + constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int rows_per_warp = granularity; + constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. + + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); + + const int * x_qs = (const int *) x; + const half2 * x_dm = (const half2 *) x_qs + 2*MMQ_TILE_NE_K; + const int * y_qs = (const int *) y + 4; + const half2 * y_dm = (const half2 *) y; + + const int i0 = (threadIdx.y / ntx) * rows_per_warp; + + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { + const int k0 = k00 + k01; + + tile_A A[ntx]; +#pragma unroll + for (int n = 0; n < ntx; ++n) { + load_generic(A[n], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q8_1 + k0, MMQ_MMA_TILE_X_K_Q8_1); + } + +#pragma unroll + for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { + tile_B B; + load_generic(B, y_qs + j0*MMQ_TILE_Y_K + k01, MMQ_TILE_Y_K); + + const int j = j0 + tile_C::get_j(0); + const float2 dsB = __half22float2(y_dm[j*MMQ_TILE_Y_K + k01/QI8_1]); + +#pragma unroll + for (int n = 0; n < ntx; ++n) { + tile_C C; + mma(C, A[n], B); + +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = i0 + n*tile_A::I + tile_C::get_i(l); + float2 dmA = __half22float2(x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + k0/QI8_1]); + sum[(j0/tile_C::J + n)*tile_C::ne + l] += dmA.x*dsB.x*C.x[l]; + sum[(j0/tile_C::J + n)*tile_C::ne + l] += dmA.y*dsB.y; + } + } + } + } +#else + typedef tile<16, 8, int> tile_A; + typedef tile< 8, 8, int> tile_B; + typedef tile<16, 8, int> tile_C; constexpr int granularity = mmq_get_granularity_device(mmq_x); constexpr int rows_per_warp = 2 * granularity; constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. - y += (threadIdx.y % ntx) * (tile_B::J*MMQ_TILE_Y_K); + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); const int * x_qs = (const int *) x; - const half2 * x_dm = (const half2 *) x_qs + 2*WARP_SIZE; + const half2 * x_dm = (const half2 *) x_qs + 2*MMQ_TILE_NE_K; const int * y_qs = (const int *) y + 4; const half2 * y_dm = (const half2 *) y; - tile_A A[ntx][WARP_SIZE/QI8_1]; - float2 dmA[ntx][tile_C::ne/2][WARP_SIZE/QI8_1]; + tile_A A[ntx][MMQ_TILE_NE_K/QI8_1]; + float2 dmA[ntx][tile_C::ne/2][MMQ_TILE_NE_K/QI8_1]; const int i0 = (threadIdx.y/ntx)*rows_per_warp; #pragma unroll for (int n = 0; n < ntx; ++n) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { const int k0 = k00 + k01; load_ldmatrix(A[n][k01/QI8_1], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q8_1 + k0, MMQ_MMA_TILE_X_K_Q8_1); @@ -799,7 +1050,7 @@ static __device__ __forceinline__ void vec_dot_q8_1_q8_1_mma( const int i = i0 + n*tile_A::I + tile_C::get_i(2*l); #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { const int k0 = k00 + k01; dmA[n][l][k01/QI8_1] = __half22float2(x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + k0/QI8_1]); @@ -810,7 +1061,7 @@ static __device__ __forceinline__ void vec_dot_q8_1_q8_1_mma( #pragma unroll for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { tile_B B; float2 dsB[tile_C::ne/2]; @@ -836,11 +1087,15 @@ static __device__ __forceinline__ void vec_dot_q8_1_q8_1_mma( } } } +#endif // defined(AMD_MFMA_AVAILABLE) } -template +// Used for Q3_K, IQ2_S, and IQ2_XS +template static __device__ __forceinline__ void vec_dot_q8_0_16_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = MMQ_DP4A_TXS_Q8_0_16; const int * x_qs = (const int *) x; @@ -849,7 +1104,7 @@ static __device__ __forceinline__ void vec_dot_q8_0_16_q8_1_dp4a( const float * y_df = (const float *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_0) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_0) { const int k0 = k00 + k01; #pragma unroll @@ -857,23 +1112,73 @@ static __device__ __forceinline__ void vec_dot_q8_0_16_q8_1_dp4a( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q8_0_16_q8_1_impl( - &x_qs[i*(2*WARP_SIZE + 1) + k0], + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q8_0_16_q8_1_impl( + &x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], - &x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + k0/(QI8_0/2)], + &x_df[i*(2*MMQ_TILE_NE_K*2/QI8_0) + i/(QI8_0/4) + k0/(QI8_0/2)], y_df[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template +// Used for Q3_K, IQ2_S, and IQ2_XS: +template static __device__ __forceinline__ void vec_dot_q8_0_16_q8_1_mma( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) + typedef tile<16, 8, int> tile_A; + typedef tile<16, 8, int> tile_B; + typedef tile<16, 16, int> tile_C; + typedef tile<64, 2, int> tile_load; + + constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int rows_per_warp = granularity; + constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. + + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); + + const int * x_qs = (const int *) x; + const float * x_df = (const float *) x_qs + MMQ_TILE_NE_K*2; + const int * y_qs = (const int *) y + 4; + const float * y_df = (const float *) y; + + const int i0 = (threadIdx.y / ntx) * rows_per_warp; + + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 4) { + const int k0 = k00 + k01; + + tile_A A[ntx]; +#pragma unroll + for (int n = 0; n < ntx; ++n) { + load_generic(((tile_load *) A)[n], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q3_K + k0, MMQ_MMA_TILE_X_K_Q3_K); + } + +#pragma unroll + for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { + tile_B B[1]; + load_generic(((tile_load *) B)[0], y_qs + j0*MMQ_TILE_Y_K + k01, MMQ_TILE_Y_K); + + const int j = j0 + tile_C::get_j(0); + const float dB = y_df[j*MMQ_TILE_Y_K + k01/QI8_1] / 2; + +#pragma unroll + for (int n = 0; n < ntx; ++n) { + tile_C C; + mma(C, A[n], B[0]); + +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = i0 + n*tile_C::I + tile_C::get_i(l); + sum[(j0/tile_C::J + n)*tile_C::ne + l] += C.x[l] * x_df[i*MMQ_MMA_TILE_X_K_Q3_K + k0/4] * dB; + } + } + } + } +#elif defined(TURING_MMA_AVAILABLE) typedef tile<16, 4, int> tile_A; typedef tile<16, 8, int> tile_A_8; @@ -884,10 +1189,10 @@ static __device__ __forceinline__ void vec_dot_q8_0_16_q8_1_mma( constexpr int rows_per_warp = 2 * granularity; constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. - y += (threadIdx.y % ntx) * (tile_B::I*MMQ_TILE_Y_K); + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); const int * x_qs = (const int *) x; - const float * x_df = (const float *) x_qs + WARP_SIZE*2; + const float * x_df = (const float *) x_qs + MMQ_TILE_NE_K*2; const int * y_qs = (const int *) y + 4; const float * y_df = (const float *) y; @@ -899,7 +1204,7 @@ static __device__ __forceinline__ void vec_dot_q8_0_16_q8_1_mma( #pragma unroll for (int n = 0; n < ntx; ++n) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += 8) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 8) { const int k0 = k00 + k01; load_ldmatrix(((tile_A_8 *) A[n])[k01/8], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q3_K + k0, MMQ_MMA_TILE_X_K_Q3_K); @@ -910,7 +1215,7 @@ static __device__ __forceinline__ void vec_dot_q8_0_16_q8_1_mma( const int i = i0 + n*tile_C::I + tile_C::get_i(2*l); #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += 4) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 4) { const int k0 = k00 + k01; dA[n][l][k01/4] = x_df[i*MMQ_MMA_TILE_X_K_Q3_K + k0/4]; @@ -921,7 +1226,7 @@ static __device__ __forceinline__ void vec_dot_q8_0_16_q8_1_mma( #pragma unroll for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR3_K*VDR_Q3_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR3_K*VDR_Q3_K_Q8_1_MMQ) { tile_B B[2]; float dB[tile_C::ne/2]; @@ -952,26 +1257,29 @@ static __device__ __forceinline__ void vec_dot_q8_0_16_q8_1_mma( #else GGML_UNUSED(x); GGML_UNUSED(y); GGML_UNUSED(sum); GGML_UNUSED(k00); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // AMD_MFMA_AVAILABLE } -template static __device__ __forceinline__ void load_tiles_q2_K( +template static __device__ __forceinline__ void load_tiles_q2_K( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_dm = (half2 *) (x_qs + 2*WARP_SIZE); + half2 * x_dm = (half2 *) (x_qs + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q2_K, mmq_y); int * x_qs = (int *) x_tile; half2 * x_dm = (half2 *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % QI2_K; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR2_K); + constexpr int nrows = ggml_cuda_get_physical_warp_size() / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/QI2_K) { - int i = i0 + threadIdx.y*(WARP_SIZE/QI2_K) + threadIdx.x/QI2_K; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -987,11 +1295,11 @@ template static __device__ __forceinlin const int x_qs_k = (x_ql_0 >> (2*l)) & 0x03030303; -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q2_K + k] = x_qs_k; #else - x_qs[i*(2*WARP_SIZE + 1) + k] = x_qs_k; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k] = x_qs_k; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } const int sc_m = bxi->scales[kqsx]; @@ -1002,17 +1310,19 @@ template static __device__ __forceinlin const half2 x_dm_ik = make_half2(bxi_dmf.x*(sc_m & 0x0F), bxi_dmf.y*(sc_m >> 4)); #endif // FAST_FP16_AVAILABLE -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_dm[i*MMQ_MMA_TILE_X_K_Q2_K + kqsx] = x_dm_ik; #else - x_dm[i*(WARP_SIZE + 1) + kqsx] = x_dm_ik; -#endif // NEW_MMA_AVAILABLE + x_dm[i*(MMQ_TILE_NE_K + 1) + kqsx] = x_dm_ik; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void vec_dot_q2_K_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q2_K, mmq_y); const int * x_qs = (const int *) x; @@ -1029,7 +1339,7 @@ static __device__ __forceinline__ void vec_dot_q2_K_q8_1_dp4a( } #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE/2; k01 += QR2_K*VDR_Q2_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K/2; k01 += QR2_K*VDR_Q2_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1037,13 +1347,13 @@ static __device__ __forceinline__ void vec_dot_q2_K_q8_1_dp4a( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; constexpr int ns = 2; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q2_K_q8_1_impl_mmq( - &x_qs[i*(2*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], - &x_dm[i*(WARP_SIZE + 1) + k0/4], k01 < WARP_SIZE/2 ? y_df[j0/nwarps].x : y_df[j0/nwarps].y, + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q2_K_q8_1_impl_mmq( + &x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], + &x_dm[i*(MMQ_TILE_NE_K + 1) + k0/4], k01 < MMQ_TILE_NE_K/2 ? y_df[j0/nwarps].x : y_df[j0/nwarps].y, &y_ds[j*MMQ_TILE_Y_K + (1 + k01/QI8_1)]); } } @@ -1052,7 +1362,7 @@ static __device__ __forceinline__ void vec_dot_q2_K_q8_1_dp4a( // Some compilers fail to unroll the loop over k01 if there is a conditional statement for ns in the inner loop. // As a workaround 2 separate loops are used instead. #pragma unroll - for (int k01 = WARP_SIZE/2; k01 < WARP_SIZE; k01 += QR2_K*VDR_Q2_K_Q8_1_MMQ) { + for (int k01 = MMQ_TILE_NE_K/2; k01 < MMQ_TILE_NE_K; k01 += QR2_K*VDR_Q2_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1060,23 +1370,89 @@ static __device__ __forceinline__ void vec_dot_q2_K_q8_1_dp4a( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; constexpr int ns = 1; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q2_K_q8_1_impl_mmq( - &x_qs[i*(2*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], - &x_dm[i*(WARP_SIZE + 1) + k0/4], k01 < WARP_SIZE/2 ? y_df[j0/nwarps].x : y_df[j0/nwarps].y, + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q2_K_q8_1_impl_mmq( + &x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], + &x_dm[i*(MMQ_TILE_NE_K + 1) + k0/4], k01 < MMQ_TILE_NE_K/2 ? y_df[j0/nwarps].x : y_df[j0/nwarps].y, &y_ds[j*MMQ_TILE_Y_K + (1 + k01/QI8_1)]); } } } } -template +template static __device__ __forceinline__ void vec_dot_q2_K_q8_1_mma( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) + typedef tile<16, 8, int> tile_A; + typedef tile<16, 8, int> tile_B; + typedef tile<16, 16, int> tile_C; + typedef tile<64, 2, int> tile_load; + + constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int rows_per_warp = granularity; + constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. + + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); + + const int * x_qs = (const int *) x; + const half2 * x_dm = (const half2 *) x_qs + MMQ_TILE_NE_K*2; + const int * y_qs = (const int *) y + 4; + const half2 * y_ds = (const half2 *) y; + + const int i0 = (threadIdx.y / ntx) * rows_per_warp; + + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 4) { + const int k0 = k00 + k01; + + tile_A A[ntx]; +#pragma unroll + for (int n = 0; n < ntx; ++n) { + load_generic(((tile_load *) A)[n], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q2_K + k0, MMQ_MMA_TILE_X_K_Q2_K); + } + +#pragma unroll + for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { + tile_B B[1]; + load_generic(((tile_load *) B)[0], y_qs + j0*MMQ_TILE_Y_K + k01, MMQ_TILE_Y_K); + + const int j = j0 + tile_C::get_j(0); + const float dB = (k01 < MMQ_TILE_NE_K/2) ? __half22float2(y_ds[j*MMQ_TILE_Y_K]).x/2 : __half22float2(y_ds[j*MMQ_TILE_Y_K]).y/2; + const float sB = (k01 >= MMQ_TILE_NE_K * 3/4) ? 0 + : (((k01/4)%2) ? __half22float2(y_ds[j*MMQ_TILE_Y_K + (1 + k01/QI8_1)]).y + : __half22float2(y_ds[j*MMQ_TILE_Y_K + (1 + k01/QI8_1)]).x); + + tile_C Cm; + if (k01 >= MMQ_TILE_NE_K * 3/4) { + tile_A A1; + A1.x[0] = 0x01010101; + A1.x[1] = 0x01010101; + mma(Cm, A1, B[0]); + } + +#pragma unroll + for (int n = 0; n < ntx; ++n) { + tile_C Cd; + mma(Cd, A[n], B[0]); + +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = i0 + n*tile_C::I + tile_C::get_i(l); + const float2 dm = __half22float2(x_dm[i*MMQ_MMA_TILE_X_K_Q2_K + k0/4]); + float tmp = Cd.x[l]*dm.x; + if (k01 >= MMQ_TILE_NE_K * 3/4) { + tmp -= Cm.x[l]*dm.y; + } + sum[(j0/tile_C::J + n)*tile_C::ne + l] += tmp*dB; + sum[(j0/tile_C::J + n)*tile_C::ne + l] -= dm.y*sB; + } + } + } + } +#elif defined(TURING_MMA_AVAILABLE) typedef tile<16, 4, int> tile_A; typedef tile<16, 8, int> tile_A_8; @@ -1087,10 +1463,10 @@ static __device__ __forceinline__ void vec_dot_q2_K_q8_1_mma( constexpr int rows_per_warp = 2 * granularity; constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. - y += (threadIdx.y % ntx) * (tile_B::I*MMQ_TILE_Y_K); + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); const int * x_qs = (const int *) x; - const half2 * x_dm = (const half2 *) x_qs + WARP_SIZE*2; + const half2 * x_dm = (const half2 *) x_qs + MMQ_TILE_NE_K*2; const int * y_qs = (const int *) y + 4; const half2 * y_ds = (const half2 *) y; @@ -1103,7 +1479,7 @@ static __device__ __forceinline__ void vec_dot_q2_K_q8_1_mma( #pragma unroll for (int n = 0; n < ntx; ++n) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { const int k0 = k00 + k01; load_ldmatrix(((tile_A_8 *) A[n])[k01/QI8_1], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q2_K + k0, MMQ_MMA_TILE_X_K_Q2_K); @@ -1117,7 +1493,7 @@ static __device__ __forceinline__ void vec_dot_q2_K_q8_1_mma( const int i = i0 + n*tile_C::I + tile_C::get_i(2*l); #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1/2) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1/2) { const int k0 = k00 + k01; const float2 dm = __half22float2(x_dm[i*MMQ_MMA_TILE_X_K_Q2_K + k0/(QI8_1/2)]); @@ -1140,7 +1516,7 @@ static __device__ __forceinline__ void vec_dot_q2_K_q8_1_mma( } #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { tile_B B[2]; // Here load_generic is faster than load_ldmatrix. @@ -1148,7 +1524,7 @@ static __device__ __forceinline__ void vec_dot_q2_K_q8_1_mma( load_generic(B[1], y_qs + j0*MMQ_TILE_Y_K + (k01 + tile_B::J), MMQ_TILE_Y_K); tile_C Cm[2]; - if (k01 >= WARP_SIZE * 3/4) { + if (k01 >= MMQ_TILE_NE_K * 3/4) { tile_A A1; A1.x[0] = 0x01010101; A1.x[1] = 0x01010101; @@ -1166,16 +1542,16 @@ static __device__ __forceinline__ void vec_dot_q2_K_q8_1_mma( #pragma unroll for (int l = 0; l < tile_C::ne; ++l) { float tmp = Cd[0].x[l]*dA[n][l/2][k01/4 + 0] + Cd[1].x[l]*dA[n][l/2][k01/4 + 1]; - if (k01 >= WARP_SIZE * 3/4) { + if (k01 >= MMQ_TILE_NE_K * 3/4) { tmp -= Cm[0].x[l]*mA[n][l/2][k01/4 + 0] + Cm[1].x[l]*mA[n][l/2][k01/4 + 1]; } - sum[(j0/tile_C::J + n)*tile_C::ne + l] += tmp*(k01 < WARP_SIZE/2 ? dB[l%2].x : dB[l%2].y); + sum[(j0/tile_C::J + n)*tile_C::ne + l] += tmp*(k01 < MMQ_TILE_NE_K/2 ? dB[l%2].x : dB[l%2].y); } } } #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE * 3/4; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K * 3/4; k01 += QI8_1) { float2 sB[tile_C::ne/2]; #pragma unroll @@ -1198,27 +1574,31 @@ static __device__ __forceinline__ void vec_dot_q2_K_q8_1_mma( #else GGML_UNUSED(x); GGML_UNUSED(y); GGML_UNUSED(sum); GGML_UNUSED(k00); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // AMD_MFMA_AVAILABLE } -template static __device__ __forceinline__ void load_tiles_q3_K( +template static __device__ __forceinline__ void load_tiles_q3_K( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q3_K, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); int * x_sc = (int *) (x_df + txs.dm); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % QI3_K; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR3_K); + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/QI3_K) { - int i = i0 + threadIdx.y * (WARP_SIZE/QI3_K) + threadIdx.x / QI3_K; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -1238,17 +1618,18 @@ template static __device__ __forceinlin const int x_qs_k = __vsubss4(x_ql_k | x_qh_k, 0x04040404); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q3_K + k] = x_qs_k; #else - x_qs[i*(2*WARP_SIZE + 1) + k] = x_qs_k; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k] = x_qs_k; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } + constexpr int rows_per_warp = warp_size / 4; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*8) { - int i = i0 + threadIdx.y*8 + threadIdx.x/(WARP_SIZE/8); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*rows_per_warp) { + int i = i0 + threadIdx.y*rows_per_warp + threadIdx.x/4; if (need_check) { i = min(i, i_max); @@ -1256,7 +1637,7 @@ template static __device__ __forceinlin const block_q3_K * bxi = (const block_q3_K *) x + kbx0 + i*stride; - const int ksc = threadIdx.x % (WARP_SIZE/8); + const int ksc = threadIdx.x % 4; const int ksc_low = ksc % (QI3_K/8); const int shift_low = 4 * (ksc / (QI3_K/8)); @@ -1268,23 +1649,23 @@ template static __device__ __forceinlin const int sc = __vsubss4(sc_low | sc_high, 0x20202020); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) const int8_t * sc8 = (const int8_t *) ≻ const float d = bxi->d; #pragma unroll for (int l = 0; l < int(sizeof(int)); ++l) { - x_df[i*MMQ_MMA_TILE_X_K_Q3_K + sizeof(int)*(threadIdx.x % (WARP_SIZE/8)) + l] = d*sc8[l]; + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + sizeof(int)*ksc + l] = d*sc8[l]; } #else - x_sc[i*(WARP_SIZE/8) + i/8 + threadIdx.x % (WARP_SIZE/8)] = sc; -#endif // NEW_MMA_AVAILABLE + x_sc[i*(MMQ_TILE_NE_K/8) + i/8 + ksc] = sc; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } -#ifndef NEW_MMA_AVAILABLE +#if !(defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE)) #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*WARP_SIZE) { - int i = (i0 + threadIdx.y*WARP_SIZE + threadIdx.x) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*warp_size) { + int i = (i0 + threadIdx.y*warp_size + threadIdx.x) % mmq_y; if (need_check) { i = min(i, i_max); @@ -1294,12 +1675,14 @@ template static __device__ __forceinlin x_df[i] = bxi->d; } -#endif // NEW_MMA_AVAILABLE +#endif // !(defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE)) } -template +template static __device__ __forceinline__ void vec_dot_q3_K_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q3_K, mmq_y); const int * x_qs = (const int *) x; @@ -1309,7 +1692,7 @@ static __device__ __forceinline__ void vec_dot_q3_K_q8_1_dp4a( const float * y_df = (const float *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR3_K*VDR_Q3_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR3_K*VDR_Q3_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1317,13 +1700,13 @@ static __device__ __forceinline__ void vec_dot_q3_K_q8_1_dp4a( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - const int8_t * scales = ((const int8_t *) (x_sc + i*(WARP_SIZE/8) + i/8)) + k0/4; + const int8_t * scales = ((const int8_t *) (x_sc + i*(MMQ_TILE_NE_K/8) + i/8)) + k0/4; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q3_K_q8_1_impl_mmq( - &x_qs[i*(2*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], scales, + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q3_K_q8_1_impl_mmq( + &x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], scales, x_df[i], y_df[j*MMQ_TILE_Y_K + k01/QI8_1]); } } @@ -1340,72 +1723,85 @@ static __device__ __forceinline__ int unpack_scales_q45_K(const int * scales, co ((scales[ksc/2] >> (2 * (ksc % 2))) & 0x30303030); // upper 2 bits } -template static __device__ __forceinline__ void load_tiles_q4_K( +template static __device__ __forceinline__ void load_tiles_q4_K( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_dm = (half2 *) (x_qs + 2*WARP_SIZE); + half2 * x_dm = (half2 *) (x_qs + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_K, mmq_y); int * x_qs = (int *) x_tile; half2 * x_dm = (half2 *) (x_qs + txs.qs); int * x_sc = (int *) (x_dm + txs.dm); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR4_K); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); } const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride; - const int qs0 = get_int_b4(bxi->qs, threadIdx.x); + const int qs0 = get_int_b4(bxi->qs, txi); -#ifdef NEW_MMA_AVAILABLE - x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 16*(threadIdx.x/8) + threadIdx.x % 8 + 0] = (qs0 >> 0) & 0x0F0F0F0F; - x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 16*(threadIdx.x/8) + threadIdx.x % 8 + 8] = (qs0 >> 4) & 0x0F0F0F0F; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 16*(txi/8) + txi % 8 + 0] = (qs0 >> 0) & 0x0F0F0F0F; + x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 16*(txi/8) + txi % 8 + 8] = (qs0 >> 4) & 0x0F0F0F0F; #else - x_qs[i*(WARP_SIZE + 1) + threadIdx.x] = qs0; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(MMQ_TILE_NE_K + 1) + txi] = qs0; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } -#ifdef NEW_MMA_AVAILABLE - +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + constexpr int rows_per_warp = warp_size / 2; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*16) { - int i = (i0 + threadIdx.y*16 + threadIdx.x/(WARP_SIZE/16)) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*rows_per_warp) { +#if defined(AMD_MFMA_AVAILABLE) + // Need if on AMD instead of % because warp_size == 64 + // This causes double work and throughput loss (MI300X) + // H100 loses about 100 t/s with 'if' condition over '%' + int i = i0 + threadIdx.y*rows_per_warp + threadIdx.x/2; + if (i < mmq_y) { +#else + int i = (i0 + threadIdx.y*rows_per_warp + threadIdx.x/2) % mmq_y; + { +#endif // defined(AMD_MFMA_AVAILABLE) + if (need_check) { + i = min(i, i_max); + } - if (need_check) { - i = min(i, i_max); - } + const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride; - const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride; + const int * scales = (const int *) bxi->scales; + const int ksc = threadIdx.x % 2; - const int * scales = (const int *) bxi->scales; - const int ksc = threadIdx.x % (WARP_SIZE/16); + const int sc32 = unpack_scales_q45_K(scales, ksc + 0); + const int m32 = unpack_scales_q45_K(scales, ksc + 2); - const int sc32 = unpack_scales_q45_K(scales, ksc + 0); - const int m32 = unpack_scales_q45_K(scales, ksc + 2); + const uint8_t * sc8 = (const uint8_t *) &sc32; + const uint8_t * m8 = (const uint8_t *) &m32; - const uint8_t * sc8 = (const uint8_t *) &sc32; - const uint8_t * m8 = (const uint8_t *) &m32; + const half2 dm = bxi->dm * make_half2(1.0f, -1.0f); - const half2 dm = bxi->dm * make_half2(1.0f, -1.0f); - -#pragma unroll - for (int l = 0; l < int(sizeof(int)); ++l) { - x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + sizeof(int)*ksc + l] = dm*make_half2(sc8[l], m8[l]); + #pragma unroll + for (int l = 0; l < sizeof(int); ++l) { + x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + sizeof(int)*ksc + l] = dm*make_half2(sc8[l], m8[l]); + } } } - #else - #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*QI4_K) { - int i = (i0 + threadIdx.y*QI4_K + threadIdx.x) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*warp_size) { + int i = (i0 + threadIdx.y*warp_size + threadIdx.x) % mmq_y; if (need_check) { i = min(i, i_max); @@ -1415,30 +1811,32 @@ template static __device__ __forceinlin x_dm[i] = bxi->dm; } - + constexpr int rows_per_warp = warp_size / 4; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * 8) { - int i = (i0 + threadIdx.y * 8 + threadIdx.x / (WARP_SIZE/8)) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*rows_per_warp) { + int i = (i0 + threadIdx.y*rows_per_warp + threadIdx.x/(MMQ_TILE_NE_K/8)) % mmq_y; if (need_check) { i = min(i, i_max); } - const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride + (threadIdx.x % (WARP_SIZE/8)) / (QI4_K/8); + const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride + (threadIdx.x % (MMQ_TILE_NE_K/8)) / (QI4_K/8); const int * scales = (const int *) bxi->scales; - const int ksc = threadIdx.x % (WARP_SIZE/8); + const int ksc = threadIdx.x % (MMQ_TILE_NE_K/8); const int scales8 = unpack_scales_q45_K(scales, ksc); - x_sc[i*(WARP_SIZE/8) + i/8 + ksc] = scales8; + x_sc[i*(MMQ_TILE_NE_K/8) + i/8 + ksc] = scales8; } -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } -template +template static __device__ __forceinline__ void vec_dot_q4_K_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_K, mmq_y); const int * x_qs = (const int *) x; @@ -1448,7 +1846,7 @@ static __device__ __forceinline__ void vec_dot_q4_K_q8_1_dp4a( const half2 * y_ds = (const half2 *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR4_K*VDR_Q4_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR4_K*VDR_Q4_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1456,97 +1854,110 @@ static __device__ __forceinline__ void vec_dot_q4_K_q8_1_dp4a( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - const uint8_t * sc = (const uint8_t *) &x_sc[i * (WARP_SIZE/8) + i/8 + k0/32] + 2*(k01/16); + const uint8_t * sc = (const uint8_t *) &x_sc[i * (MMQ_TILE_NE_K/8) + i/8 + k0/32] + 2*(k01/16); - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q4_K_q8_1_impl_mmq( - &x_qs[i*(WARP_SIZE + 1) + k0/2], &y_qs[j*MMQ_TILE_Y_K + k01], sc, sc+8, + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q4_K_q8_1_impl_mmq( + &x_qs[i*(MMQ_TILE_NE_K + 1) + k0/2], &y_qs[j*MMQ_TILE_Y_K + k01], sc, sc+8, x_dm[i], &y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template static __device__ __forceinline__ void load_tiles_q5_K( +template static __device__ __forceinline__ void load_tiles_q5_K( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_dm = (half2 *) (x_qs + WARP_SIZE*2); + half2 * x_dm = (half2 *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q5_K, mmq_y); int * x_qs = (int *) x_tile; half2 * x_dm = (half2 *) (x_qs + txs.qs); int * x_sc = (int *) (x_dm + txs.dm); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR5_K); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); } const block_q5_K * bxi = (const block_q5_K *) x + kbx0 + i*stride; - const int ky = QR5_K*threadIdx.x; + const int ky = QR5_K*txi; - const int ql = get_int_b4(bxi->qs, threadIdx.x); + const int ql = get_int_b4(bxi->qs, txi); const int ql0 = (ql >> 0) & 0x0F0F0F0F; const int ql1 = (ql >> 4) & 0x0F0F0F0F; - const int qh = get_int_b4(bxi->qh, threadIdx.x % (QI5_K/4)); - const int qh0 = ((qh >> (2 * (threadIdx.x / (QI5_K/4)) + 0)) << 4) & 0x10101010; - const int qh1 = ((qh >> (2 * (threadIdx.x / (QI5_K/4)) + 1)) << 4) & 0x10101010; + const int qh = get_int_b4(bxi->qh, txi % (QI5_K/4)); + const int qh0 = ((qh >> (2 * (txi / (QI5_K/4)) + 0)) << 4) & 0x10101010; + const int qh1 = ((qh >> (2 * (txi / (QI5_K/4)) + 1)) << 4) & 0x10101010; - const int kq0 = ky - ky % (QI5_K/2) + threadIdx.x % (QI5_K/4) + 0; - const int kq1 = ky - ky % (QI5_K/2) + threadIdx.x % (QI5_K/4) + QI5_K/4; + const int kq0 = ky - ky % (QI5_K/2) + txi % (QI5_K/4) + 0; + const int kq1 = ky - ky % (QI5_K/2) + txi % (QI5_K/4) + QI5_K/4; -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kq0] = ql0 | qh0; x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kq1] = ql1 | qh1; #else - x_qs[i*(2*WARP_SIZE + 1) + kq0] = ql0 | qh0; - x_qs[i*(2*WARP_SIZE + 1) + kq1] = ql1 | qh1; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kq0] = ql0 | qh0; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kq1] = ql1 | qh1; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } -#ifdef NEW_MMA_AVAILABLE - +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + constexpr int rows_per_warp = warp_size / 2; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*16) { - int i = (i0 + threadIdx.y*16 + threadIdx.x/(WARP_SIZE/16)) % mmq_y; - - if (need_check) { - i = min(i, i_max); - } - - const block_q5_K * bxi = (const block_q5_K *) x + kbx0 + i*stride; - - const int * scales = (const int *) bxi->scales; - const int ksc = threadIdx.x % (WARP_SIZE/16); - - const int sc32 = unpack_scales_q45_K(scales, ksc + 0); - const int m32 = unpack_scales_q45_K(scales, ksc + 2); - - const uint8_t * sc8 = (const uint8_t *) &sc32; - const uint8_t * m8 = (const uint8_t *) &m32; - - const half2 dm = bxi->dm * make_half2(1.0f, -1.0f); - -#pragma unroll - for (int l = 0; l < int(sizeof(int)); ++l) { - x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + sizeof(int)*ksc + l] = dm*make_half2(sc8[l], m8[l]); - } - } - + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*rows_per_warp) { +#if defined(AMD_MFMA_AVAILABLE) + // Need if on AMD instead of % because warp_size == 64 + // This causes double work and throughput loss (MI300X) + // H100 loses about 100 t/s with 'if' condition over '%' + int i = i0 + threadIdx.y*rows_per_warp + threadIdx.x/2; + if (i < mmq_y) { #else + int i = (i0 + threadIdx.y*rows_per_warp + threadIdx.x/2) % mmq_y; + { +#endif // defined(AMD_MFMA_AVAILABLE) + if (need_check) { + i = min(i, i_max); + } + + const block_q5_K * bxi = (const block_q5_K *) x + kbx0 + i*stride; + + const int * scales = (const int *) bxi->scales; + const int ksc = threadIdx.x % 2; + + const int sc32 = unpack_scales_q45_K(scales, ksc + 0); + const int m32 = unpack_scales_q45_K(scales, ksc + 2); + + const uint8_t * sc8 = (const uint8_t *) &sc32; + const uint8_t * m8 = (const uint8_t *) &m32; + + const half2 dm = bxi->dm * make_half2(1.0f, -1.0f); #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*QI5_K) { - int i = (i0 + threadIdx.y*QI5_K + threadIdx.x) % mmq_y; + for (int l = 0; l < int(sizeof(int)); ++l) { + x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + sizeof(int)*ksc + l] = dm*make_half2(sc8[l], m8[l]); + } + } + } +#else +#pragma unroll + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*warp_size) { + int i = (i0 + threadIdx.y*warp_size + threadIdx.x) % mmq_y; if (need_check) { i = min(i, i_max); @@ -1557,9 +1968,10 @@ template static __device__ __forceinlin x_dm[i] = bxi->dm; } + constexpr int rows_per_warp = warp_size / 4; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*8) { - int i = (i0 + threadIdx.y*8 + threadIdx.x/(WARP_SIZE/8)) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*rows_per_warp) { + int i = (i0 + threadIdx.y*rows_per_warp + threadIdx.x/(MMQ_TILE_NE_K/8)) % mmq_y; if (need_check) { i = min(i, i_max); @@ -1569,17 +1981,19 @@ template static __device__ __forceinlin const int * scales = (const int *) bxi->scales; - const int ksc = threadIdx.x % (WARP_SIZE/8); + const int ksc = threadIdx.x % (MMQ_TILE_NE_K/8); const int scales8 = unpack_scales_q45_K(scales, ksc); - x_sc[i*(WARP_SIZE/8) + i/8 + ksc] = scales8; + x_sc[i*(MMQ_TILE_NE_K/8) + i/8 + ksc] = scales8; } -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } -template +template static __device__ __forceinline__ void vec_dot_q5_K_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q5_K, mmq_y); const int * x_qs = (const int *) x; @@ -1589,7 +2003,7 @@ static __device__ __forceinline__ void vec_dot_q5_K_q8_1_dp4a( const half2 * y_ds = (const half2 *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR5_K*VDR_Q5_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR5_K*VDR_Q5_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1597,36 +2011,42 @@ static __device__ __forceinline__ void vec_dot_q5_K_q8_1_dp4a( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - const uint8_t * sc = ((const uint8_t *) &x_sc[i * (WARP_SIZE/8) + i/8 + k00/32]) + 2*(k01/16); + const uint8_t * sc = ((const uint8_t *) &x_sc[i * (MMQ_TILE_NE_K/8) + i/8 + k00/32]) + 2*(k01/16); - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q5_K_q8_1_impl_mmq( - &x_qs[i*(QR5_K*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], sc, sc+8, + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q5_K_q8_1_impl_mmq( + &x_qs[i*(QR5_K*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], sc, sc+8, x_dm[i], &y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template static __device__ __forceinline__ void load_tiles_q6_K( +template static __device__ __forceinline__ void load_tiles_q6_K( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); - int * x_sc = (int *) (x_df + WARP_SIZE/QI6_K); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); + int * x_sc = (int *) (x_df + MMQ_TILE_NE_K/QI6_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q6_K, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); int * x_sc = (int *) (x_df + txs.dm); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR6_K); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -1634,67 +2054,67 @@ template static __device__ __forceinlin const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride; - const int ql = get_int_b2(bxi->ql, threadIdx.x); + const int ql = get_int_b2(bxi->ql, txi); const int ql0 = (ql >> 0) & 0x0F0F0F0F; const int ql1 = (ql >> 4) & 0x0F0F0F0F; - const int qh = get_int_b2(bxi->qh, (QI6_K/4) * (threadIdx.x / (QI6_K/2)) + threadIdx.x % (QI6_K/4)); - const int qh0 = ((qh >> ((threadIdx.x & 0x08) >> 2)) << 4) & 0x30303030; - const int qh1 = (qh >> ((threadIdx.x & 0x08) >> 2)) & 0x30303030; + const int qh = get_int_b2(bxi->qh, (QI6_K/4) * (txi / (QI6_K/2)) + txi % (QI6_K/4)); + const int qh0 = ((qh >> ((txi & 0x08) >> 2)) << 4) & 0x30303030; + const int qh1 = (qh >> ((txi & 0x08) >> 2)) & 0x30303030; - const int kq0 = 2*threadIdx.x - threadIdx.x % (QI6_K/2) + 0; - const int kq1 = 2*threadIdx.x - threadIdx.x % (QI6_K/2) + QI6_K/2; + const int kq0 = 2*txi - txi % (QI6_K/2) + 0; + const int kq1 = 2*txi - txi % (QI6_K/2) + QI6_K/2; -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q6_K + kq0] = __vsubss4(ql0 | qh0, 0x20202020); x_qs[i*MMQ_MMA_TILE_X_K_Q6_K + kq1] = __vsubss4(ql1 | qh1, 0x20202020); #else - x_qs[i*(2*WARP_SIZE + 1) + kq0] = __vsubss4(ql0 | qh0, 0x20202020); - x_qs[i*(2*WARP_SIZE + 1) + kq1] = __vsubss4(ql1 | qh1, 0x20202020); -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kq0] = __vsubss4(ql0 | qh0, 0x20202020); + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kq1] = __vsubss4(ql1 | qh1, 0x20202020); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI6_K; // == 1 if QK_K == 256 - const int kbxd = threadIdx.x % blocks_per_tile_x_row; // == 0 if QK_K == 256 - #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI6_K) { - int i = (i0 + threadIdx.y * QI6_K + threadIdx.x / blocks_per_tile_x_row) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*warp_size) { + int i = (i0 + threadIdx.y*warp_size + threadIdx.x) % mmq_y; if (need_check) { i = min(i, i_max); } - const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride + kbxd; + const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q6_K + kbxd] = bxi->d; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q6_K] = bxi->d; #else - x_df[i*(WARP_SIZE/QI6_K) + i/QI6_K + kbxd] = bxi->d; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/QI6_K) + i/QI6_K] = bxi->d; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } + constexpr int rows_per_warp = warp_size / 4; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * 8) { - int i = (i0 + threadIdx.y * 8 + threadIdx.x / (WARP_SIZE/8)) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*rows_per_warp) { + int i = (i0 + threadIdx.y*rows_per_warp + threadIdx.x/(MMQ_TILE_NE_K/8)) % mmq_y; if (need_check) { i = min(i, i_max); } - const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride + (threadIdx.x % (WARP_SIZE/8)) / 4; + const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride + (threadIdx.x % (MMQ_TILE_NE_K/8)) / 4; -#ifdef NEW_MMA_AVAILABLE - x_sc[i*MMQ_MMA_TILE_X_K_Q6_K + threadIdx.x % (WARP_SIZE/8)] = get_int_b2(bxi->scales, threadIdx.x % (QI6_K/8)); +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_sc[i*MMQ_MMA_TILE_X_K_Q6_K + threadIdx.x%4] = get_int_b2(bxi->scales, threadIdx.x % (MMQ_TILE_NE_K/8)); #else - x_sc[i*(WARP_SIZE/8) + i/8 + threadIdx.x % (WARP_SIZE/8)] = get_int_b2(bxi->scales, threadIdx.x % (QI6_K/8)); -#endif // NEW_MMA_AVAILABLE + x_sc[i*(MMQ_TILE_NE_K/8) + i/8 + threadIdx.x%(MMQ_TILE_NE_K/8)] = get_int_b2(bxi->scales, threadIdx.x%(QI6_K/8)); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void vec_dot_q6_K_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q6_K, mmq_y); const int * x_qs = (const int *) x; @@ -1704,7 +2124,7 @@ static __device__ __forceinline__ void vec_dot_q6_K_q8_1_dp4a( const float * y_df = (const float *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR6_K*VDR_Q6_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR6_K*VDR_Q6_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1712,23 +2132,74 @@ static __device__ __forceinline__ void vec_dot_q6_K_q8_1_dp4a( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - const int8_t * sc = ((const int8_t *) &x_sc[i * (WARP_SIZE/8) + i/8 + k0/16]); + const int8_t * sc = ((const int8_t *) &x_sc[i * (MMQ_TILE_NE_K/8) + i/8 + k0/16]); - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q6_K_q8_1_impl_mmq( - &x_qs[i*(QR6_K*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], sc, - x_df[i*(WARP_SIZE/QI6_K) + i/QI6_K], &y_df[j*MMQ_TILE_Y_K + k01/QI8_1]); + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q6_K_q8_1_impl_mmq( + &x_qs[i*(QR6_K*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], sc, + x_df[i*(MMQ_TILE_NE_K/QI6_K) + i/QI6_K], &y_df[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template +template static __device__ __forceinline__ void vec_dot_q6_K_q8_1_mma( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) + typedef tile<16, 8, int> tile_A; + typedef tile<16, 8, int> tile_B; + typedef tile<16, 16, int> tile_C; + typedef tile<64, 2, int> tile_load; + + constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int rows_per_warp = granularity; + constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. + + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); + + const int * x_qs = (const int *) x; + const float * x_df = (const float *) x_qs + MMQ_TILE_NE_K*2; + const int * x_sc = (const int *) x_df + MMQ_TILE_NE_K/QI6_K; + const int * y_qs = (const int *) y + 4; + const float * y_df = (const float *) y; + + const int i0 = (threadIdx.y / ntx) * rows_per_warp; + + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 4) { + const int k0 = k00 + k01; + + tile_A A[ntx]; +#pragma unroll + for (int n = 0; n < ntx; ++n) { + load_generic(((tile_load *) A)[n], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q6_K + k0, MMQ_MMA_TILE_X_K_Q6_K); + } + +#pragma unroll + for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { + tile_B B[1]; + load_generic(((tile_load *) B)[0], y_qs + j0*MMQ_TILE_Y_K + k01, MMQ_TILE_Y_K); + + const int j = j0 + tile_C::get_j(0); + const float dB = y_df[j*MMQ_TILE_Y_K + k01/QI8_1] / 2; + +#pragma unroll + for (int n = 0; n < ntx; ++n) { + tile_C C; + mma(C, A[n], B[0]); + +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = i0 + n*tile_C::I + tile_C::get_i(l); + const int8_t * sc = (const int8_t *) (x_sc + i*MMQ_MMA_TILE_X_K_Q6_K + k00/16); + sum[(j0/tile_C::J + n)*tile_C::ne + l] += C.x[l] * sc[k01/4] * x_df[i*MMQ_MMA_TILE_X_K_Q6_K] * dB; + } + } + } + } +#elif defined(TURING_MMA_AVAILABLE) typedef tile<16, 4, int> tile_A; typedef tile< 8, 4, int> tile_B; @@ -1738,11 +2209,11 @@ static __device__ __forceinline__ void vec_dot_q6_K_q8_1_mma( constexpr int rows_per_warp = 2 * granularity; constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. - y += (threadIdx.y % ntx) * (tile_B::I*MMQ_TILE_Y_K); + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); const int * x_qs = (const int *) x; - const float * x_df = (const float *) x_qs + WARP_SIZE*2; - const int * x_sc = (const int *) x_df + WARP_SIZE/QI6_K; + const float * x_df = (const float *) x_qs + MMQ_TILE_NE_K*2; + const int * x_sc = (const int *) x_df + MMQ_TILE_NE_K/QI6_K; const int * y_qs = (const int *) y + 4; const float * y_df = (const float *) y; @@ -1755,7 +2226,7 @@ static __device__ __forceinline__ void vec_dot_q6_K_q8_1_mma( #pragma unroll for (int n = 0; n < ntx; ++n) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += 8) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 8) { const int k0 = k00 + k01; load_ldmatrix(A[n][k01/4 + 0], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q6_K + (k0 + 0), MMQ_MMA_TILE_X_K_Q6_K); @@ -1763,7 +2234,7 @@ static __device__ __forceinline__ void vec_dot_q6_K_q8_1_mma( } #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += 16) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 16) { const int k0 = k00 + k01; #pragma unroll @@ -1793,7 +2264,7 @@ static __device__ __forceinline__ void vec_dot_q6_K_q8_1_mma( float tmp[ntx][tile_C::ne] = {{0.0f}}; #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += 8) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 8) { tile_B B[2]; float dB[tile_C::ne/2]; @@ -1832,27 +2303,32 @@ static __device__ __forceinline__ void vec_dot_q6_K_q8_1_mma( #else GGML_UNUSED(x); GGML_UNUSED(y); GGML_UNUSED(sum); GGML_UNUSED(k00); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // AMD_MFMA_AVAILABLE } -template static __device__ __forceinline__ void load_tiles_iq4_nl( +template static __device__ __forceinline__ void load_tiles_iq4_nl( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ4_NL, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI4_NL; - const int kqsx = threadIdx.x % QI4_NL; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR4_NL); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI4_NL; + const int kqsx = txi % QI4_NL; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -1861,23 +2337,25 @@ template static __device__ __forceinlin const block_iq4_nl * bxi = (const block_iq4_nl *) x + kbx0 + i*stride + kbx; const int aux_q4 = get_int_b2(bxi->qs, kqsx); - const int2 v = get_int_from_table_16(aux_q4); - const int k0 = 8 * (threadIdx.x / 4) + threadIdx.x % 4; -#ifdef NEW_MMA_AVAILABLE - x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 0] = v.x; - x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 4] = v.y; + const int2 v = get_int_from_table_16(aux_q4, kvalues_iq4nl); + const int k0 = kbx * (2 * QI4_NL) + kqsx; + +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 0] = v.x; + x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + QI4_NL] = v.y; #else - x_qs[i*(2*WARP_SIZE + 1) + k0 + 0] = v.x; - x_qs[i*(2*WARP_SIZE + 1) + k0 + 4] = v.y; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + 0] = v.x; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + QI4_NL] = v.y; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI4_NL; + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI4_NL; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; const int kbxd = threadIdx.x % blocks_per_tile_x_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI4_NL) { - int i = i0 + threadIdx.y * QI4_NL + threadIdx.x / blocks_per_tile_x_row; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; if (need_check) { i = min(i, i_max); @@ -1885,31 +2363,35 @@ template static __device__ __forceinlin const block_iq4_nl * bxi = (const block_iq4_nl *) x + kbx0 + i*stride + kbxd; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = __half2float(bxi->d); +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = __half2float(bxi->d); #else - x_df[i*(WARP_SIZE/4) + i/4 + kbxd] = __half2float(bxi->d); -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/QI4_NL) + i/QI4_NL + kbxd] = __half2float(bxi->d); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq2_xxs( +template static __device__ __forceinline__ void load_tiles_iq2_xxs( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ2_XXS, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % (QI2_XXS/2); + constexpr int threads_per_row = (MMQ_ITER_K / (4 * QR2_XXS)) / 2; + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/(QI2_XXS/2)) { - int i = i0 + threadIdx.y*(2*WARP_SIZE/QI2_XXS) + threadIdx.x/(QI2_XXS/2); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -1932,42 +2414,46 @@ template static __device__ __forceinlin const int signs1 = __vcmpne4(((signs_packed & 0x30) << 3) | ((signs_packed & 0xC0) << 17), 0x00000000); const int grid1 = __vsub4(grid_pos[1] ^ signs1, signs1); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 8*kqsx + (2*l + 0)] = grid0; x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 8*kqsx + (2*l + 1)] = grid1; #else - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l + 0)] = grid0; - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l + 1)] = grid1; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l + 0)] = grid0; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l + 1)] = grid1; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } const int ls = aux32 >> 28; const float d = bxi->d; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = (ls*d + d/2)/4; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = (ls*d + d/2)/4; #else - x_df[i*(WARP_SIZE/4) + i/4 + kqsx] = (ls*d + d/2)/4; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/4) + i/4 + kqsx] = (ls*d + d/2)/4; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq2_xs( +template static __device__ __forceinline__ void load_tiles_iq2_xs( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = MMQ_DP4A_TXS_Q8_0_16; int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % (QI2_XS/2); + constexpr int threads_per_row = (MMQ_ITER_K / (4 * QR2_XS)) / 2; + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/(QI2_XS/2)) { - int i = i0 + threadIdx.y*(2*WARP_SIZE/QI2_XS) + threadIdx.x/(QI2_XS/2); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -1986,44 +2472,48 @@ template static __device__ __forceinlin const int grid_l = __vsub4(grid_pos[0] ^ signs[0], signs[0]); const int grid_h = __vsub4(grid_pos[1] ^ signs[1], signs[1]); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q3_K + 8*kqsx + (2*l + 0)] = grid_l; x_qs[i*MMQ_MMA_TILE_X_K_Q3_K + 8*kqsx + (2*l + 1)] = grid_h; #else - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l + 0)] = grid_l; - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l + 1)] = grid_h; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l + 0)] = grid_l; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l + 1)] = grid_h; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } const int ls = bxi->scales[kqsx]; const float d = bxi->d; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; - x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; #else - x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; - x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; -#endif // NEW_MMA_AVAILABLE + x_df[i*(2*MMQ_TILE_NE_K*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; + x_df[i*(2*MMQ_TILE_NE_K*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq2_s( +template static __device__ __forceinline__ void load_tiles_iq2_s( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ2_S, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % (QI2_S/2); + constexpr int threads_per_row = (MMQ_ITER_K / (4 * QR2_S)) / 2; + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/(QI2_S/2)) { - int i = i0 + threadIdx.y*(2*WARP_SIZE/QI2_S) + threadIdx.x/(QI2_S/2); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -2049,44 +2539,48 @@ template static __device__ __forceinlin const int grid_l = __vsub4(grid_pos[0] ^ signs0, signs0); const int grid_h = __vsub4(grid_pos[1] ^ signs1, signs1); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q3_K + 8*kqsx + (2*l + 0)] = grid_l; x_qs[i*MMQ_MMA_TILE_X_K_Q3_K + 8*kqsx + (2*l + 1)] = grid_h; #else - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l + 0)] = grid_l; - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l + 1)] = grid_h; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l + 0)] = grid_l; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l + 1)] = grid_h; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } const int ls = bxi->scales[kqsx]; const float d = bxi->d; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; - x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; #else - x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; - x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; -#endif // NEW_MMA_AVAILABLE + x_df[i*(2*MMQ_TILE_NE_K*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; + x_df[i*(2*MMQ_TILE_NE_K*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq3_xxs( +template static __device__ __forceinline__ void load_tiles_iq3_xxs( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ3_XXS, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % (QI3_XXS/2); + constexpr int threads_per_row = (MMQ_ITER_K / (4 * QR3_XXS)) / 2; + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/(QI3_XXS/2)) { - int i = i0 + threadIdx.y*(2*WARP_SIZE/QI3_XXS) + threadIdx.x/(QI3_XXS/2); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -2107,42 +2601,46 @@ template static __device__ __forceinlin const int grid_l = __vsub4(grid_pos.x ^ signs[0], signs[0]); const int grid_h = __vsub4(grid_pos.y ^ signs[1], signs[1]); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 8*kqsx + (2*l + 0)] = grid_l; x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 8*kqsx + (2*l + 1)] = grid_h; #else - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l + 0)] = grid_l; - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l + 1)] = grid_h; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l + 0)] = grid_l; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l + 1)] = grid_h; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } const int ls = aux32 >> 28; const float d = bxi->d; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = (ls*d + d/2)/2; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = (ls*d + d/2)/2; #else - x_df[i*(WARP_SIZE/4) + i/4 + kqsx] = (ls*d + d/2)/2; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/4) + i/4 + kqsx] = (ls*d + d/2)/2; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq3_s( +template static __device__ __forceinline__ void load_tiles_iq3_s( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ3_S, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % (QI3_S/2); + constexpr int threads_per_row = (MMQ_ITER_K / (4 * QR3_S)) / 2; + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/(QI3_S/2)) { - int i = i0 + threadIdx.y*(2*WARP_SIZE/QI3_S) + threadIdx.x/(QI3_S/2); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -2170,42 +2668,46 @@ template static __device__ __forceinlin const int grid_l = __vsub4(grid_pos.x ^ signs0, signs0); const int grid_h = __vsub4(grid_pos.y ^ signs1, signs1); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 8*kqsx + (2*l+0)] = grid_l; x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 8*kqsx + (2*l+1)] = grid_h; #else - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l+0)] = grid_l; - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l+1)] = grid_h; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l+0)] = grid_l; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l+1)] = grid_h; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } const int ls = 1 + 2*((bxi->scales[kqsx/2] >> (((2*kqsx) << 1) & 0x04)) & 0x0F); const float d = bxi->d; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = ls*d; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = ls*d; #else - x_df[i*(WARP_SIZE/4) + i/4 + kqsx] = ls*d; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/4) + i/4 + kqsx] = ls*d; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq1_s( +template static __device__ __forceinline__ void load_tiles_iq1_s( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_ds = (half2 *) (x_qs + WARP_SIZE*2); + half2 * x_ds = (half2 *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ3_S, mmq_y); int * x_qs = (int *) x_tile; half2 * x_ds = (half2 *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % QI1_S; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR1_S); + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/QI1_S) { - int i = i0 + threadIdx.y*(WARP_SIZE/QI1_S) + threadIdx.x/QI1_S; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -2225,66 +2727,71 @@ template static __device__ __forceinlin const int grid0 = (grid >> 0) & 0x0F0F0F0F; const int grid1 = (grid >> 4) & 0x0F0F0F0F; -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 8*kqsx + (2*l+0)] = grid0; x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 8*kqsx + (2*l+1)] = grid1; #else - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l+0)] = grid0; - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l+1)] = grid1; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l+0)] = grid0; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l+1)] = grid1; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } const float d1q = __half2float(bxi->d) * (((qh >> 11) & 0x0E) + 1); const float delta = -1.0f + IQ1S_DELTA - (qh & 0x8000) * (2.0f*IQ1S_DELTA/0x8000); -#ifdef NEW_MMA_AVAILABLE - x_ds[i*MMQ_MMA_TILE_X_K_Q8_1 + kqsx] = make_half2(d1q, d1q*delta); +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_ds[i*MMQ_MMA_TILE_X_K_Q8_1 + kqsx] = make_half2(d1q, d1q*delta); #else - x_ds[i*(WARP_SIZE/4) + i/4 + kqsx] = make_half2(d1q, d1q*delta); -#endif // NEW_MMA_AVAILABLE + x_ds[i*(MMQ_TILE_NE_K/4) + i/4 + kqsx] = make_half2(d1q, d1q*delta); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq4_xs( +template static __device__ __forceinline__ void load_tiles_iq4_xs( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ4_XS, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = 0; // threadIdx.x / QI4_XS - const int kqsx = threadIdx.x; // threadIdx.x % QI4_XS + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR4_XS); + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); } - const block_iq4_xs * bxi = (const block_iq4_xs *) x + kbx0 + i*stride + kbx; + const block_iq4_xs * bxi = (const block_iq4_xs *) x + kbx0 + i*stride; const int aux_q4 = get_int_b4(bxi->qs, kqsx); - const int2 v = get_int_from_table_16(aux_q4); - const int k0 = 8 * (threadIdx.x / 4) + threadIdx.x % 4; -#ifdef NEW_MMA_AVAILABLE + const int2 v = get_int_from_table_16(aux_q4, kvalues_iq4nl); + const int k0 = 8 * (kqsx / 4) + kqsx % 4; + +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 0] = v.x; x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 4] = v.y; #else - x_qs[i*(2*WARP_SIZE + 1) + k0 + 0] = v.x; - x_qs[i*(2*WARP_SIZE + 1) + k0 + 4] = v.y; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + 0] = v.x; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + 4] = v.y; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } + constexpr int rows_per_warp = warp_size / 8; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * 4) { - int i = i0 + threadIdx.y * 4 + threadIdx.x / (WARP_SIZE/4); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / (MMQ_TILE_NE_K/4); if (need_check) { i = min(i, i_max); @@ -2297,18 +2804,21 @@ template static __device__ __forceinlin const int ls = ((bxi->scales_l[(threadIdx.x % 8)/2] >> (4*(threadIdx.x % 2))) & 0x0F) | (((bxi->scales_h >> (2*(threadIdx.x % 8))) & 0x03) << 4); -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + threadIdx.x % 8] = d * (ls - 32); +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + threadIdx.x % 8] = d * (ls - 32); #else - x_df[i*(WARP_SIZE/4) + i/4 + threadIdx.x % 8] = d * (ls - 32); -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/4) + i/4 + threadIdx.x % 8] = d * (ls - 32); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void mmq_write_back_dp4a( const float * __restrict__ sum, const int32_t * __restrict__ ids_dst, float * __restrict__ dst, const int stride, const int i_max, const int j_max) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + #pragma unroll for (int j0 = 0; j0 < mmq_x; j0 += nwarps) { const int j = j0 + threadIdx.y; @@ -2318,32 +2828,40 @@ static __device__ __forceinline__ void mmq_write_back_dp4a( } #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; if (need_check && i > i_max) { continue; } - dst[ids_dst[j]*stride + i] = sum[(j0/nwarps) * (mmq_y/WARP_SIZE) + i0/WARP_SIZE]; + dst[ids_dst[j]*stride + i] = sum[(j0/nwarps) * (mmq_y/warp_size) + i0/warp_size]; } } } -template +template static __device__ __forceinline__ void mmq_write_back_mma( const float * __restrict__ sum, const int * __restrict__ ids_dst, float * __restrict__ dst, const int stride, const int i_max, const int j_max) { - typedef tile<16, 8, int> tile_C; constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int nwarps = mmq_get_nwarps_device(); + +#if defined(AMD_MFMA_AVAILABLE) + constexpr int tileC_IJ = mmq_get_granularity_device(0); + typedef tile tile_C; + constexpr int rows_per_warp = granularity; +#else + typedef tile<16, 8, int> tile_C; constexpr int rows_per_warp = 2 * granularity; +#endif constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. const int i0 = (threadIdx.y / ntx) * (ntx*tile_C::I); -#ifdef NEW_MMA_AVAILABLE +#if defined(TURING_MMA_AVAILABLE) || defined(AMD_MFMA_AVAILABLE) static_assert(nwarps*tile_C::I == mmq_y, "nwarps*tile_C::I != mmq_y"); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) #pragma unroll for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { @@ -2371,179 +2889,189 @@ static __device__ __forceinline__ void mmq_write_back_mma( // ------------------------------------------------------------------------------------------------------------------------------------- -template +template struct mmq_type_traits; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q4_0_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_0; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_0; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q4_1_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_1; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_1_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_1; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_1_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q5_0_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_0; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_0; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q5_1_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_1; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_1_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_1; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_1_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q8_0_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q8_0; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q8_0; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { + static constexpr int vdr = VDR_MXFP4_Q8_1_MMQ; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_mxfp4; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; +}; + +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q2_K_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q2_K; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q2_K_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q2_K_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q2_K; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q2_K_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q2_K_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q3_K_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q3_K; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q3_K_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q3_K; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q3_K_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q4_K_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_K; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_K_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_K; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_K_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q5_K_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_K; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q5_K_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_K; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q5_K_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q6_K_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q6_K; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q6_K_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q6_K_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q6_K; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q6_K_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q6_K_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ2_XXS_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_xxs; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_xxs; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ2_XS_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_xs; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_16_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_xs; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_16_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ2_S_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_s; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_16_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_s; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_16_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ3_XXS_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq3_xxs; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq3_xxs; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ3_S_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq3_s; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq3_s; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ1_S_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq1_s; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_1_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq1_s; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_1_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ4_NL_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq4_nl; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq4_nl; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ4_XS_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq4_xs; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq4_xs; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template +template static __device__ __forceinline__ void mul_mat_q_process_tile( const char * __restrict__ x, const int offset_x, const int * __restrict__ y, const int * __restrict__ ids_dst, float * __restrict__ dst, float * __restrict__ tmp_fixup, const int stride_row_x, const int ncols_y, const int stride_col_dst, const int tile_x_max_i, const int tile_y_max_j, const int kb0_start, const int kb0_stop) { + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + constexpr int nwarps = mmq_get_nwarps_device(); constexpr int qk = ggml_cuda_type_traits::qk; constexpr int mmq_y = get_mmq_y_device(); - constexpr load_tiles_mmq_t load_tiles = mmq_type_traits::load_tiles; + constexpr load_tiles_mmq_t load_tiles = mmq_type_traits::load_tiles; extern __shared__ int data_mul_mat_q[]; int * tile_y = data_mul_mat_q + mmq_x; - int * tile_x = tile_y + GGML_PAD(mmq_x*(WARP_SIZE + WARP_SIZE/QI8_1), nwarps*WARP_SIZE); + int * tile_x = tile_y + GGML_PAD(mmq_x*MMQ_TILE_Y_K, nwarps*warp_size); -#ifdef NEW_MMA_AVAILABLE - constexpr vec_dot_mmq_t vec_dot = mmq_type_traits::vec_dot_mma; - constexpr mmq_write_back_t write_back = mmq_write_back_mma; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + constexpr vec_dot_mmq_t vec_dot = mmq_type_traits::vec_dot_mma; + constexpr mmq_write_back_t write_back = mmq_write_back_mma; #else - constexpr vec_dot_mmq_t vec_dot = mmq_type_traits::vec_dot_dp4a; - constexpr mmq_write_back_t write_back = mmq_write_back_dp4a; -#endif // NEW_MMA_AVAILABLE + constexpr vec_dot_mmq_t vec_dot = mmq_type_traits::vec_dot_dp4a; + constexpr mmq_write_back_t write_back = mmq_write_back_dp4a; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) constexpr int blocks_per_iter = MMQ_ITER_K / qk; - float sum[mmq_x*mmq_y / (nwarps*WARP_SIZE)] = {0.0f}; + float sum[mmq_x*mmq_y / (nwarps*warp_size)] = {0.0f}; for (int kb0 = kb0_start; kb0 < kb0_stop; kb0 += blocks_per_iter) { load_tiles(x, tile_x, offset_x + kb0, tile_x_max_i, stride_row_x); @@ -2551,8 +3079,8 @@ static __device__ __forceinline__ void mul_mat_q_process_tile( { const int * by0 = y + ncols_y*(kb0*(qk*sizeof(block_q8_1_mmq) / (4*QK8_1*sizeof(int))) + 0*sizeof(block_q8_1_mmq)/sizeof(int)); #pragma unroll - for (int l0 = 0; l0 < mmq_x*MMQ_TILE_Y_K; l0 += nwarps*WARP_SIZE) { - int l = l0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int l0 = 0; l0 < mmq_x*MMQ_TILE_Y_K; l0 += nwarps*warp_size) { + int l = l0 + threadIdx.y*warp_size + threadIdx.x; tile_y[l] = by0[l]; } @@ -2567,8 +3095,8 @@ static __device__ __forceinline__ void mul_mat_q_process_tile( { const int * by0 = y + ncols_y*(kb0*(qk*sizeof(block_q8_1_mmq) / (4*QK8_1*sizeof(int))) + 1*sizeof(block_q8_1_mmq)/sizeof(int)); #pragma unroll - for (int l0 = 0; l0 < mmq_x*MMQ_TILE_Y_K; l0 += nwarps*WARP_SIZE) { - int l = l0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int l0 = 0; l0 < mmq_x*MMQ_TILE_Y_K; l0 += nwarps*warp_size) { + int l = l0 + threadIdx.y*warp_size + threadIdx.x; tile_y[l] = by0[l]; } @@ -2576,7 +3104,7 @@ static __device__ __forceinline__ void mul_mat_q_process_tile( __syncthreads(); - vec_dot(tile_x, tile_y, sum, WARP_SIZE); + vec_dot(tile_x, tile_y, sum, MMQ_TILE_NE_K); __syncthreads(); } @@ -2591,18 +3119,18 @@ static __device__ __forceinline__ void mul_mat_q_process_tile( // The mul_mat_q kernel implements "stream-k" work partitioning as described in https://arxiv.org/abs/2301.03598 -template -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +template +#if defined(GGML_USE_HIP) #if defined(RDNA4) || defined(RDNA3) || defined(RDNA2) || defined(CDNA) || defined(GCN) - __launch_bounds__(WARP_SIZE*nwarps, 2) + __launch_bounds__(ggml_cuda_get_physical_warp_size()*mmq_get_nwarps_device(), 2) #endif // defined(RDNA4) || defined(RDNA3) || defined(RDNA2) || defined(CDNA) || defined(GCN) #else #if __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA - __launch_bounds__(WARP_SIZE*nwarps, 1) + __launch_bounds__(ggml_cuda_get_physical_warp_size()*mmq_get_nwarps_device(), 1) #else - __launch_bounds__(WARP_SIZE*nwarps, 2) + __launch_bounds__(ggml_cuda_get_physical_warp_size()*mmq_get_nwarps_device(), 2) #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#endif // defined(GGML_USE_HIP) static __global__ void mul_mat_q( const char * __restrict__ x, const int * __restrict__ y, const int32_t * __restrict__ ids_dst, const int32_t * __restrict__ expert_bounds, float * __restrict__ dst, float * __restrict__ tmp_fixup, @@ -2616,6 +3144,9 @@ static __global__ void mul_mat_q( return; } + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + constexpr int qk = ggml_cuda_type_traits::qk; constexpr int mmq_y = get_mmq_y_device(); @@ -2627,10 +3158,10 @@ static __global__ void mul_mat_q( // For MoE the correct indices are loaded from ids_dst. extern __shared__ int ids_dst_shared[]; // Stored at beginning of shared memory. #pragma unroll - for (int j0 = 0; j0 < mmq_x; j0 += nwarps*WARP_SIZE) { - const int j = j0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int j0 = 0; j0 < mmq_x; j0 += nwarps*warp_size) { + const int j = j0 + threadIdx.y*warp_size + threadIdx.x; - if (j0 + nwarps*WARP_SIZE > mmq_x && j >= mmq_x) { + if (j0 + nwarps*warp_size > mmq_x && j >= mmq_x) { break; } @@ -2638,8 +3169,8 @@ static __global__ void mul_mat_q( } __syncthreads(); - // On AMD or old CUDA the performance with stream-k was worse, use conventional tiling instead: -#if (defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) || __CUDA_ARCH__ < GGML_CUDA_CC_VOLTA + // On non-CDNA AMD or old CUDA the performance with stream-k was worse, use conventional tiling instead: +#if (defined(GGML_USE_HIP) && !defined(CDNA)) || __CUDA_ARCH__ < GGML_CUDA_CC_VOLTA { const int wt = blockIdx.z / nchannels_y; const int zt = blockIdx.z - wt*nchannels_y; @@ -2667,10 +3198,10 @@ static __global__ void mul_mat_q( // __syncthreads(); // There is no previous tile that could cause a race condition. #pragma unroll - for (int j0 = 0; j0 < mmq_x; j0 += nwarps*WARP_SIZE) { - const int j = j0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int j0 = 0; j0 < mmq_x; j0 += nwarps*warp_size) { + const int j = j0 + threadIdx.y*warp_size + threadIdx.x; - if (j0 + nwarps*WARP_SIZE > mmq_x && j >= mmq_x) { + if (j0 + nwarps*warp_size > mmq_x && j >= mmq_x) { break; } @@ -2688,12 +3219,12 @@ static __global__ void mul_mat_q( const int offset_x = (wt/sample_ratio)*stride_sample_x + (zt/channel_ratio)*stride_channel_x + it*mmq_y*stride_row_x; constexpr bool fixup = false; - mul_mat_q_process_tile + mul_mat_q_process_tile (x, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, stride_row_x, ncols_y, stride_col_dst, tile_x_max_i, tile_y_max_j, 0, ncols_x/qk); return; } -#endif // (defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) || __CUDA_ARCH__ < GGML_CUDA_CC_VOLTA +#endif // (defined(GGML_USE_HIP) && !defined(CDNA3)) || __CUDA_ARCH__ < GGML_CUDA_CC_VOLTA const int64_t blocks_per_ne00 = ncols_x / qk; constexpr int blocks_per_iter = MMQ_ITER_K / qk; @@ -2745,10 +3276,10 @@ static __global__ void mul_mat_q( __syncthreads(); #pragma unroll - for (int j0 = 0; j0 < mmq_x; j0 += nwarps*WARP_SIZE) { - const int j = j0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int j0 = 0; j0 < mmq_x; j0 += nwarps*warp_size) { + const int j = j0 + threadIdx.y*warp_size + threadIdx.x; - if (j0 + nwarps*WARP_SIZE > mmq_x && j >= mmq_x) { + if (j0 + nwarps*warp_size > mmq_x && j >= mmq_x) { break; } @@ -2766,7 +3297,7 @@ static __global__ void mul_mat_q( const int offset_x = (wt/sample_ratio)*stride_sample_x + (zt/channel_ratio)*stride_channel_x + it*mmq_y*stride_row_x; constexpr bool fixup = false; // All but (potentially) the last iterations write their data to dst rather than the fixup buffer. - mul_mat_q_process_tile + mul_mat_q_process_tile (x, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, stride_row_x, ncols_y, stride_col_dst, tile_x_max_i, tile_y_max_j, kb0_start, kb0_stop); @@ -2812,10 +3343,10 @@ static __global__ void mul_mat_q( // The memory layout for the fixup buffer is always contiguous, therefore reset ids: __syncthreads(); #pragma unroll - for (int j0 = 0; j0 < mmq_x; j0 += nwarps*WARP_SIZE) { - const int j = j0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int j0 = 0; j0 < mmq_x; j0 += nwarps*warp_size) { + const int j = j0 + threadIdx.y*warp_size + threadIdx.x; - if (j0 + nwarps*WARP_SIZE > mmq_x && j >= mmq_x) { + if (j0 + nwarps*warp_size > mmq_x && j >= mmq_x) { break; } @@ -2833,13 +3364,13 @@ static __global__ void mul_mat_q( const int offset_x = (wt/sample_ratio)*stride_sample_x + (zt/channel_ratio)*stride_channel_x + it*mmq_y*stride_row_x; constexpr bool fixup = true; // Last index writes its data to fixup buffer to avoid data races with other blocks. - mul_mat_q_process_tile + mul_mat_q_process_tile (x, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, stride_row_x, ncols_y, stride_col_dst, tile_x_max_i, tile_y_max_j, kb0_start, kb0_stop); } -template +template static __global__ void mul_mat_q_stream_k_fixup( const int32_t * ids_dst, const int32_t * expert_bounds, float * __restrict__ dst, const float * __restrict__ tmp_last_tile, const int ncols_x, const int nrows_x, const int ncols_dst, const int stride_col_dst, @@ -2849,7 +3380,10 @@ static __global__ void mul_mat_q_stream_k_fixup( constexpr int blocks_per_iter = MMQ_ITER_K / qk; const int64_t blocks_per_ne00 = ncols_x / qk; - float sum[mmq_x*mmq_y / (nwarps*WARP_SIZE)] = {0.0f}; + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + + float sum[mmq_x*mmq_y / (nwarps*warp_size)] = {0.0f}; const int ntx = (ncols_dst + mmq_x - 1) / mmq_x; const int nty = (nrows_x + mmq_y - 1) / mmq_y; @@ -2893,10 +3427,10 @@ static __global__ void mul_mat_q_stream_k_fixup( const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - sum[(j0/nwarps) * (mmq_y/WARP_SIZE) + i0/WARP_SIZE] += tmp_last_tile[bidx*(mmq_x*mmq_y) + j*mmq_y + i]; + sum[(j0/nwarps) * (mmq_y/warp_size) + i0/warp_size] += tmp_last_tile[bidx*(mmq_x*mmq_y) + j*mmq_y + i]; } } @@ -2937,14 +3471,14 @@ static __global__ void mul_mat_q_stream_k_fixup( } #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; if (need_check && i > i_max) { continue; } - dst[j*stride_col_dst + i] += sum[(j0/nwarps) * (mmq_y/WARP_SIZE) + i0/WARP_SIZE]; + dst[j*stride_col_dst + i] += sum[(j0/nwarps) * (mmq_y/warp_size) + i0/warp_size]; } } return; @@ -2955,7 +3489,7 @@ static __global__ void mul_mat_q_stream_k_fixup( const int col_high = expert_bounds[zt + 1]; const int col_diff = col_high - col_low; - for (int j = threadIdx.y*WARP_SIZE + threadIdx.x; j < mmq_x; j += nwarps*WARP_SIZE) { + for (int j = threadIdx.y*warp_size + threadIdx.x; j < mmq_x; j += nwarps*warp_size) { ids_dst_shared[j] = ids_dst[col_low + j]; } __syncthreads(); @@ -2975,14 +3509,14 @@ static __global__ void mul_mat_q_stream_k_fixup( } #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; if (need_check && i > i_max) { continue; } - dst[ids_dst_shared[j]*stride_col_dst + i] += sum[(j0/nwarps) * (mmq_y/WARP_SIZE) + i0/WARP_SIZE]; + dst[ids_dst_shared[j]*stride_col_dst + i] += sum[(j0/nwarps) * (mmq_y/warp_size) + i0/warp_size]; } } } @@ -2996,13 +3530,13 @@ struct mmq_args { }; template -static size_t mmq_get_nbytes_shared(const int mmq_x, const int mmq_y, const int cc) { +static size_t mmq_get_nbytes_shared(const int mmq_x, const int mmq_y, const int cc, const int warp_size, const int nwarps) { const tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(type, mmq_y); const int mmq_tile_x_k = mmq_get_mma_tile_x_k(type); const size_t nbs_ids = mmq_x*sizeof(int); - const size_t nbs_x = new_mma_available(cc) ? mmq_y*mmq_tile_x_k*sizeof(int) : txs.qs*sizeof(int) + txs.dm*sizeof(half2) + txs.sc*sizeof(int); + const size_t nbs_x = (turing_mma_available(cc) || amd_mfma_available(cc)) ? mmq_y*mmq_tile_x_k*sizeof(int) : txs.qs*sizeof(int) + txs.dm*sizeof(half2) + txs.sc*sizeof(int); const size_t nbs_y = mmq_x*sizeof(block_q8_1_mmq); - return nbs_ids + nbs_x + GGML_PAD(nbs_y, MMQ_NWARPS*WARP_SIZE*sizeof(int)); + return nbs_ids + nbs_x + GGML_PAD(nbs_y, nwarps*warp_size*sizeof(int)); } template @@ -3010,14 +3544,16 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a const int id = ggml_cuda_get_device(); const int cc = ggml_cuda_info().devices[id].cc; const int nsm = ggml_cuda_info().devices[id].nsm; + const int warp_size = ggml_cuda_info().devices[id].warp_size; + const int nwarps = mmq_get_nwarps_host(cc, warp_size); const int mmq_y = get_mmq_y_host(cc); - const dim3 block_dims(WARP_SIZE, MMQ_NWARPS, 1); + const dim3 block_dims(warp_size, nwarps, 1); - const int nbytes_shared = mmq_get_nbytes_shared(mmq_x, mmq_y, cc); + const int nbytes_shared = mmq_get_nbytes_shared(mmq_x, mmq_y, cc, warp_size, nwarps); - CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); - CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); + CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); + CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); const int nty = (args.nrows_x + mmq_y - 1) / mmq_y; const int ntx = (args.ncols_dst + mmq_x - 1) / mmq_x; @@ -3032,14 +3568,14 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a if (!args.use_stream_k) { if (args.nrows_x % mmq_y == 0) { constexpr bool need_check = false; - mul_mat_q<<>> + mul_mat_q<<>> (args.x, args.y, args.ids_dst, args.expert_bounds, args.dst, nullptr, args.ncols_x, args.nrows_x, args.ncols_dst, args.stride_row_x, args.ncols_y, args.nrows_dst, channel_ratio, args.nchannels_y, args.stride_channel_x, args.stride_channel_y, args.stride_channel_dst, sample_ratio, args.nsamples_y, args.stride_sample_x, args.stride_sample_y, args.stride_sample_dst); } else { constexpr bool need_check = true; - mul_mat_q<<>> + mul_mat_q<<>> (args.x, args.y, args.ids_dst, args.expert_bounds, args.dst, nullptr, args.ncols_x, args.nrows_x, args.ncols_dst, args.stride_row_x, args.ncols_y, args.nrows_dst, channel_ratio, args.nchannels_y, args.stride_channel_x, args.stride_channel_y, args.stride_channel_dst, @@ -3059,8 +3595,7 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a if (args.nrows_x % mmq_y == 0) { constexpr bool need_check = false; - - mul_mat_q<<>> + mul_mat_q<<>> (args.x, args.y, args.ids_dst, args.expert_bounds, args.dst, tmp_fixup.ptr, args.ncols_x, args.nrows_x, args.ncols_dst, args.stride_row_x, args.ncols_y, args.nrows_dst, channel_ratio, args.nchannels_y, args.stride_channel_x, args.stride_channel_y, args.stride_channel_dst, @@ -3070,13 +3605,12 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a return; } - mul_mat_q_stream_k_fixup<<>> + mul_mat_q_stream_k_fixup<<>> (args.ids_dst, args.expert_bounds, args.dst, tmp_fixup.ptr, args.ncols_x, args.nrows_x, args.ncols_dst, args.nrows_dst, args.nchannels_y, args.stride_channel_dst, args.nsamples_y, args.stride_sample_dst); } else { constexpr bool need_check = true; - - mul_mat_q<<>> + mul_mat_q<<>> (args.x, args.y, args.ids_dst, args.expert_bounds, args.dst, tmp_fixup.ptr, args.ncols_x, args.nrows_x, args.ncols_dst, args.stride_row_x, args.ncols_y, args.nrows_dst, channel_ratio, args.nchannels_y, args.stride_channel_x, args.stride_channel_y, args.stride_channel_dst, @@ -3086,7 +3620,7 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a return; } - mul_mat_q_stream_k_fixup<<>> + mul_mat_q_stream_k_fixup<<>> (args.ids_dst, args.expert_bounds, args.dst, tmp_fixup.ptr, args.ncols_x, args.nrows_x, args.ncols_dst, args.nrows_dst, args.nchannels_y, args.stride_channel_dst, args.nsamples_y, args.stride_sample_dst); } @@ -3094,9 +3628,11 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a template void mul_mat_q_case(ggml_backend_cuda_context & ctx, const mmq_args & args, cudaStream_t stream) { - const int id = ggml_cuda_get_device(); - const int cc = ggml_cuda_info().devices[id].cc; - const size_t smpbo = ggml_cuda_info().devices[id].smpbo; + const int id = ggml_cuda_get_device(); + const int cc = ggml_cuda_info().devices[id].cc; + const size_t smpbo = ggml_cuda_info().devices[id].smpbo; + const int warp_size = ggml_cuda_info().devices[id].warp_size; + const int nwarps = mmq_get_nwarps_host(cc, warp_size); const int mmq_x_max = get_mmq_x_max_host(cc); const int mmq_y = get_mmq_y_host(cc); @@ -3107,7 +3643,7 @@ void mul_mat_q_case(ggml_backend_cuda_context & ctx, const mmq_args & args, cuda for (int mmq_x = 8; mmq_x <= mmq_x_max && ntiles_x_best > 1; mmq_x += 8) { const int granularity = mmq_get_granularity_host(mmq_x, cc); - if (mmq_x % granularity != 0 || mmq_get_nbytes_shared(mmq_x, mmq_y, cc) > smpbo) { + if (mmq_x % granularity != 0 || mmq_get_nbytes_shared(mmq_x, mmq_y, cc, warp_size, nwarps) > smpbo) { continue; } @@ -3183,6 +3719,7 @@ extern DECL_MMQ_CASE(GGML_TYPE_Q4_1); extern DECL_MMQ_CASE(GGML_TYPE_Q5_0); extern DECL_MMQ_CASE(GGML_TYPE_Q5_1); extern DECL_MMQ_CASE(GGML_TYPE_Q8_0); +extern DECL_MMQ_CASE(GGML_TYPE_MXFP4); extern DECL_MMQ_CASE(GGML_TYPE_Q2_K); extern DECL_MMQ_CASE(GGML_TYPE_Q3_K); extern DECL_MMQ_CASE(GGML_TYPE_Q4_K); diff --git a/ggml/src/ggml-cuda/mmv.cu b/ggml/src/ggml-cuda/mmvf.cu similarity index 85% rename from ggml/src/ggml-cuda/mmv.cu rename to ggml/src/ggml-cuda/mmvf.cu index e14c93516b..16100b6804 100644 --- a/ggml/src/ggml-cuda/mmv.cu +++ b/ggml/src/ggml-cuda/mmvf.cu @@ -1,9 +1,10 @@ #include "ggml.h" #include "common.cuh" -#include "mmv.cuh" +#include "convert.cuh" +#include "mmvf.cuh" template -static __global__ void mul_mat_vec( +static __global__ void mul_mat_vec_f( const T * __restrict__ x, const float * __restrict__ y, const int32_t * __restrict__ ids, float * __restrict__ dst, const int ncols2, const int nchannels_y, const int stride_row, const int stride_col_y2, const int stride_col_dst, const int channel_ratio, const int stride_channel_x, const int stride_channel_y, const int stride_channel_dst, @@ -37,7 +38,7 @@ static __global__ void mul_mat_vec( float sumf[ncols_dst] = {0.0f}; - if constexpr (std::is_same::value) { + if constexpr (std::is_same_v) { const float2 * x2 = (const float2 *) x; for (int col2 = tid; col2 < ncols2; col2 += block_size) { @@ -50,10 +51,10 @@ static __global__ void mul_mat_vec( sumf[j] += tmpx.y*tmpy.y; } } - } else if constexpr (std::is_same::value) { + } else if constexpr (std::is_same_v) { const half2 * x2 = (const half2 *) x; - if (std::is_same::value) { + if (std::is_same_v) { for (int col2 = tid; col2 < ncols2; col2 += block_size) { const float2 tmpx = __half22float2(x2[col2]); @@ -86,19 +87,19 @@ static __global__ void mul_mat_vec( NO_DEVICE_CODE; #endif // FP16_AVAILABLE } - } else if constexpr (std::is_same::value) { + } else if constexpr (std::is_same_v) { const int * x2 = (const int *) x; for (int col2 = tid; col2 < ncols2; col2 += block_size) { const int tmpx = x2[col2]; #pragma unroll for (int j = 0; j < ncols_dst; ++j) { const float2 tmpy = y2[j*stride_col_y2 + col2]; - sumf[j] += float(reinterpret_cast(&tmpx)[0]) * tmpy.x; - sumf[j] += float(reinterpret_cast(&tmpx)[1]) * tmpy.y; + sumf[j] += ggml_cuda_cast(reinterpret_cast(&tmpx)[0]) * tmpy.x; + sumf[j] += ggml_cuda_cast(reinterpret_cast(&tmpx)[1]) * tmpy.y; } } } else { - static_assert(std::is_same::value, "unsupported type"); + static_assert(std::is_same_v, "unsupported type"); } #pragma unroll @@ -126,7 +127,7 @@ static __global__ void mul_mat_vec( } template -static void launch_mul_mat_vec_cuda( +static void launch_mul_mat_vec_f_cuda( const T * x, const float * y, const int32_t * ids, float * dst, const int64_t ncols, const int64_t nrows, const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, @@ -141,11 +142,9 @@ static void launch_mul_mat_vec_cuda( GGML_ASSERT( nsamples_dst % nsamples_x == 0); const int64_t channel_ratio = nchannels_dst / nchannels_x; const int64_t sample_ratio = nsamples_dst / nsamples_x; - int device; - int warp_size; - CUDA_CHECK(cudaGetDevice(&device)); - warp_size = ggml_cuda_info().devices[device].warp_size; + const int device = ggml_cuda_get_device(); + const int warp_size = ggml_cuda_info().devices[device].warp_size; int64_t block_size_best = warp_size; int64_t niter_best = (ncols + 2*warp_size - 1) / (2*warp_size); @@ -161,54 +160,54 @@ static void launch_mul_mat_vec_cuda( } } - const int smem = warp_size*sizeof(float); + const int nbytes_shared = warp_size*sizeof(float); const dim3 block_nums(nrows, nchannels_dst, nsamples_dst); const dim3 block_dims(block_size_best, 1, 1); switch (block_size_best) { case 32: { - mul_mat_vec<<>> + mul_mat_vec_f<<>> (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); } break; case 64: { - mul_mat_vec<<>> + mul_mat_vec_f<<>> (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); } break; case 96: { - mul_mat_vec<<>> + mul_mat_vec_f<<>> (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); } break; case 128: { - mul_mat_vec<<>> + mul_mat_vec_f<<>> (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); } break; case 160: { - mul_mat_vec<<>> + mul_mat_vec_f<<>> (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); } break; case 192: { - mul_mat_vec<<>> + mul_mat_vec_f<<>> (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); } break; case 224: { - mul_mat_vec<<>> + mul_mat_vec_f<<>> (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); } break; case 256: { - mul_mat_vec<<>> + mul_mat_vec_f<<>> (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); @@ -220,7 +219,7 @@ static void launch_mul_mat_vec_cuda( } template -static void mul_mat_vec_cuda_switch_ncols_dst( +static void mul_mat_vec_f_cuda_switch_ncols_dst( const T * x, const float * y, const int32_t * ids, float * dst, const int64_t ncols, const int64_t nrows, const int64_t ncols_dst, const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, @@ -230,49 +229,49 @@ static void mul_mat_vec_cuda_switch_ncols_dst( cudaStream_t stream) { switch (ncols_dst) { case 1: - launch_mul_mat_vec_cuda + launch_mul_mat_vec_f_cuda (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); break; case 2: - launch_mul_mat_vec_cuda + launch_mul_mat_vec_f_cuda (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); break; case 3: - launch_mul_mat_vec_cuda + launch_mul_mat_vec_f_cuda (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); break; case 4: - launch_mul_mat_vec_cuda + launch_mul_mat_vec_f_cuda (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); break; case 5: - launch_mul_mat_vec_cuda + launch_mul_mat_vec_f_cuda (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); break; case 6: - launch_mul_mat_vec_cuda + launch_mul_mat_vec_f_cuda (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); break; case 7: - launch_mul_mat_vec_cuda + launch_mul_mat_vec_f_cuda (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); break; case 8: - launch_mul_mat_vec_cuda + launch_mul_mat_vec_f_cuda (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); @@ -284,7 +283,7 @@ static void mul_mat_vec_cuda_switch_ncols_dst( } template -static void mul_mat_vec_cuda( +static void mul_mat_vec_f_cuda( const T * x, const float * y, const int32_t * ids, float * dst, const int64_t ncols, const int64_t nrows, const int64_t ncols_dst, const int64_t stride_row, const int64_t stride_col_y, const int stride_col_dst, @@ -292,22 +291,22 @@ static void mul_mat_vec_cuda( const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x, const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, enum ggml_prec prec, cudaStream_t stream) { - if constexpr(std::is_same::value) { + if constexpr(std::is_same_v) { if (prec == GGML_PREC_DEFAULT) { - mul_mat_vec_cuda_switch_ncols_dst + mul_mat_vec_f_cuda_switch_ncols_dst (x, y, ids, dst, ncols, nrows, ncols_dst, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); return; } } - mul_mat_vec_cuda_switch_ncols_dst + mul_mat_vec_f_cuda_switch_ncols_dst (x, y, ids, dst, ncols, nrows, ncols_dst, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); } -void ggml_cuda_mul_mat_vec(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst) { +void ggml_cuda_mul_mat_vec_f(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst) { GGML_ASSERT( src1->type == GGML_TYPE_F32); GGML_ASSERT(!ids || ids->type == GGML_TYPE_I32); GGML_ASSERT( dst->type == GGML_TYPE_F32); @@ -355,19 +354,19 @@ void ggml_cuda_mul_mat_vec(ggml_backend_cuda_context & ctx, const ggml_tensor * switch (src0->type) { case GGML_TYPE_F32: { const float * src0_d = (const float *) src0->data; - mul_mat_vec_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, + mul_mat_vec_f_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, ne02, nchannels_y, nchannels_dst, s02, stride_channel_y, stride_channel_dst, ne03, ne3, s03, s13, s3, prec, ctx.stream()); } break; case GGML_TYPE_F16: { const half * src0_d = (const half *) src0->data; - mul_mat_vec_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, + mul_mat_vec_f_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, ne02, nchannels_y, nchannels_dst, s02, stride_channel_y, stride_channel_dst, ne03, ne3, s03, s13, s3, prec, ctx.stream()); } break; case GGML_TYPE_BF16: { const nv_bfloat16 * src0_d = (const nv_bfloat16 *) src0->data; - mul_mat_vec_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, + mul_mat_vec_f_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, ne02, nchannels_y, nchannels_dst, s02, stride_channel_y, stride_channel_dst, ne03, ne3, s03, s13, s3, prec, ctx.stream()); } break; @@ -376,7 +375,7 @@ void ggml_cuda_mul_mat_vec(ggml_backend_cuda_context & ctx, const ggml_tensor * } } -void ggml_cuda_op_mul_mat_vec( +void ggml_cuda_op_mul_mat_vec_f( ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, const char * src0_dd_i, const float * src1_ddf_i, const char * src1_ddq_i, float * dst_dd_i, const int64_t row_low, const int64_t row_high, const int64_t src1_ncols, @@ -414,19 +413,19 @@ void ggml_cuda_op_mul_mat_vec( switch (src0->type) { case GGML_TYPE_F32: { const float * src0_d = (const float *) src0_dd_i; - mul_mat_vec_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, + mul_mat_vec_f_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, prec, stream); } break; case GGML_TYPE_F16: { const half * src0_d = (const half *) src0_dd_i; - mul_mat_vec_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, + mul_mat_vec_f_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, prec, stream); } break; case GGML_TYPE_BF16: { const nv_bfloat16 * src0_d = (const nv_bfloat16 *) src0_dd_i; - mul_mat_vec_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, + mul_mat_vec_f_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, prec, stream); } break; @@ -442,15 +441,15 @@ void ggml_cuda_op_mul_mat_vec( GGML_UNUSED(src1_padded_row_size); } -bool ggml_cuda_should_use_mmv(enum ggml_type type, int cc, const int64_t * src0_ne, int64_t ne11) { +bool ggml_cuda_should_use_mmvf(enum ggml_type type, int cc, const int64_t * src0_ne, int64_t ne11) { if (src0_ne[0] % 2 != 0) { return false; } switch (type) { case GGML_TYPE_F32: if (GGML_CUDA_CC_IS_NVIDIA(cc)) { - if (cc >= GGML_CUDA_CC_ADA_LOVELACE) { - return ne11 <= 8; + if (ampere_mma_available(cc)) { + return ne11 <= 3; } if (cc >= GGML_CUDA_CC_TURING) { return ne11 <= 4; @@ -466,6 +465,9 @@ bool ggml_cuda_should_use_mmv(enum ggml_type type, int cc, const int64_t * src0_ case GGML_TYPE_F16: if (GGML_CUDA_CC_IS_NVIDIA(cc)) { const bool src0_small = (src0_ne[1] <= 512 || src0_ne[2]*src0_ne[3] == 1); + if (ampere_mma_available(cc)) { + return src0_small && ne11 == 1; + } if (cc >= GGML_CUDA_CC_ADA_LOVELACE) { return src0_small && ne11 <= 4; } @@ -486,6 +488,9 @@ bool ggml_cuda_should_use_mmv(enum ggml_type type, int cc, const int64_t * src0_ case GGML_TYPE_BF16: if (GGML_CUDA_CC_IS_NVIDIA(cc)) { const bool src0_small = (src0_ne[1] <= 512 || src0_ne[2]*src0_ne[3] == 1); + if (ampere_mma_available(cc)) { + return src0_small && ne11 == 1; + } if (cc >= GGML_CUDA_CC_ADA_LOVELACE) { return src0_small && ne11 <= 4; } diff --git a/ggml/src/ggml-cuda/mmv.cuh b/ggml/src/ggml-cuda/mmvf.cuh similarity index 55% rename from ggml/src/ggml-cuda/mmv.cuh rename to ggml/src/ggml-cuda/mmvf.cuh index 1330bcb6a8..1da460992e 100644 --- a/ggml/src/ggml-cuda/mmv.cuh +++ b/ggml/src/ggml-cuda/mmvf.cuh @@ -1,11 +1,11 @@ #include "common.cuh" -void ggml_cuda_mul_mat_vec(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst); +void ggml_cuda_mul_mat_vec_f(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst); -void ggml_cuda_op_mul_mat_vec( +void ggml_cuda_op_mul_mat_vec_f( ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, const char * src0_dd_i, const float * src1_ddf_i, const char * src1_ddq_i, float * dst_dd_i, const int64_t row_low, const int64_t row_high, const int64_t src1_ncols, const int64_t src1_padded_row_size, cudaStream_t stream); -bool ggml_cuda_should_use_mmv(enum ggml_type type, int cc, const int64_t * src0_ne, int64_t ne11); +bool ggml_cuda_should_use_mmvf(enum ggml_type type, int cc, const int64_t * src0_ne, int64_t ne11); diff --git a/ggml/src/ggml-cuda/mmvq.cu b/ggml/src/ggml-cuda/mmvq.cu index dc7adf509f..5c8e5c4a7e 100644 --- a/ggml/src/ggml-cuda/mmvq.cu +++ b/ggml/src/ggml-cuda/mmvq.cu @@ -13,6 +13,7 @@ static constexpr __device__ vec_dot_q_cuda_t get_vec_dot_q_cuda(ggml_type type) case GGML_TYPE_Q5_0: return vec_dot_q5_0_q8_1; case GGML_TYPE_Q5_1: return vec_dot_q5_1_q8_1; case GGML_TYPE_Q8_0: return vec_dot_q8_0_q8_1; + case GGML_TYPE_MXFP4: return vec_dot_mxfp4_q8_1; case GGML_TYPE_Q2_K: return vec_dot_q2_K_q8_1; case GGML_TYPE_Q3_K: return vec_dot_q3_K_q8_1; case GGML_TYPE_Q4_K: return vec_dot_q4_K_q8_1; @@ -38,6 +39,7 @@ static constexpr __device__ int get_vdr_mmvq(ggml_type type) { case GGML_TYPE_Q5_0: return VDR_Q5_0_Q8_1_MMVQ; case GGML_TYPE_Q5_1: return VDR_Q5_1_Q8_1_MMVQ; case GGML_TYPE_Q8_0: return VDR_Q8_0_Q8_1_MMVQ; + case GGML_TYPE_MXFP4: return VDR_MXFP4_Q8_1_MMVQ; case GGML_TYPE_Q2_K: return VDR_Q2_K_Q8_1_MMVQ; case GGML_TYPE_Q3_K: return VDR_Q3_K_Q8_1_MMVQ; case GGML_TYPE_Q4_K: return VDR_Q4_K_Q8_1_MMVQ; @@ -384,6 +386,13 @@ static void mul_mat_vec_q_switch_type( nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); break; + case GGML_TYPE_MXFP4: + mul_mat_vec_q_switch_ncols_dst + (vx, vy, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row_x, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, + stream); + break; case GGML_TYPE_Q2_K: mul_mat_vec_q_switch_ncols_dst (vx, vy, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row_x, stride_col_y, stride_col_dst, diff --git a/ggml/src/ggml-cuda/norm.cu b/ggml/src/ggml-cuda/norm.cu index 0020dbcec5..bddcca51b7 100644 --- a/ggml/src/ggml-cuda/norm.cu +++ b/ggml/src/ggml-cuda/norm.cu @@ -104,10 +104,12 @@ static __global__ void group_norm_f32(const float * x, float * dst, const int gr } } -template +template static __global__ void rms_norm_f32( const float * x, float * dst, const int ncols, const int64_t stride_row, const int64_t stride_channel, - const int64_t stride_sample, const float eps) { + const int64_t stride_sample, const float eps, const float * mul = nullptr, const int64_t mul_stride_row = 0, + const int64_t mul_stride_channel = 0, const int64_t mul_stride_sample = 0, const int mul_ncols = 0, + const int mul_nrows = 0, const int mul_nchannels = 0, const int mul_nsamples = 0) { const int nrows = gridDim.x; const int nchannels = gridDim.y; @@ -119,6 +121,13 @@ static __global__ void rms_norm_f32( x += sample*stride_sample + channel*stride_channel + row*stride_row; dst += ((sample*nchannels + channel)*nrows + row)*ncols; + if constexpr (do_multiply) { + const int mul_row = row % mul_nrows; + const int mul_channel = channel % mul_nchannels; + const int mul_sample = sample % mul_nsamples; + mul += mul_sample*mul_stride_sample + mul_channel*mul_stride_channel + mul_row*mul_stride_row; + } + float tmp = 0.0f; // partial sum for thread in warp for (int col = tid; col < ncols; col += block_size) { @@ -145,7 +154,12 @@ static __global__ void rms_norm_f32( const float scale = rsqrtf(mean + eps); for (int col = tid; col < ncols; col += block_size) { - dst[col] = scale * x[col]; + if constexpr (do_multiply) { + const int mul_col = col % mul_ncols; + dst[col] = scale * x[col] * mul[mul_col]; + } else { + dst[col] = scale * x[col]; + } } } @@ -310,10 +324,30 @@ static void rms_norm_f32_cuda( const dim3 blocks_num(nrows, nchannels, nsamples); if (ncols < 1024) { const dim3 block_dims(WARP_SIZE, 1, 1); - rms_norm_f32<<>>(x, dst, ncols, stride_row, stride_channel, stride_sample, eps); + rms_norm_f32<<>>(x, dst, ncols, stride_row, stride_channel, stride_sample, eps); } else { const dim3 block_dims(1024, 1, 1); - rms_norm_f32<1024><<>>(x, dst, ncols, stride_row, stride_channel, stride_sample, eps); + rms_norm_f32<1024, false><<>>(x, dst, ncols, stride_row, stride_channel, stride_sample, eps); + } +} + +static void rms_norm_mul_f32_cuda( + const float * x, const float * mul, float * dst, const int ncols, const int nrows, const int nchannels, const int nsamples, + const int64_t stride_row, const int64_t stride_channel, const int64_t stride_sample, + const int64_t mul_stride_row, const int64_t mul_stride_channel, const int64_t mul_stride_sample, + const int mul_ncols, const int mul_nrows, const int mul_nchannels, const int mul_nsamples, + const float eps, cudaStream_t stream) { + const dim3 blocks_num(nrows, nchannels, nsamples); + if (mul == nullptr) { + rms_norm_f32_cuda(x, dst, ncols, nrows, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, stream); + return; + } + if (ncols < 1024) { + const dim3 block_dims(WARP_SIZE, 1, 1); + rms_norm_f32<<>>(x, dst, ncols, stride_row, stride_channel, stride_sample, eps, mul, mul_stride_row, mul_stride_channel, mul_stride_sample, mul_ncols, mul_nrows, mul_nchannels, mul_nsamples); + } else { + const dim3 block_dims(1024, 1, 1); + rms_norm_f32<1024, true><<>>(x, dst, ncols, stride_row, stride_channel, stride_sample, eps, mul, mul_stride_row, mul_stride_channel, mul_stride_sample, mul_ncols, mul_nrows, mul_nchannels, mul_nsamples); } } @@ -407,6 +441,59 @@ void ggml_cuda_op_rms_norm(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { rms_norm_f32_cuda(src0_d, dst_d, ne00, ne01, ne02, ne03, s01, s02, s03, eps, stream); } +void ggml_cuda_op_rms_norm_fused(ggml_backend_cuda_context & ctx, ggml_tensor * dst, ggml_tensor * mul_tensor) { + const ggml_tensor * rms_norm_src = (ggml_tensor *) dst->src[0]; + float eps = 0.0f; + + memcpy(&eps, dst->op_params, sizeof(float)); + + const float * src0_d = (const float *) rms_norm_src->data; + const float * mul_d = nullptr; + const ggml_tensor * mul_src = nullptr; + + if (mul_tensor->src[0] == dst) { + mul_d = (float *) mul_tensor->src[1]->data; + mul_src = mul_tensor->src[1]; + } else if(mul_tensor->src[1] == dst) { + mul_d = (float *) mul_tensor->src[0]->data; + mul_src = mul_tensor->src[0]; + } else { + GGML_ASSERT(false); + } + + float * dst_d = (float *) mul_tensor->data; + cudaStream_t stream = ctx.stream(); + + GGML_ASSERT(rms_norm_src->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); + GGML_ASSERT(mul_tensor->type == GGML_TYPE_F32); + GGML_ASSERT(eps >= 0.0f); + + const int64_t ne00 = rms_norm_src->ne[0]; + const int64_t ne01 = rms_norm_src->ne[1]; + const int64_t ne02 = rms_norm_src->ne[2]; + const int64_t ne03 = rms_norm_src->ne[3]; + + const size_t ts0 = ggml_type_size(rms_norm_src->type); + GGML_ASSERT(rms_norm_src->nb[0] == ts0); + const int64_t s01 = rms_norm_src->nb[1] / ts0; + const int64_t s02 = rms_norm_src->nb[2] / ts0; + const int64_t s03 = rms_norm_src->nb[3] / ts0; + + const size_t ts_mul = ggml_type_size(mul_src->type); + GGML_ASSERT(mul_src->nb[0] == ts_mul); + const int64_t mul_s01 = mul_src->nb[1] / ts_mul; + const int64_t mul_s02 = mul_src->nb[2] / ts_mul; + const int64_t mul_s03 = mul_src->nb[3] / ts_mul; + + const int mul_ncols = mul_src->ne[0]; + const int mul_nrows = mul_src->ne[1]; + const int mul_nchannels = mul_src->ne[2]; + const int mul_nsamples = mul_src->ne[3]; + + rms_norm_mul_f32_cuda(src0_d, mul_d, dst_d, ne00, ne01, ne02, ne03, s01, s02, s03, mul_s01, mul_s02, mul_s03, mul_ncols, mul_nrows, mul_nchannels, mul_nsamples, eps, stream); +} + void ggml_cuda_op_rms_norm_back(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const ggml_tensor * grad = dst->src[0]; // gradients const ggml_tensor * src0f = dst->src[1]; // src0 from forward pass diff --git a/ggml/src/ggml-cuda/norm.cuh b/ggml/src/ggml-cuda/norm.cuh index 706a5660a6..7ea7bd4df3 100644 --- a/ggml/src/ggml-cuda/norm.cuh +++ b/ggml/src/ggml-cuda/norm.cuh @@ -6,6 +6,8 @@ void ggml_cuda_op_group_norm(ggml_backend_cuda_context & ctx, ggml_tensor * dst) void ggml_cuda_op_rms_norm(ggml_backend_cuda_context & ctx, ggml_tensor * dst); +void ggml_cuda_op_rms_norm_fused(ggml_backend_cuda_context & ctx, ggml_tensor * dst, ggml_tensor * mul_tensor); + void ggml_cuda_op_rms_norm_back(ggml_backend_cuda_context & ctx, ggml_tensor * dst); void ggml_cuda_op_l2_norm(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff --git a/ggml/src/ggml-cuda/opt-step-sgd.cu b/ggml/src/ggml-cuda/opt-step-sgd.cu new file mode 100644 index 0000000000..460b16de44 --- /dev/null +++ b/ggml/src/ggml-cuda/opt-step-sgd.cu @@ -0,0 +1,49 @@ +#include "ggml-impl.h" +#include "opt-step-sgd.cuh" + +#include + +static __global__ void opt_step_sgd_f32( + float * __restrict__ x, const float * __restrict__ g, + const float * __restrict__ pars, const int64_t k) { + + const int64_t i = (int64_t) blockIdx.x*blockDim.x + threadIdx.x; + + if (i >= k) { + return; + } + x[i] = x[i] * (1.0f - pars[0] * pars[1]) - pars[0] * g[i]; +} + +static void opt_step_sgd_f32_cuda( + float * x, const float * g, const float * __restrict__ pars, const int64_t k, cudaStream_t stream) { + + const dim3 block_dims(CUDA_OPT_STEP_SGD_BLOCK_SIZE, 1, 1); + const dim3 block_nums((k + CUDA_OPT_STEP_SGD_BLOCK_SIZE - 1) / CUDA_OPT_STEP_SGD_BLOCK_SIZE, 1, 1); + opt_step_sgd_f32<<>>(x, g, pars, k); +} + +void ggml_cuda_opt_step_sgd(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src0_grad = dst->src[1]; + const ggml_tensor * params = dst->src[2]; + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(src0_grad->type == GGML_TYPE_F32); + GGML_ASSERT(params->type == GGML_TYPE_F32); + GGML_ASSERT(ggml_is_contiguous(src0)); + GGML_ASSERT(ggml_is_contiguous(src0_grad)); + GGML_ASSERT(ggml_is_contiguous(params)); + GGML_ASSERT(ggml_are_same_shape(src0, src0_grad)); + GGML_ASSERT(ggml_nelements(params) == 2); + + float * src0_d = (float *) src0->data; + const float * src0_grad_d = (const float *) src0_grad->data; + const float * params_d = (const float *) params->data; + + cudaStream_t stream = ctx.stream(); + + const int64_t ne = ggml_nelements(src0); + + opt_step_sgd_f32_cuda(src0_d, src0_grad_d, params_d, ne, stream); +} diff --git a/ggml/src/ggml-cuda/opt-step-sgd.cuh b/ggml/src/ggml-cuda/opt-step-sgd.cuh new file mode 100644 index 0000000000..f97ab7d9be --- /dev/null +++ b/ggml/src/ggml-cuda/opt-step-sgd.cuh @@ -0,0 +1,5 @@ +#include "common.cuh" + +#define CUDA_OPT_STEP_SGD_BLOCK_SIZE 256 + +void ggml_cuda_opt_step_sgd(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff --git a/ggml/src/ggml-cuda/reduce_rows.cuh b/ggml/src/ggml-cuda/reduce_rows.cuh new file mode 100644 index 0000000000..6bee204136 --- /dev/null +++ b/ggml/src/ggml-cuda/reduce_rows.cuh @@ -0,0 +1,53 @@ +#include "common.cuh" + +// Row reduction kernel template - compute sum (norm=false) or mean (norm=true) +template +static __global__ void reduce_rows_f32(const float * __restrict__ x, float * __restrict__ dst, const int ncols) { + const int row = blockIdx.x; + const int col = threadIdx.x; + + float sum = 0.0f; + const int num_unroll = 8; + float temp[num_unroll]; + float sum_temp[num_unroll] = { 0.0f }; + for (int i = col; i < ncols;) { + for (int j = 0; j < num_unroll; ++j) { + if (i < ncols) { + temp[j] = x[row * ncols + i]; + } else { + temp[j] = 0; + } + i += blockDim.x; + } + for (int j = 0; j < num_unroll; ++j) { + sum_temp[j] += temp[j]; + } + } + for (int j = 0; j < num_unroll; ++j) { + sum += sum_temp[j]; + } + + // sum up partial sums + sum = warp_reduce_sum(sum); + if (blockDim.x > WARP_SIZE) { + assert((blockDim.x <= 1024) && (blockDim.x % WARP_SIZE) == 0); + __shared__ float s_sum[32]; + const int warp_id = threadIdx.x / WARP_SIZE; + const int lane_id = threadIdx.x % WARP_SIZE; + if (lane_id == 0) { + s_sum[warp_id] = sum; + } + __syncthreads(); + sum = 0.0f; + if (lane_id < (blockDim.x / WARP_SIZE)) { + sum = s_sum[lane_id]; + } + sum = warp_reduce_sum(sum); + } + + if (col != 0) { + return; + } + + dst[row] = norm ? sum / ncols : sum; +} diff --git a/ggml/src/ggml-cuda/roll.cu b/ggml/src/ggml-cuda/roll.cu new file mode 100644 index 0000000000..a339dfc1ae --- /dev/null +++ b/ggml/src/ggml-cuda/roll.cu @@ -0,0 +1,67 @@ +#include "ggml-cuda/common.cuh" +#include "roll.cuh" + +static __forceinline__ __device__ int64_t wrap_index(const int64_t idx, const int64_t ne) { + if (idx < 0) { + return idx + ne; + } + if (idx >= ne) { + return idx - ne; + } + return idx; +} + +static __global__ void roll_f32_cuda(const float * __restrict__ src, + float * __restrict__ dst, + const int64_t ne00, + const int64_t ne01, + const int64_t ne02, + const int64_t ne03, + const int s0, + const int s1, + const int s2, + const int s3) { + const int64_t idx = int64_t(blockDim.x) * blockIdx.x + threadIdx.x; + const int64_t n_elements = ne00 * ne01 * ne02 * ne03; + + if (idx >= n_elements) { + return; + } + + const int64_t i0 = idx % ne00; + const int64_t i1 = (idx / ne00) % ne01; + const int64_t i2 = (idx / (ne00 * ne01)) % ne02; + const int64_t i3 = (idx / (ne00 * ne01 * ne02)) % ne03; + + const int64_t d0 = wrap_index(i0 - s0, ne00); + const int64_t d1 = wrap_index(i1 - s1, ne01); + const int64_t d2 = wrap_index(i2 - s2, ne02); + const int64_t d3 = wrap_index(i3 - s3, ne03); + + dst[i3 * (ne00 * ne01 * ne02) + i2 * (ne01 * ne00) + i1 * ne00 + i0] = + src[d3 * (ne00 * ne01 * ne02) + d2 * (ne01 * ne00) + d1 * ne00 + d0]; +} + +void ggml_cuda_op_roll(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + int s0 = dst->op_params[0]; + int s1 = dst->op_params[1]; + int s2 = dst->op_params[2]; + int s3 = dst->op_params[3]; + + const ggml_tensor * src0 = dst->src[0]; + const float * src0_d = (const float *) dst->src[0]->data; + float * dst_d = (float *) dst->data; + + GGML_TENSOR_UNARY_OP_LOCALS; + + GGML_ASSERT(dst->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(ggml_are_same_shape(dst->src[0], dst)); + + cudaStream_t stream = ctx.stream(); + + int64_t sz = (ne00 * ne01 * ne02 * ne03); + int64_t num_blocks = (sz + CUDA_ROLL_BLOCK_SIZE - 1) / CUDA_ROLL_BLOCK_SIZE; + + roll_f32_cuda<<>>( + src0_d, dst_d, ne00, ne01, ne02, ne03, s0, s1, s2, s3); +} diff --git a/ggml/src/ggml-cuda/roll.cuh b/ggml/src/ggml-cuda/roll.cuh new file mode 100644 index 0000000000..322d55436e --- /dev/null +++ b/ggml/src/ggml-cuda/roll.cuh @@ -0,0 +1,5 @@ +#include "common.cuh" + +#define CUDA_ROLL_BLOCK_SIZE 256 + +void ggml_cuda_op_roll(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff --git a/ggml/src/ggml-cuda/set-rows.cu b/ggml/src/ggml-cuda/set-rows.cu index 560604d095..b4115a43c2 100644 --- a/ggml/src/ggml-cuda/set-rows.cu +++ b/ggml/src/ggml-cuda/set-rows.cu @@ -3,27 +3,6 @@ typedef void (*set_rows_kernel_t)(const char * src, char * dst); -template -__device__ void set_rows_1(const src_t * src_f, dst_t * dst_f) { - GGML_UNUSED(src_f); - GGML_UNUSED(dst_f); -} - -template<> -__device__ __forceinline__ void set_rows_1(const float * src_f, half * dst_h) { - convert_f32_f16(src_f, dst_h); -} - -template<> -__device__ __forceinline__ void set_rows_1(const float * src_f, nv_bfloat16 * dst_b) { - convert_f32_bf16(src_f, dst_b); -} - -template<> -__device__ __forceinline__ void set_rows_1(const float * src_f, float * dst_f) { - convert_f32_f32(src_f, dst_f); -} - // Generic quantized set_rows kernel template template static __global__ void k_set_rows_quant( @@ -60,6 +39,9 @@ static __global__ void k_set_rows_quant( block_type * dst_block = dst_row_ptr + i00 / qk; quantize_func(src_block, dst_block); + + GGML_UNUSED(ne10); + GGML_UNUSED(ne13); } // Template dispatch function for quantized set_rows @@ -130,9 +112,7 @@ static __global__ void k_set_rows( const src_t * src0_row = src0 + i01*s01 + i02*s02 + i03*s03; dst_t * dst_row_ptr = dst + dst_row*s1 + i02*s2 + i03*s3; - const src_t* src_elem = src0_row + i00; - dst_t* dst_elem = dst_row_ptr + i00; - set_rows_1(src_elem, dst_elem); + dst_row_ptr[i00] = ggml_cuda_cast(src0_row[i00]); GGML_UNUSED(ne10); GGML_UNUSED(ne13); diff --git a/ggml/src/ggml-cuda/softcap.cu b/ggml/src/ggml-cuda/softcap.cu new file mode 100644 index 0000000000..40dfe45d65 --- /dev/null +++ b/ggml/src/ggml-cuda/softcap.cu @@ -0,0 +1,34 @@ +#include "softcap.cuh" + +static __global__ void softcap_f32(const float * x, float * dst, const float scale, const float softcap, const int k) { + const int i = blockDim.x*blockIdx.x + threadIdx.x; + + if (i >= k) { + return; + } + + dst[i] = tanhf(scale * x[i]) * softcap; +} + +static void softcap_f32_cuda(const float * x, float * dst, const float scale, const float softcap, const int k, cudaStream_t stream) { + const int num_blocks = (k + CUDA_SOFTCAP_BLOCK_SIZE - 1) / CUDA_SOFTCAP_BLOCK_SIZE; + softcap_f32<<>>(x, dst, scale, softcap, k); +} + +// fused GGML_OP_SCALE + GGML_UNARY_OP_TANH + GGML_OP_SCALE +void ggml_cuda_op_softcap(ggml_backend_cuda_context & ctx, ggml_tensor * dst, ggml_tensor * src) { + const ggml_tensor * src0 = src->src[0]; + const float * src0_d = (const float *)src0->data; + float * dst_d = (float *)dst->data; + cudaStream_t stream = ctx.stream(); + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT( dst->type == GGML_TYPE_F32); + + float scale; + float softcap; + memcpy(&scale, (float *) src->op_params + 0, sizeof(float)); + memcpy(&softcap, (float *) dst->op_params + 0, sizeof(float)); + + softcap_f32_cuda(src0_d, dst_d, scale, softcap, ggml_nelements(src0), stream); +} diff --git a/ggml/src/ggml-cuda/softcap.cuh b/ggml/src/ggml-cuda/softcap.cuh new file mode 100644 index 0000000000..6d34fb2bee --- /dev/null +++ b/ggml/src/ggml-cuda/softcap.cuh @@ -0,0 +1,5 @@ +#include "common.cuh" + +#define CUDA_SOFTCAP_BLOCK_SIZE 256 + +void ggml_cuda_op_softcap(ggml_backend_cuda_context & ctx, ggml_tensor * dst, ggml_tensor * src); diff --git a/ggml/src/ggml-cuda/softmax.cu b/ggml/src/ggml-cuda/softmax.cu index 14543e978c..eeacde0bdb 100644 --- a/ggml/src/ggml-cuda/softmax.cu +++ b/ggml/src/ggml-cuda/softmax.cu @@ -45,7 +45,7 @@ struct soft_max_params { #endif // __clang__ template static __global__ void soft_max_f32( - const float * x, const T * mask, float * dst, const soft_max_params p) { + const float * x, const T * mask, const float * sinks, float * dst, const soft_max_params p) { const int ncols = ncols_template == 0 ? p.ncols : ncols_template; const int tid = threadIdx.x; @@ -77,7 +77,7 @@ static __global__ void soft_max_f32( // shared memory buffer to cache values between iterations: float * vals = use_shared ? buf_iw + WARP_SIZE : dst; - float max_val = -INFINITY; + float max_val = sinks ? sinks[i02] : -INFINITY; #pragma unroll for (int col0 = 0; col0 < ncols; col0 += block_size) { @@ -143,6 +143,10 @@ static __global__ void soft_max_f32( tmp = warp_reduce_sum(tmp); } + if (sinks) { + tmp += expf(sinks[i02] - max_val); + } + const float inv_sum = 1.0f / tmp; #pragma unroll @@ -183,7 +187,7 @@ static __global__ void soft_max_back_f32( } template -static void launch_soft_max_kernels(const float * x, const T * mask, float * dst, +static void launch_soft_max_kernels(const float * x, const T * mask, const float * sinks, float * dst, const soft_max_params & p, cudaStream_t stream, dim3 block_dims, dim3 block_nums, size_t nbytes_shared) { const int id = ggml_cuda_get_device(); @@ -196,7 +200,7 @@ static void launch_soft_max_kernels(const float * x, const T * mask, float * dst if (p.ncols == ncols) { CUDA_SET_SHARED_MEMORY_LIMIT((soft_max_f32), smpbo); soft_max_f32<<>> - (x, mask, dst, p); + (x, mask, sinks, dst, p); return true; } return false; @@ -209,12 +213,12 @@ static void launch_soft_max_kernels(const float * x, const T * mask, float * dst //default case CUDA_SET_SHARED_MEMORY_LIMIT((soft_max_f32), smpbo); - soft_max_f32<<>>(x, mask, dst, p); + soft_max_f32<<>>(x, mask, sinks, dst, p); } template -static void soft_max_f32_cuda(const float * x, const T * mask, float * dst, const soft_max_params & params, cudaStream_t stream) { +static void soft_max_f32_cuda(const float * x, const T * mask, const float * sinks, float * dst, const soft_max_params & params, cudaStream_t stream) { int nth = WARP_SIZE; const int64_t ncols_x = params.ncols; @@ -230,10 +234,10 @@ static void soft_max_f32_cuda(const float * x, const T * mask, float * dst, cons if (nbytes_shared <= smpbo) { - launch_soft_max_kernels<32, 64, 128, 256, 512, 1024, 2048, 4096>(x, mask, dst, params, stream, block_dims, block_nums, nbytes_shared); + launch_soft_max_kernels<32, 64, 128, 256, 512, 1024, 2048, 4096>(x, mask, sinks, dst, params, stream, block_dims, block_nums, nbytes_shared); } else { const size_t nbytes_shared_low = WARP_SIZE*sizeof(float); - soft_max_f32<<>>(x, mask, dst, params); + soft_max_f32<<>>(x, mask, sinks, dst, params); } } @@ -249,9 +253,11 @@ static void soft_max_back_f32_cuda( void ggml_cuda_op_soft_max(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; const ggml_tensor * src1 = dst->src[1]; + const ggml_tensor * src2 = dst->src[2]; const float * src0_d = (const float *) src0->data; const void * src1_d = src1 ? (const void *) src1->data : nullptr; + const void * src2_d = src2 ? (const void *) src2->data : nullptr; float * dst_d = (float *) dst->data; cudaStream_t stream = ctx.stream(); @@ -309,9 +315,9 @@ void ggml_cuda_op_soft_max(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { params.m1 = m1; if (use_f16) { - soft_max_f32_cuda(src0_d, (const half *) src1_d, dst_d, params, stream); + soft_max_f32_cuda(src0_d, (const half *) src1_d, (const float *) src2_d, dst_d, params, stream); } else { - soft_max_f32_cuda(src0_d, (const float *) src1_d, dst_d, params, stream); + soft_max_f32_cuda(src0_d, (const float *) src1_d, (const float *) src2_d, dst_d, params, stream); } } diff --git a/ggml/src/ggml-cuda/ssm-scan.cu b/ggml/src/ggml-cuda/ssm-scan.cu index c9184398b4..dc9a7d58d0 100644 --- a/ggml/src/ggml-cuda/ssm-scan.cu +++ b/ggml/src/ggml-cuda/ssm-scan.cu @@ -1,87 +1,117 @@ +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 +#define USE_CUB +#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 + +#ifdef USE_CUB +#include +using namespace cub; +#endif // USE_CUB + #include "ssm-scan.cuh" -template -__global__ void __launch_bounds__(splitD, 2) - ssm_scan_f32(const float * __restrict__ src0, const float * __restrict__ src1, const float * __restrict__ src2, - const float * __restrict__ src3, const float * __restrict__ src4, const float * __restrict__ src5, +// We would like to keep pragma unroll for cases where L_template is not 0, +// so we suppress the clang transformation warning. +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpass-failed" +#endif // __clang__ +template +__global__ void __launch_bounds__(splitD, 1) + ssm_scan_f32(const float *__restrict__ src0, const float *__restrict__ src1, const float *__restrict__ src2, + const float *__restrict__ src3, const float *__restrict__ src4, const float *__restrict__ src5, const int32_t * __restrict__ src6, float * __restrict__ dst, const int src0_nb2, const int src0_nb3, const int src1_nb2, const int src1_nb3, const int src2_nb1, const int src2_nb2, const int src3_nb1, const int src4_nb2, const int src4_nb3, const int src5_nb2, const int src5_nb3, - const int64_t s_off, const int64_t d_inner, const int64_t L) { + const int64_t s_off, const int64_t d_inner, const int64_t L_param) +{ + const size_t L = L_template == 0 ? L_param : L_template; + const float *s0_block = (const float *)((const char *)src0 + src6[blockIdx.x] * src0_nb3 + blockIdx.y * splitD * src0_nb2); + const float *x_block = (const float *)((const char *)src1 + (blockIdx.x * src1_nb3) + blockIdx.y * splitD * sizeof(float)); + const float *dt_block = (const float *)((const char *)src2 + (blockIdx.x * src2_nb2) + blockIdx.y * splitD * sizeof(float)); + const float *A_block = (const float *)((const char *)src3 + blockIdx.y * splitD * src3_nb1); + const float *B_block = (const float *)((const char *)src4 + (blockIdx.x * src4_nb3)); + const float *C_block = (const float *)((const char *)src5 + (blockIdx.x * src5_nb3)); + float *y_block = (float *)((char *)dst + (blockIdx.x * d_inner * L * sizeof(float)) + blockIdx.y * splitD * sizeof(float)); + float *s_block = (float *)((char *)dst + s_off + blockIdx.x * src0_nb3 + blockIdx.y * splitD * src0_nb2); - constexpr int warp_size = ggml_cuda_get_physical_warp_size(); - const int bidx = blockIdx.x; // split along B (sequences) - const int bidy = blockIdx.y; // split along D (d_inner) - const int tid = threadIdx.x; - const int wid = tid / 32; - const int wtid = tid % 32; - - extern __shared__ float smem[]; - const int stride_sA = N + 1; - const int stride_ss0 = N + 1; - float * smem_A = smem; - float * smem_s0 = smem_A + splitD * stride_sA; - - const float * s0_block = (const float *) ((const char *) src0 + src6[bidx] * src0_nb3 + bidy * splitD * src0_nb2); - const float * x_block = (const float *) ((const char *) src1 + (bidx * src1_nb3) + bidy * splitD * sizeof(float)); - const float * dt_block = (const float *) ((const char *) src2 + (bidx * src2_nb2) + bidy * splitD * sizeof(float)); - const float * A_block = (const float *) ((const char *) src3 + bidy * splitD * src3_nb1); - const float * B_block = (const float *) ((const char *) src4 + (bidx * src4_nb3)); - const float * C_block = (const float *) ((const char *) src5 + (bidx * src5_nb3)); - float * y_block = (float *) ((char *) dst + (bidx * d_inner * L * sizeof(float)) + bidy * splitD * sizeof(float)); - float * s_block = (float *) ((char *) dst + s_off + bidx * src0_nb3 + bidy * splitD * src0_nb2); - - const int stride_s0 = src0_nb2 / sizeof(float); - const int stride_x = src1_nb2 / sizeof(float); + const int stride_x = src1_nb2 / sizeof(float); const int stride_dt = src2_nb1 / sizeof(float); - const int stride_A = src3_nb1 / sizeof(float); - const int stride_B = src4_nb2 / sizeof(float); - const int stride_C = src5_nb2 / sizeof(float); - const int stride_s = stride_s0; - const int stride_y = d_inner; + const int stride_B = src4_nb2 / sizeof(float); + const int stride_C = src5_nb2 / sizeof(float); + const int stride_y = d_inner; - // can N not be 16? for example 32? - if (N == 16) { + float regA[N]; + float regs0[N]; + + __shared__ float smemB[N]; + __shared__ float smemC[N]; + +#ifdef USE_CUB + using BlockLoad = cub::BlockLoad; + using BlockStore = cub::BlockStore; + + union CubTempStorage { + typename BlockLoad::TempStorage load_temp; + typename BlockStore::TempStorage store_temp; + }; + __shared__ CubTempStorage cub_temp_storage; + + BlockLoad(cub_temp_storage.load_temp).Load(A_block, regA); + BlockLoad(cub_temp_storage.load_temp).Load(s0_block, regs0); +#else + const int stride_s0 = src0_nb2 / sizeof(float); + const int stride_A = src3_nb1 / sizeof(float); #pragma unroll - for (size_t i = 0; i < splitD / 4; i += 2) { - float value = A_block[(wid * warp_size + i) * stride_A + wtid]; - // todo: bank conflict - // I am always confused with how to use the swizzling method to solve - // bank conflit. Hoping somebody can tell me. - smem_A[(wid * warp_size + i) * stride_sA + wtid + ((wtid / 16) > 0 ? 1 : 0)] = value; - } -#pragma unroll - for (size_t i = 0; i < splitD / 4; i += 2) { - float value = s0_block[(wid * warp_size + i) * stride_s0 + wtid]; - smem_s0[(wid * warp_size + i) * stride_ss0 + wtid + ((wtid / 16) > 0 ? 1 : 0)] = value; - } + for (size_t n = 0; n < N; ++n) + { + regA[n] = A_block[threadIdx.x * stride_A + n]; + regs0[n] = s0_block[threadIdx.x * stride_s0 + n]; } +#endif - __syncthreads(); - - for (int64_t i = 0; i < L; i++) { - float dt_soft_plus = dt_block[i * stride_dt + tid]; - if (dt_soft_plus <= 20.0f) { - dt_soft_plus = log1pf(exp(dt_soft_plus)); - } - float x_dt = x_block[i * stride_x + tid] * dt_soft_plus; - float sumf = 0.0f; #pragma unroll - for (size_t j = 0; j < N; j++) { - float state = (smem_s0[tid * stride_ss0 + j] * expf(dt_soft_plus * smem_A[tid * stride_sA + j])) + - (B_block[i * stride_B + j] * x_dt); - sumf += state * C_block[i * stride_C + j]; - if (i == L - 1) { - s_block[tid * stride_s + j] = state; - } else { - smem_s0[tid * stride_ss0 + j] = state; - } + for (size_t i = 0; i < L; i++) + { + if (threadIdx.x < N) + { + smemB[threadIdx.x] = B_block[i * stride_B + threadIdx.x]; + smemC[threadIdx.x] = C_block[i * stride_C + threadIdx.x]; } __syncthreads(); - y_block[i * stride_y + tid] = sumf; + + float dt_soft_plus = dt_block[i * stride_dt + threadIdx.x]; + if (dt_soft_plus <= 20.0f) + { + dt_soft_plus = log1pf(expf(dt_soft_plus)); + } + float x_dt = x_block[i * stride_x + threadIdx.x] * dt_soft_plus; + + float sumf = 0.0f; +#pragma unroll + for (size_t n = 0; n < N; n++) + { + float state = regs0[n] * expf(dt_soft_plus * regA[n]) + smemB[n] * x_dt; + sumf += state * smemC[n]; + regs0[n] = state; + } + y_block[i * stride_y + threadIdx.x] = sumf; } + +#ifdef USE_CUB + BlockStore(cub_temp_storage.store_temp).Store(s_block, regs0); +#else + const int stride_s = stride_s0; +#pragma unroll + for (size_t n = 0; n < N; ++n) + { + s_block[threadIdx.x * stride_s + n] = regs0[n]; + } +#endif } +#ifdef __clang__ +#pragma clang diagnostic pop +#endif // __clang__ // assumes as many threads as d_state template @@ -201,11 +231,11 @@ static void ssm_scan_f32_cuda(const float * src0, const float * src1, const floa const int src5_nb3, const int64_t s_off, const int64_t d_state, const int64_t head_dim, const int64_t n_head, const int64_t n_group, const int64_t n_tok, const int64_t n_seq, cudaStream_t stream) { + const int threads = 128; // NOTE: if you change conditions here, be sure to update the corresponding supports_op condition! if (src3_nb1 == sizeof(float)) { // Mamba-2 if (d_state == 128) { - const int threads = 128; GGML_ASSERT(d_state % threads == 0); // NOTE: can be any power of two between 4 and 64 const int splitH = 16; @@ -229,7 +259,6 @@ static void ssm_scan_f32_cuda(const float * src0, const float * src1, const floa GGML_ABORT("doesn't support d_state!=(128 or 256)."); } } else { - const int threads = 128; // Mamba-1 GGML_ASSERT(n_head % threads == 0); GGML_ASSERT(head_dim == 1); @@ -237,10 +266,63 @@ static void ssm_scan_f32_cuda(const float * src0, const float * src1, const floa const dim3 blocks(n_seq, (n_head + threads - 1) / threads, 1); const int smem_size = (threads * (d_state + 1) * 2) * sizeof(float); if (d_state == 16) { - ssm_scan_f32<128, 16><<>>( - src0, src1, src2, src3, src4, src5, src6, dst, + switch (n_tok) + { + case 1: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 2: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 3: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 4: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 5: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 6: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 7: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 8: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + default: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + } } else { GGML_ABORT("doesn't support d_state!=16."); } diff --git a/ggml/src/ggml-cuda/sum.cu b/ggml/src/ggml-cuda/sum.cu index eb3d7cdba9..c56257b440 100644 --- a/ggml/src/ggml-cuda/sum.cu +++ b/ggml/src/ggml-cuda/sum.cu @@ -1,19 +1,15 @@ -#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 -#define USE_CUB -#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 +#include "sum.cuh" +#include "sumrows.cuh" -#ifdef USE_CUB +#ifdef GGML_CUDA_USE_CUB #include using namespace cub; -#endif // USE_CUB - -#include "sumrows.cuh" -#include "sum.cuh" +#endif // GGML_CUDA_USE_CUB #include void sum_f32_cuda(ggml_cuda_pool & pool, const float * x, float * dst, const int64_t ne, cudaStream_t stream) { -#ifdef USE_CUB +#ifdef GGML_CUDA_USE_CUB size_t tmp_size = 0; DeviceReduce::Sum(nullptr, tmp_size, x, dst, ne, stream); ggml_cuda_pool_alloc tmp_alloc(pool, tmp_size); @@ -23,7 +19,7 @@ void sum_f32_cuda(ggml_cuda_pool & pool, const float * x, float * dst, const int // For AMD there is rocPRIM which could be used as a drop-in replacement via hipcub but this would require C++11 -> C++14. sum_rows_f32_cuda(x, dst, ne, 1, stream); GGML_UNUSED(pool); -#endif // USE_CUB +#endif // GGML_CUDA_USE_CUB } void ggml_cuda_op_sum(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { diff --git a/ggml/src/ggml-cuda/sumrows.cu b/ggml/src/ggml-cuda/sumrows.cu index 2eee08fa07..4025771aad 100644 --- a/ggml/src/ggml-cuda/sumrows.cu +++ b/ggml/src/ggml-cuda/sumrows.cu @@ -1,9 +1,17 @@ +#include "reduce_rows.cuh" #include "sumrows.cuh" void sum_rows_f32_cuda(const float * x, float * dst, const int ncols, const int nrows, cudaStream_t stream) { - const dim3 block_dims(WARP_SIZE, 1, 1); + const int id = ggml_cuda_get_device(); + const int nsm = ggml_cuda_info().devices[id].nsm; const dim3 block_nums(nrows, 1, 1); - reduce_rows_f32<<>>(x, dst, ncols); + if ((nrows / nsm) < 2) { + const dim3 block_dims(512, 1, 1); + reduce_rows_f32<<>>(x, dst, ncols); + } else { + const dim3 block_dims(ncols < 1024 ? 32 : 128, 1, 1); + reduce_rows_f32<<>>(x, dst, ncols); + } } void ggml_cuda_op_sum_rows(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { @@ -19,8 +27,17 @@ void ggml_cuda_op_sum_rows(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const int64_t ncols = src0->ne[0]; const int64_t nrows = ggml_nrows(src0); - const dim3 block_dims(WARP_SIZE, 1, 1); const dim3 block_nums(nrows, 1, 1); - reduce_rows_f32<<>>(src0_d, dst_d, ncols); + const int id = ggml_cuda_get_device(); + const int nsm = ggml_cuda_info().devices[id].nsm; + if ((nrows / nsm) < 2) { + // Increase num threads to 512 for small nrows to better hide the latency + const dim3 block_dims(512, 1, 1); + reduce_rows_f32<<>>(src0_d, dst_d, ncols); + } else { + // Enough active SMs to hide latency, use smaller blocks to allow better scheduling + const dim3 block_dims(ncols < 1024 ? 32 : 128, 1, 1); + reduce_rows_f32<<>>(src0_d, dst_d, ncols); + } } diff --git a/ggml/src/ggml-cuda/template-instances/mmq-instance-mxfp4.cu b/ggml/src/ggml-cuda/template-instances/mmq-instance-mxfp4.cu new file mode 100644 index 0000000000..c14624c52c --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/mmq-instance-mxfp4.cu @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmq.cuh" + +DECL_MMQ_CASE(GGML_TYPE_MXFP4); diff --git a/ggml/src/ggml-cuda/unary.cu b/ggml/src/ggml-cuda/unary.cu index 91c830c4da..5aff8a876a 100644 --- a/ggml/src/ggml-cuda/unary.cu +++ b/ggml/src/ggml-cuda/unary.cu @@ -300,6 +300,81 @@ void ggml_cuda_op_geglu_quick(ggml_backend_cuda_context & ctx, ggml_tensor * dst ggml_cuda_op_unary_gated(ctx, dst); } +// swiglu_oai + +template +static __global__ void swiglu_oai_kernel(const T * x, const T * g, T * dst, const int64_t k, const int64_t n, const int64_t o0, const int64_t o1, float alpha, float limit) { + const int64_t i = int64_t(blockDim.x)*blockIdx.x + threadIdx.x; + + if (i >= k) { + return; + } + + // perform base op and multiply with gate (either offset in same tensor or a separate one) + const int64_t j0 = (i / n) * o0 + (i % n); + const int64_t j1 = o0 == o1 ? j0 : (i / n) * o1 + (i % n); + + float xi = x[j0]; + float gi = g[j1]; + xi = fminf(xi, limit); + gi = fmaxf(fminf(gi, limit), -limit); + + float out_glu = xi / (1.0f + expf(-xi * alpha)); + out_glu = out_glu * (1.0f + gi); + + dst[i] = out_glu; +} + +template +static void swiglu_oai_cuda(const T * x, const T * g, T * dst, const int64_t k, const int64_t n, const int64_t o0, const int64_t o1, const float alpha, const float limit, cudaStream_t stream) { + const int64_t num_blocks = (k + CUDA_GLU_BLOCK_SIZE - 1) / CUDA_GLU_BLOCK_SIZE; + swiglu_oai_kernel<<>>(x, g, dst, k, n, o0, o1, alpha, limit); +} + +void ggml_cuda_op_swiglu_oai(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + void * src0_d = src0->data; + void * src1_d = src1 ? src1->data : src0->data; + const int64_t src0_o = src0->nb[1]; + const int64_t src1_o = src1 ? src1->nb[1] : src0->nb[1]; + void * dst_d = dst->data; + const int64_t nc = src1 ? src0->ne[0] : src0->ne[0] / 2; + cudaStream_t stream = ctx.stream(); + + GGML_ASSERT(ggml_is_contiguous_1(src0)); + GGML_ASSERT(src0->nb[0] == ggml_element_size(src0)); + GGML_ASSERT(ggml_is_contiguous(dst)); + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT( dst->type == GGML_TYPE_F32); + GGML_ASSERT(src0->type == dst->type); + GGML_ASSERT(dst->ne[0] == nc); + GGML_ASSERT(ggml_nrows(dst) == ggml_nrows(src0)); + + if (src1) { + GGML_ASSERT(ggml_is_contiguous_1(src1)); + GGML_ASSERT(src1->nb[0] == ggml_element_size(src1)); + GGML_ASSERT(src1->ne[0] == nc); + GGML_ASSERT(src0->type == src1->type); + } + + //const int32_t swapped = ((const int32_t *) dst->op_params)[1]; + const int32_t swapped = ggml_get_op_params_i32(dst, 1); + const float alpha = ggml_get_op_params_f32(dst, 2); + const float limit = ggml_get_op_params_f32(dst, 3); + + float * src0_p = (float *) src0_d; + float * src1_p = (float *) src1_d; + + if (!src1) { + src0_p += swapped ? nc : 0; + src1_p += swapped ? 0 : nc; + } + + swiglu_oai_cuda(src0_p, src1_p, (float *)dst_d, ggml_nelements(dst), nc, src0_o / sizeof(float), src1_o / sizeof(float), alpha, limit, stream); +} + /* silu_back */ static __device__ __forceinline__ float op_silu_back(float grad, float x) { diff --git a/ggml/src/ggml-cuda/unary.cuh b/ggml/src/ggml-cuda/unary.cuh index cb14d16f8f..da3caf1d89 100644 --- a/ggml/src/ggml-cuda/unary.cuh +++ b/ggml/src/ggml-cuda/unary.cuh @@ -67,6 +67,8 @@ void ggml_cuda_op_geglu(ggml_backend_cuda_context & ctx, ggml_tensor * dst); void ggml_cuda_op_swiglu(ggml_backend_cuda_context & ctx, ggml_tensor * dst); +void ggml_cuda_op_swiglu_oai(ggml_backend_cuda_context & ctx, ggml_tensor * dst); + void ggml_cuda_op_geglu_erf(ggml_backend_cuda_context & ctx, ggml_tensor * dst); void ggml_cuda_op_geglu_quick(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff --git a/ggml/src/ggml-cuda/vecdotq.cuh b/ggml/src/ggml-cuda/vecdotq.cuh index ba195e1d10..d8f9aa5ba6 100644 --- a/ggml/src/ggml-cuda/vecdotq.cuh +++ b/ggml/src/ggml-cuda/vecdotq.cuh @@ -1,8 +1,20 @@ #pragma once #include "common.cuh" + #include +static __device__ __forceinline__ int get_int_b1(const void * x, const int & i32) { + const uint8_t * x8 = (const uint8_t *) x; + + int x32 = x8[4*i32 + 0] << 0; + x32 |= x8[4*i32 + 1] << 8; + x32 |= x8[4*i32 + 2] << 16; + x32 |= x8[4*i32 + 3] << 24; + + return x32; +} + static __device__ __forceinline__ int get_int_b2(const void * x, const int & i32) { const uint16_t * x16 = (const uint16_t *) x; // assume at least 2 byte alignment @@ -16,6 +28,20 @@ static __device__ __forceinline__ int get_int_b4(const void * x, const int & i32 return ((const int *) x)[i32]; // assume at least 4 byte alignment } +static __device__ __forceinline__ int2 get_int_from_table_16(const int & q4, const int8_t * table) { + const int q0_32 = (q4 >> 0) & 0x0F0F0F0F; + const int8_t * q0_8 = (const int8_t *) &q0_32; + const char4 val0_8 = make_char4( + table[q0_8[0]], table[q0_8[1]], table[q0_8[2]], table[q0_8[3]]); + + const int q1_32 = (q4 >> 4) & 0x0F0F0F0F; + const int8_t * q1_8 = (const int8_t *) &q1_32; + const char4 val1_8 = make_char4( + table[q1_8[0]], table[q1_8[1]], table[q1_8[2]], table[q1_8[3]]); + + return make_int2(*((const int *) &val0_8), *((const int *) &val1_8)); +} + // VDR = vec dot ratio, how many contiguous integers each thread processes when the vec dot kernel is called // MMVQ = mul_mat_vec_q, MMQ = mul_mat_q @@ -211,6 +237,30 @@ template static __device__ __forceinline__ float vec_dot_q8_0_16_q8_1_ return d8_1*sumf; } +#define VDR_MXFP4_Q8_1_MMVQ 2 +#define VDR_MXFP4_Q8_1_MMQ 4 + +static __device__ __forceinline__ float vec_dot_mxfp4_q8_1( + const void * __restrict__ vbq, const block_q8_1 * __restrict__ bq8_1, const int & kbx, const int & iqs) { + + const block_mxfp4 * bq4 = (const block_mxfp4 *) vbq + kbx; + + const int * q8 = (const int *) bq8_1->qs + iqs; + + int sumi = 0; +#pragma unroll + for (int l = 0; l < VDR_MXFP4_Q8_1_MMVQ; ++l) { + const int aux_q4 = get_int_b1(bq4->qs, iqs + l); + const int2 v = get_int_from_table_16(aux_q4, kvalues_mxfp4); + + sumi = ggml_cuda_dp4a(v.x, q8[l + 0], sumi); + sumi = ggml_cuda_dp4a(v.y, q8[l + 4], sumi); + } + + const float d = ggml_cuda_e8m0_to_fp32(bq4->e) * 0.5f * __low2float(bq8_1->ds); + return d * sumi; +} + #define VDR_Q2_K_Q8_1_MMVQ 1 #define VDR_Q2_K_Q8_1_MMQ 4 @@ -1068,20 +1118,6 @@ static __device__ __forceinline__ float vec_dot_iq1_m_q8_1( return d * ((sumi[0] + sumf[0]) * sc0 + (sumi[1] + sumf[1]) * sc1); } -static __device__ __forceinline__ int2 get_int_from_table_16(const int & q4) { - const int q0_32 = (q4 >> 0) & 0x0F0F0F0F; - const int8_t * q0_8 = (const int8_t *) &q0_32; - const char4 val0_8 = make_char4( - kvalues_iq4nl[q0_8[0]], kvalues_iq4nl[q0_8[1]], kvalues_iq4nl[q0_8[2]], kvalues_iq4nl[q0_8[3]]); - - const int q1_32 = (q4 >> 4) & 0x0F0F0F0F; - const int8_t * q1_8 = (const int8_t *) &q1_32; - const char4 val1_8 = make_char4( - kvalues_iq4nl[q1_8[0]], kvalues_iq4nl[q1_8[1]], kvalues_iq4nl[q1_8[2]], kvalues_iq4nl[q1_8[3]]); - - return make_int2(*((const int *) &val0_8), *((const int *) &val1_8)); -} - #define VDR_IQ4_NL_Q8_1_MMVQ 2 #define VDR_IQ4_NL_Q8_1_MMQ 4 @@ -1096,7 +1132,7 @@ static __device__ __forceinline__ float vec_dot_iq4_nl_q8_1( #pragma unroll for (int l = 0; l < VDR_Q4_0_Q8_1_MMVQ; ++l) { const int aux_q4 = get_int_b2(bq4->qs, iqs + l); - const int2 v = get_int_from_table_16(aux_q4); + const int2 v = get_int_from_table_16(aux_q4, kvalues_iq4nl); sumi = ggml_cuda_dp4a(v.x, q8[l + 0], sumi); sumi = ggml_cuda_dp4a(v.y, q8[l + 4], sumi); @@ -1118,7 +1154,7 @@ static __device__ __forceinline__ float vec_dot_iq4_xs_q8_1( #pragma unroll for (int j = 0; j < 4; ++j) { const int aux_q4 = get_int_b4(bq4->qs, iqs + j); - const int2 v = get_int_from_table_16(aux_q4); + const int2 v = get_int_from_table_16(aux_q4, kvalues_iq4nl); const int u0 = get_int_b4(bq8_1[iqs/4].qs, j + 0); const int u1 = get_int_b4(bq8_1[iqs/4].qs, j + 4); diff --git a/ggml/src/ggml-cuda/vendors/cuda.h b/ggml/src/ggml-cuda/vendors/cuda.h index 1746b07320..3b3086778e 100644 --- a/ggml/src/ggml-cuda/vendors/cuda.h +++ b/ggml/src/ggml-cuda/vendors/cuda.h @@ -6,6 +6,10 @@ #include #include +#if CUDART_VERSION >= 12050 +#include +#endif // CUDART_VERSION >= 12050 + #if CUDART_VERSION < 11020 #define CU_DEVICE_ATTRIBUTE_VIRTUAL_MEMORY_MANAGEMENT_SUPPORTED CU_DEVICE_ATTRIBUTE_VIRTUAL_ADDRESS_MANAGEMENT_SUPPORTED #define CUBLAS_TF32_TENSOR_OP_MATH CUBLAS_TENSOR_OP_MATH diff --git a/ggml/src/ggml-cuda/vendors/hip.h b/ggml/src/ggml-cuda/vendors/hip.h index 184d445f5c..6e9c67aca0 100644 --- a/ggml/src/ggml-cuda/vendors/hip.h +++ b/ggml/src/ggml-cuda/vendors/hip.h @@ -1,14 +1,10 @@ #pragma once -#define HIP_ENABLE_WARP_SYNC_BUILTINS 1 +#define HIP_DISABLE_WARP_SYNC_BUILTINS 1 #include #include #include -#include -#ifdef __HIP_PLATFORM_AMD__ -// for rocblas_initialize() -#include "rocblas/rocblas.h" -#endif // __HIP_PLATFORM_AMD__ +#include #define CUBLAS_GEMM_DEFAULT HIPBLAS_GEMM_DEFAULT #define CUBLAS_GEMM_DEFAULT_TENSOR_OP HIPBLAS_GEMM_DEFAULT @@ -139,7 +135,7 @@ #define CUBLAS_STATUS_INTERNAL_ERROR HIPBLAS_STATUS_INTERNAL_ERROR #define CUBLAS_STATUS_NOT_SUPPORTED HIPBLAS_STATUS_NOT_SUPPORTED -#if defined(__HIP_PLATFORM_AMD__) && HIP_VERSION >= 70000000 +#if HIP_VERSION >= 60500000 #define CUBLAS_COMPUTE_16F HIPBLAS_COMPUTE_16F #define CUBLAS_COMPUTE_32F HIPBLAS_COMPUTE_32F #define CUBLAS_COMPUTE_32F_FAST_16F HIPBLAS_COMPUTE_32F_FAST_16F @@ -151,7 +147,11 @@ #define CUBLAS_COMPUTE_32F_FAST_16F HIPBLAS_R_32F #define cublasComputeType_t hipblasDatatype_t #define cudaDataType_t hipblasDatatype_t -#endif +#endif // HIP_VERSION >= 6050000 + +#if !defined(__HIP_PLATFORM_AMD__) +#error "The HIP backend supports only AMD targets" +#endif // !defined(__HIP_PLATFORM_AMD__) #define __CUDA_ARCH__ 1300 @@ -160,15 +160,26 @@ #endif #if defined(__gfx908__) || defined(__gfx90a__) || defined(__gfx942__) -#define CDNA +#define CDNA // For the entire family +#endif + +#if defined(__gfx942__) +#define CDNA3 +#endif + +#if defined(__gfx90a__) +#define CDNA2 +#endif + +#if defined(__gfx908__) +#define CDNA1 #endif #if defined(__GFX12__) #define RDNA4 #endif -#if defined(__gfx1100__) || defined(__gfx1101__) || defined(__gfx1102__) || defined(__gfx1103__) || \ - defined(__gfx1150__) || defined(__gfx1151__) +#if defined(__GFX11__) #define RDNA3 #endif @@ -185,7 +196,8 @@ #define __has_builtin(x) 0 #endif -typedef hip_bfloat16 nv_bfloat16; +typedef __hip_bfloat16 nv_bfloat16; +typedef __hip_bfloat162 nv_bfloat162; typedef int8_t int8x4_t __attribute__((ext_vector_type(4))); typedef uint8_t uint8x4_t __attribute__((ext_vector_type(4))); @@ -236,17 +248,3 @@ static __device__ __forceinline__ unsigned int __vcmpne4(unsigned int a, unsigne } return c; } - -#if defined(__HIP_PLATFORM_AMD__) && HIP_VERSION < 50600000 -// __shfl_xor() for half2 was added in ROCm 5.6 -static __device__ __forceinline__ half2 __shfl_xor(half2 var, int laneMask, int width) { - typedef union half2_b32 { - half2 val; - int b32; - } half2_b32_t; - half2_b32_t tmp; - tmp.val = var; - tmp.b32 = __shfl_xor(tmp.b32, laneMask, width); - return tmp.val; -} -#endif // defined(__HIP_PLATFORM_AMD__) && HIP_VERSION < 50600000 diff --git a/ggml/src/ggml-cuda/vendors/musa.h b/ggml/src/ggml-cuda/vendors/musa.h index 937779a90a..8c55a2e4e5 100644 --- a/ggml/src/ggml-cuda/vendors/musa.h +++ b/ggml/src/ggml-cuda/vendors/musa.h @@ -13,7 +13,7 @@ #define CUBLAS_OP_N MUBLAS_OP_N #define CUBLAS_OP_T MUBLAS_OP_T #define CUBLAS_STATUS_SUCCESS MUBLAS_STATUS_SUCCESS -#define CUBLAS_TF32_TENSOR_OP_MATH MUBLAS_MATH_MODE_DEFAULT +#define CUBLAS_TF32_TENSOR_OP_MATH MUBLAS_TENSOR_OP_MATH #define CUDA_R_16F MUSA_R_16F #define CUDA_R_16BF MUSA_R_16BF #define CUDA_R_32F MUSA_R_32F @@ -29,7 +29,7 @@ #define cublasSgemm mublasSgemm #define cublasStatus_t mublasStatus_t #define cublasOperation_t mublasOperation_t -#define cublasGetStatusString mublasStatus_to_string +#define cublasGetStatusString mublasGetStatusString #define cudaDataType_t musaDataType_t #define cudaDeviceCanAccessPeer musaDeviceCanAccessPeer #define cudaDeviceDisablePeerAccess musaDeviceDisablePeerAccess @@ -137,4 +137,5 @@ #define cudaStreamEndCapture musaStreamEndCapture #define cudaOccupancyMaxActiveBlocksPerMultiprocessor musaOccupancyMaxActiveBlocksPerMultiprocessor -typedef mt_bfloat16 nv_bfloat16; +typedef __mt_bfloat16 nv_bfloat16; +typedef __mt_bfloat162 nv_bfloat162; diff --git a/ggml/src/ggml-hip/CMakeLists.txt b/ggml/src/ggml-hip/CMakeLists.txt index e29df98560..d327b90cce 100644 --- a/ggml/src/ggml-hip/CMakeLists.txt +++ b/ggml/src/ggml-hip/CMakeLists.txt @@ -46,8 +46,8 @@ if (GGML_HIP_ROCWMMA_FATTN) endif() endif() -if (${hip_VERSION} VERSION_LESS 5.5) - message(FATAL_ERROR "At least ROCM/HIP V5.5 is required") +if (${hip_VERSION} VERSION_LESS 6.1) + message(FATAL_ERROR "At least ROCM/HIP V6.1 is required") endif() message(STATUS "HIP and hipBLAS found") @@ -113,10 +113,18 @@ if (GGML_HIP_ROCWMMA_FATTN) add_compile_definitions(GGML_HIP_ROCWMMA_FATTN) endif() +if (NOT GGML_HIP_MMQ_MFMA) + add_compile_definitions(GGML_HIP_NO_MMQ_MFMA) +endif() + if (GGML_HIP_FORCE_ROCWMMA_FATTN_GFX12 OR ${hip_VERSION} VERSION_GREATER_EQUAL 7.0) add_compile_definitions(GGML_HIP_ROCWMMA_FATTN_GFX12) endif() +if (GGML_HIP_EXPORT_METRICS) + set(CMAKE_HIP_FLAGS "${CMAKE_HIP_FLAGS} -Rpass-analysis=kernel-resource-usage --save-temps") +endif() + if (NOT GGML_CUDA_FA) add_compile_definitions(GGML_CUDA_NO_FA) endif() diff --git a/ggml/src/ggml-impl.h b/ggml/src/ggml-impl.h index a2e30994c4..19a7adb2d1 100644 --- a/ggml/src/ggml-impl.h +++ b/ggml/src/ggml-impl.h @@ -410,6 +410,67 @@ static inline ggml_fp16_t ggml_compute_fp32_to_fp16(float f) { #define GGML_FP16_TO_FP32(x) GGML_COMPUTE_FP16_TO_FP32(x) #define GGML_FP32_TO_FP16(x) GGML_COMPUTE_FP32_TO_FP16(x) +static inline float ggml_e8m0_to_fp32(uint8_t x) { + uint32_t bits; // Stores the raw bit representation of the float + + // Handle special case for minimum exponent (denormalized float) + if (x == 0) { + // Bit pattern for 2^(-127): + // - Sign bit: 0 (positive) + // - Exponent: 0 (denormalized number) + // - Mantissa: 0x400000 (0.5 in fractional form) + // Value = 0.5 * 2^(-126) = 2^(-127) + bits = 0x00400000; + } + // note: disabled as we don't need to handle NaNs + //// Handle special case for NaN (all bits set) + //else if (x == 0xFF) { + // // Standard quiet NaN pattern: + // // - Sign bit: 0 + // // - Exponent: all 1s (0xFF) + // // - Mantissa: 0x400000 (quiet NaN flag) + // bits = 0x7FC00000; + //} + // Normalized values (most common case) + else { + // Construct normalized float by shifting exponent into position: + // - Exponent field: 8 bits (positions 30-23) + // - Mantissa: 0 (implicit leading 1) + // Value = 2^(x - 127) + bits = (uint32_t) x << 23; + } + + float result; // Final float value + // Safely reinterpret bit pattern as float without type-punning issues + memcpy(&result, &bits, sizeof(float)); + return result; +} + +// Equal to ggml_e8m0_to_fp32/2 +// Useful with MXFP4 quantization since the E0M2 values are doubled +static inline float ggml_e8m0_to_fp32_half(uint8_t x) { + uint32_t bits; + + // For x < 2: use precomputed denormal patterns + if (x < 2) { + // 0x00200000 = 2^(-128), 0x00400000 = 2^(-127) + bits = 0x00200000 << x; + } + // For x >= 2: normalized exponent adjustment + else { + // 0.5 * 2^(x-127) = 2^(x-128) = normalized with exponent (x-1) + bits = (uint32_t)(x - 1) << 23; + } + // Note: NaNs are not handled here + + float result; + memcpy(&result, &bits, sizeof(float)); + return result; +} + +#define GGML_E8M0_TO_FP32(x) ggml_e8m0_to_fp32(x) +#define GGML_E8M0_TO_FP32_HALF(x) ggml_e8m0_to_fp32_half(x) + /** * Converts brain16 to float32. * diff --git a/ggml/src/ggml-metal/ggml-metal-impl.h b/ggml/src/ggml-metal/ggml-metal-impl.h index b7b3fc49af..fc6526d6d5 100644 --- a/ggml/src/ggml-metal/ggml-metal-impl.h +++ b/ggml/src/ggml-metal/ggml-metal-impl.h @@ -23,6 +23,9 @@ #define N_R0_Q8_0 4 #define N_SG_Q8_0 2 +#define N_R0_MXFP4 2 +#define N_SG_MXFP4 2 + #define N_R0_Q2_K 4 #define N_SG_Q2_K 2 @@ -129,6 +132,15 @@ typedef struct { uint64_t o1[8]; } ggml_metal_kargs_bin; +typedef struct { + int64_t ne0; + int64_t ne1; + size_t nb01; + size_t nb02; + size_t nb11; + size_t nb21; +} ggml_metal_kargs_add_id; + typedef struct { int32_t ne00; int32_t ne01; @@ -444,6 +456,8 @@ typedef struct{ uint64_t nb1; int32_t i00; int32_t i10; + float alpha; + float limit; } ggml_metal_kargs_glu; typedef struct { @@ -528,6 +542,7 @@ typedef struct { int64_t n_group; int64_t n_seq_tokens; int64_t n_seqs; + int64_t s_off; uint64_t nb01; uint64_t nb02; uint64_t nb03; diff --git a/ggml/src/ggml-metal/ggml-metal.m b/ggml/src/ggml-metal/ggml-metal.m index dc391a0d4d..cb8eff4a77 100644 --- a/ggml/src/ggml-metal/ggml-metal.m +++ b/ggml/src/ggml-metal/ggml-metal.m @@ -195,6 +195,7 @@ enum ggml_metal_kernel_type { GGML_METAL_KERNEL_TYPE_MUL_ROW_C4, GGML_METAL_KERNEL_TYPE_DIV, GGML_METAL_KERNEL_TYPE_DIV_ROW_C4, + GGML_METAL_KERNEL_TYPE_ADD_ID, GGML_METAL_KERNEL_TYPE_REPEAT_F32, GGML_METAL_KERNEL_TYPE_REPEAT_F16, GGML_METAL_KERNEL_TYPE_REPEAT_I32, @@ -234,6 +235,7 @@ enum ggml_metal_kernel_type { GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_0, GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_1, GGML_METAL_KERNEL_TYPE_GET_ROWS_Q8_0, + GGML_METAL_KERNEL_TYPE_GET_ROWS_MXFP4, GGML_METAL_KERNEL_TYPE_GET_ROWS_Q2_K, GGML_METAL_KERNEL_TYPE_GET_ROWS_Q3_K, GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_K, @@ -286,6 +288,7 @@ enum ggml_metal_kernel_type { GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_0_F32, GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_1_F32, GGML_METAL_KERNEL_TYPE_MUL_MV_Q8_0_F32, + GGML_METAL_KERNEL_TYPE_MUL_MV_MXFP4_F32, GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_2, GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_3, GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_4, @@ -310,6 +313,10 @@ enum ggml_metal_kernel_type { GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_3, GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_4, GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_5, + GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_2, + GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_3, + GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_4, + GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_5, GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_2, GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_3, GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_4, @@ -351,6 +358,7 @@ enum ggml_metal_kernel_type { GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_0_F32, GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_1_F32, GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q8_0_F32, + GGML_METAL_KERNEL_TYPE_MUL_MV_ID_MXFP4_F32, GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q2_K_F32, GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q3_K_F32, GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q4_K_F32, @@ -373,6 +381,7 @@ enum ggml_metal_kernel_type { GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_0_F32, GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_1_F32, GGML_METAL_KERNEL_TYPE_MUL_MM_Q8_0_F32, + GGML_METAL_KERNEL_TYPE_MUL_MM_MXFP4_F32, GGML_METAL_KERNEL_TYPE_MUL_MM_Q2_K_F32, GGML_METAL_KERNEL_TYPE_MUL_MM_Q3_K_F32, GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_K_F32, @@ -397,6 +406,7 @@ enum ggml_metal_kernel_type { GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_0_F16, GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_1_F16, GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q8_0_F16, + GGML_METAL_KERNEL_TYPE_MUL_MM_ID_MXFP4_F16, GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q2_K_F16, GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q3_K_F16, GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_K_F16, @@ -579,6 +589,7 @@ enum ggml_metal_kernel_type { GGML_METAL_KERNEL_TYPE_REGLU, GGML_METAL_KERNEL_TYPE_GEGLU, GGML_METAL_KERNEL_TYPE_SWIGLU, + GGML_METAL_KERNEL_TYPE_SWIGLU_OAI, GGML_METAL_KERNEL_TYPE_GEGLU_ERF, GGML_METAL_KERNEL_TYPE_GEGLU_QUICK, GGML_METAL_KERNEL_TYPE_SUM_ROWS, @@ -1199,6 +1210,7 @@ static struct ggml_backend_metal_context * ggml_metal_init(ggml_backend_dev_t de GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_ROW_C4, mul_row_c4, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_DIV, div, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_DIV_ROW_C4, div_row_c4, true); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ADD_ID, add_id, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_REPEAT_F32, repeat_f32, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_REPEAT_F16, repeat_f16, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_REPEAT_I32, repeat_i32, true); @@ -1238,6 +1250,7 @@ static struct ggml_backend_metal_context * ggml_metal_init(ggml_backend_dev_t de GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_0, get_rows_q5_0, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_1, get_rows_q5_1, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q8_0, get_rows_q8_0, true); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_MXFP4, get_rows_mxfp4, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q2_K, get_rows_q2_K, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q3_K, get_rows_q3_K, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_K, get_rows_q4_K, true); @@ -1290,6 +1303,7 @@ static struct ggml_backend_metal_context * ggml_metal_init(ggml_backend_dev_t de GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_0_F32, mul_mv_q5_0_f32, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_1_F32, mul_mv_q5_1_f32, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q8_0_F32, mul_mv_q8_0_f32, has_simdgroup_reduction); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_MXFP4_F32, mul_mv_mxfp4_f32, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_2, mul_mv_ext_f16_f32_r1_2, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_3, mul_mv_ext_f16_f32_r1_3, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_4, mul_mv_ext_f16_f32_r1_4, has_simdgroup_reduction); @@ -1314,6 +1328,10 @@ static struct ggml_backend_metal_context * ggml_metal_init(ggml_backend_dev_t de GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_3, mul_mv_ext_q8_0_f32_r1_3, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_4, mul_mv_ext_q8_0_f32_r1_4, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_5, mul_mv_ext_q8_0_f32_r1_5, has_simdgroup_reduction); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_2, mul_mv_ext_mxfp4_f32_r1_2, has_simdgroup_reduction); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_3, mul_mv_ext_mxfp4_f32_r1_3, has_simdgroup_reduction); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_4, mul_mv_ext_mxfp4_f32_r1_4, has_simdgroup_reduction); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_5, mul_mv_ext_mxfp4_f32_r1_5, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_2, mul_mv_ext_q4_K_f32_r1_2, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_3, mul_mv_ext_q4_K_f32_r1_3, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_4, mul_mv_ext_q4_K_f32_r1_4, has_simdgroup_reduction); @@ -1355,6 +1373,7 @@ static struct ggml_backend_metal_context * ggml_metal_init(ggml_backend_dev_t de GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_0_F32, mul_mv_id_q5_0_f32, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_1_F32, mul_mv_id_q5_1_f32, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q8_0_F32, mul_mv_id_q8_0_f32, has_simdgroup_reduction); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_MXFP4_F32, mul_mv_id_mxfp4_f32, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q2_K_F32, mul_mv_id_q2_K_f32, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q3_K_F32, mul_mv_id_q3_K_f32, has_simdgroup_reduction); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q4_K_F32, mul_mv_id_q4_K_f32, has_simdgroup_reduction); @@ -1377,6 +1396,8 @@ static struct ggml_backend_metal_context * ggml_metal_init(ggml_backend_dev_t de GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_0_F32, mul_mm_q5_0_f32, has_simdgroup_mm); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_1_F32, mul_mm_q5_1_f32, has_simdgroup_mm); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q8_0_F32, mul_mm_q8_0_f32, has_simdgroup_mm); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_MXFP4_F32, mul_mm_mxfp4_f32, has_simdgroup_mm); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_MXFP4_F32, mul_mm_mxfp4_f32, has_simdgroup_mm); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q2_K_F32, mul_mm_q2_K_f32, has_simdgroup_mm); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q3_K_F32, mul_mm_q3_K_f32, has_simdgroup_mm); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_K_F32, mul_mm_q4_K_f32, has_simdgroup_mm); @@ -1401,6 +1422,7 @@ static struct ggml_backend_metal_context * ggml_metal_init(ggml_backend_dev_t de GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_0_F16, mul_mm_id_q5_0_f16, has_simdgroup_mm); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_1_F16, mul_mm_id_q5_1_f16, has_simdgroup_mm); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q8_0_F16, mul_mm_id_q8_0_f16, has_simdgroup_mm); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_MXFP4_F16, mul_mm_id_mxfp4_f16, has_simdgroup_mm); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q2_K_F16, mul_mm_id_q2_K_f16, has_simdgroup_mm); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q3_K_F16, mul_mm_id_q3_K_f16, has_simdgroup_mm); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_K_F16, mul_mm_id_q4_K_f16, has_simdgroup_mm); @@ -1583,6 +1605,7 @@ static struct ggml_backend_metal_context * ggml_metal_init(ggml_backend_dev_t de GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_REGLU, reglu, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GEGLU, geglu, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SWIGLU, swiglu, true); + GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SWIGLU_OAI, swiglu_oai, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GEGLU_ERF, geglu_erf, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GEGLU_QUICK, geglu_quick, true); GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SUM_ROWS, sum_rows, true); @@ -1774,6 +1797,7 @@ static bool ggml_metal_supports_op(const struct ggml_backend_metal_device_contex case GGML_GLU_OP_REGLU: case GGML_GLU_OP_GEGLU: case GGML_GLU_OP_SWIGLU: + case GGML_GLU_OP_SWIGLU_OAI: case GGML_GLU_OP_GEGLU_ERF: case GGML_GLU_OP_GEGLU_QUICK: return ggml_is_contiguous_1(op->src[0]) && op->src[0]->type == GGML_TYPE_F32; @@ -1791,6 +1815,7 @@ static bool ggml_metal_supports_op(const struct ggml_backend_metal_device_contex case GGML_OP_SUB: case GGML_OP_MUL: case GGML_OP_DIV: + case GGML_OP_ADD_ID: return op->src[0]->type == GGML_TYPE_F32; case GGML_OP_ACC: case GGML_OP_REPEAT: @@ -1955,6 +1980,7 @@ static bool ggml_metal_supports_op(const struct ggml_backend_metal_device_contex static int ggml_metal_encode_node( ggml_backend_t backend, int idx, + int idx_end, id encoder, struct ggml_metal_mem_pool * mem_pool) { struct ggml_backend_metal_context * ctx = backend->context; @@ -2041,6 +2067,7 @@ static int ggml_metal_encode_node( const enum ggml_type src0t = src0 ? src0->type : GGML_TYPE_COUNT; const enum ggml_type src1t = src1 ? src1->type : GGML_TYPE_COUNT; + const enum ggml_type src2t = src2 ? src2->type : GGML_TYPE_COUNT; const enum ggml_type dstt = dst ? dst->type : GGML_TYPE_COUNT; size_t offs_src0 = 0; @@ -2181,7 +2208,9 @@ static int ggml_metal_encode_node( size_t offs_fuse; id id_fuse; - for (n_fuse = 0; n_fuse <= 6; ++n_fuse) { + // note: in metal, we sometimes encode the graph in parallel so we have to avoid fusing nodes + // across splits. idx_end indicates the last node in the current split + for (n_fuse = 0; n_fuse <= 6 && idx + n_fuse + 1 < idx_end; ++n_fuse) { if (!ggml_can_fuse(gf, idx + n_fuse, ops + n_fuse, 2)) { break; } @@ -2288,6 +2317,38 @@ static int ggml_metal_encode_node( [encoder dispatchThreadgroups:MTLSizeMake(ne01, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; } } break; + case GGML_OP_ADD_ID: + { + GGML_ASSERT(src0t == GGML_TYPE_F32); + GGML_ASSERT(src1t == GGML_TYPE_F32); + GGML_ASSERT(src2t == GGML_TYPE_I32); + GGML_ASSERT(dstt == GGML_TYPE_F32); + + GGML_ASSERT(ggml_is_contiguous_rows(src0)); + + id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ADD_ID].pipeline; + + ggml_metal_kargs_add_id args = { + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb11 =*/ nb11, + /*.nb21 =*/ nb21, + + }; + + [encoder setComputePipelineState:pipeline]; + [encoder setBytes:&args length:sizeof(args) atIndex:0]; + [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; + [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; + [encoder setBuffer:id_src2 offset:offs_src2 atIndex:3]; + [encoder setBuffer:id_dst offset:offs_dst atIndex:4]; + + const int nth = MIN((int) pipeline.maxTotalThreadsPerThreadgroup, ne00); + + [encoder dispatchThreadgroups:MTLSizeMake(ne01, ne02, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; + } break; case GGML_OP_REPEAT: { id pipeline; @@ -2707,6 +2768,9 @@ static int ggml_metal_encode_node( case GGML_GLU_OP_SWIGLU: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SWIGLU].pipeline; break; + case GGML_GLU_OP_SWIGLU_OAI: + pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SWIGLU_OAI].pipeline; + break; case GGML_GLU_OP_GEGLU_ERF: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GEGLU_ERF].pipeline; break; @@ -2717,7 +2781,9 @@ static int ggml_metal_encode_node( GGML_ABORT("fatal error"); } - const int32_t swp = ((const int32_t *) dst->op_params)[1]; + const int32_t swp = ggml_get_op_params_i32(dst, 1); + const float alpha = ggml_get_op_params_f32(dst, 2); + const float limit = ggml_get_op_params_f32(dst, 3); const int32_t i00 = swp ? ne0 : 0; const int32_t i10 = swp ? 0 : ne0; @@ -2731,6 +2797,8 @@ static int ggml_metal_encode_node( /*.nb1 =*/ nb1, /*.i00 =*/ src1 ? 0 : i00, /*.i10 =*/ src1 ? 0 : i10, + /*.alpha=*/ alpha, + /*.limit=*/ limit }; [encoder setComputePipelineState:pipeline]; @@ -2989,8 +3057,13 @@ static int ggml_metal_encode_node( } else { [encoder setBuffer:h_src0 offset:offs_src0 atIndex:1]; } - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - [encoder setBytes:&args length:sizeof(args) atIndex:3]; + if (id_src2) { + [encoder setBuffer:id_src2 offset:offs_src2 atIndex:2]; + } else { + [encoder setBuffer:h_src0 offset:offs_src0 atIndex:2]; + } + [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; + [encoder setBytes:&args length:sizeof(args) atIndex:4]; [encoder setThreadgroupMemoryLength:32*sizeof(float) atIndex:0]; @@ -3138,6 +3211,7 @@ static int ggml_metal_encode_node( /*.n_group =*/ n_group, /*.n_seq_tokens =*/ n_seq_tokens, /*.n_seqs =*/ n_seqs, + /*.s_off =*/ ggml_nelements(src1) * sizeof(float), /*.nb01 =*/ nb01, /*.nb02 =*/ nb02, /*.nb03 =*/ nb03, @@ -3166,12 +3240,22 @@ static int ggml_metal_encode_node( [encoder setBuffer:id_dst offset:offs_dst atIndex:7]; [encoder setBytes:&args length:sizeof(args) atIndex:8]; + // One shared memory bucket for each simd group in the threadgroup + // NOTE: Metal kernels require the buffer size to be multiple of 16 bytes + // https://developer.apple.com/documentation/metal/mtlcomputecommandencoder/1443142-setthreadgroupmemorylength + if (d_state >= 32) { + GGML_ASSERT((int64_t)(d_state / 32) <= 32); + const int64_t shmem_size = 32; + GGML_ASSERT(d_state <= (int64_t)pipeline.maxTotalThreadsPerThreadgroup); + [encoder setThreadgroupMemoryLength:(shmem_size)*sizeof(float) atIndex:0]; + } + if (ne30 == 1) { // Mamba-2 - [encoder dispatchThreadgroups:MTLSizeMake(d_inner, n_head, n_seqs) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; + [encoder dispatchThreadgroups:MTLSizeMake(d_inner, n_head, n_seqs) threadsPerThreadgroup:MTLSizeMake(d_state, 1, 1)]; } else { GGML_ASSERT(d_inner == 1); - [encoder dispatchThreadgroups:MTLSizeMake(n_head, n_seqs, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; + [encoder dispatchThreadgroups:MTLSizeMake(n_head, n_seqs, 1) threadsPerThreadgroup:MTLSizeMake(d_state, 1, 1)]; } } break; case GGML_OP_RWKV_WKV6: @@ -3277,6 +3361,7 @@ static int ggml_metal_encode_node( src0t == GGML_TYPE_Q5_0 || src0t == GGML_TYPE_Q5_1 || src0t == GGML_TYPE_Q8_0 || + src0t == GGML_TYPE_MXFP4 || src0t == GGML_TYPE_IQ4_NL || false) && (ne11 >= 2 && ne11 <= 8) ) || @@ -3369,6 +3454,14 @@ static int ggml_metal_encode_node( case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_5].pipeline; break; default: GGML_ABORT("not implemented"); } break; + case GGML_TYPE_MXFP4: + switch (r1ptg) { + case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_2].pipeline; break; + case 3: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_3].pipeline; break; + case 4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_4].pipeline; break; + case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_MXFP4_F32_R1_5].pipeline; break; + default: GGML_ABORT("not implemented"); + } break; case GGML_TYPE_Q4_K: switch (r1ptg) { case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_2].pipeline; break; @@ -3467,6 +3560,7 @@ static int ggml_metal_encode_node( case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_0_F32 ].pipeline; break; case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_1_F32 ].pipeline; break; case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q8_0_F32 ].pipeline; break; + case GGML_TYPE_MXFP4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_MXFP4_F32 ].pipeline; break; case GGML_TYPE_Q2_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q2_K_F32 ].pipeline; break; case GGML_TYPE_Q3_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q3_K_F32 ].pipeline; break; case GGML_TYPE_Q4_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_K_F32 ].pipeline; break; @@ -3609,6 +3703,13 @@ static int ggml_metal_encode_node( nr0 = N_R0_Q8_0; pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_Q8_0_F32].pipeline; } break; + case GGML_TYPE_MXFP4: + { + nsg = N_SG_MXFP4; + nr0 = N_R0_MXFP4; + smem = 32*sizeof(float); + pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_MXFP4_F32].pipeline; + } break; case GGML_TYPE_Q2_K: { nsg = N_SG_Q2_K; @@ -3742,8 +3843,6 @@ static int ggml_metal_encode_node( case GGML_OP_MUL_MAT_ID: { // src2 = ids - const enum ggml_type src2t = src2->type; GGML_UNUSED(src2t); - GGML_ASSERT(src2t == GGML_TYPE_I32); GGML_ASSERT(!ggml_is_transposed(src0)); @@ -3869,6 +3968,7 @@ static int ggml_metal_encode_node( case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_0_F16 ].pipeline; break; case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_1_F16 ].pipeline; break; case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q8_0_F16 ].pipeline; break; + case GGML_TYPE_MXFP4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_MXFP4_F16 ].pipeline; break; case GGML_TYPE_Q2_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q2_K_F16 ].pipeline; break; case GGML_TYPE_Q3_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q3_K_F16 ].pipeline; break; case GGML_TYPE_Q4_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_K_F16 ].pipeline; break; @@ -4004,6 +4104,13 @@ static int ggml_metal_encode_node( nr0 = N_R0_Q8_0; pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q8_0_F32].pipeline; } break; + case GGML_TYPE_MXFP4: + { + nsg = N_SG_MXFP4; + nr0 = N_R0_MXFP4; + smem = 32*sizeof(float); + pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_MXFP4_F32].pipeline; + } break; case GGML_TYPE_Q2_K: { nsg = N_SG_Q2_K; @@ -4156,6 +4263,7 @@ static int ggml_metal_encode_node( case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_0 ].pipeline; break; case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_1 ].pipeline; break; case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q8_0 ].pipeline; break; + case GGML_TYPE_MXFP4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_MXFP4 ].pipeline; break; case GGML_TYPE_Q2_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q2_K ].pipeline; break; case GGML_TYPE_Q3_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q3_K ].pipeline; break; case GGML_TYPE_Q4_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_K ].pipeline; break; @@ -4288,7 +4396,7 @@ static int ggml_metal_encode_node( ops[1] = GGML_OP_MUL; ops[2] = GGML_OP_ADD; - for (n_fuse = 0; n_fuse <= 1; ++n_fuse) { + for (n_fuse = 0; n_fuse <= 1 && idx + n_fuse + 1 < idx_end; ++n_fuse) { if (!ggml_can_fuse(gf, idx + n_fuse, ops + n_fuse, 2)) { break; } @@ -4966,11 +5074,14 @@ static int ggml_metal_encode_node( GGML_ASSERT(ne11 == ne21); GGML_ASSERT(ne12 == ne22); - struct ggml_tensor * src3 = node->src[3]; + struct ggml_tensor * src3 = node->src[3]; // mask + struct ggml_tensor * src4 = node->src[4]; // sinks size_t offs_src3 = 0; + size_t offs_src4 = 0; id id_src3 = src3 ? ggml_metal_get_buffer(src3, &offs_src3) : nil; + id id_src4 = src4 ? ggml_metal_get_buffer(src4, &offs_src4) : nil; GGML_ASSERT(!src3 || src3->type == GGML_TYPE_F16); GGML_ASSERT(!src3 || src3->ne[1] >= GGML_PAD(src0->ne[1], 8) && @@ -4986,8 +5097,6 @@ static int ggml_metal_encode_node( const uint64_t nb32 = src3 ? src3->nb[2] : 0; GGML_UNUSED(nb32); const uint64_t nb33 = src3 ? src3->nb[3] : 0; GGML_UNUSED(nb33); - const enum ggml_type src2t = src2 ? src2->type : GGML_TYPE_COUNT; GGML_UNUSED(src2t); - float scale; float max_bias; float logit_softcap; @@ -5375,7 +5484,12 @@ static int ggml_metal_encode_node( } else { [encoder setBuffer:id_src0 offset:offs_src0 atIndex:4]; } - [encoder setBuffer:id_dst offset:offs_dst atIndex:5]; + if (id_src4) { + [encoder setBuffer:id_src4 offset:offs_src4 atIndex:5]; + } else { + [encoder setBuffer:id_src0 offset:offs_src0 atIndex:5]; + } + [encoder setBuffer:id_dst offset:offs_dst atIndex:6]; if (!use_vec_kernel) { // half8x8 kernel @@ -6271,7 +6385,11 @@ static void ggml_backend_metal_set_n_cb(ggml_backend_t backend, int n_cb) { [encoder pushDebugGroup:[NSString stringWithCString:ggml_op_desc(ggml_graph_node(ctx->gf, idx)) encoding:NSUTF8StringEncoding]]; } - const int res = ggml_metal_encode_node(backend, idx, encoder, mem_pool); + const int res = ggml_metal_encode_node(backend, idx, node_end, encoder, mem_pool); + if (idx + res > node_end) { + GGML_ABORT("fusion error: nodes spanning multiple encoders have been fused. this indicates a bug in the fusion logic %s", + "https://github.com/ggml-org/llama.cpp/pull/14849"); + } if (should_capture) { [encoder popDebugGroup]; diff --git a/ggml/src/ggml-metal/ggml-metal.metal b/ggml/src/ggml-metal/ggml-metal.metal index f62b9ad548..b35a3bbdc3 100644 --- a/ggml/src/ggml-metal/ggml-metal.metal +++ b/ggml/src/ggml-metal/ggml-metal.metal @@ -35,6 +35,10 @@ constexpr constant static float kvalues_iq4nl_f[16] = { -127.f, -104.f, -83.f, -65.f, -49.f, -35.f, -22.f, -10.f, 1.f, 13.f, 25.f, 38.f, 53.f, 69.f, 89.f, 113.f }; +constexpr constant static float kvalues_mxfp4_f[16] = { + 0, .5f, 1.f, 1.5f, 2.f, 3.f, 4.f, 6.f, -0, -.5f, -1.f, -1.5f, -2.f, -3.f, -4.f, -6.f +}; + static inline int best_index_int8(int n, constant float * val, float x) { if (x <= val[0]) return 0; if (x >= val[n-1]) return n-1; @@ -46,6 +50,18 @@ static inline int best_index_int8(int n, constant float * val, float x) { return x - val[mu-1] < val[mu] - x ? mu-1 : mu; } +static inline float e8m0_to_fp32(uint8_t x) { + uint32_t bits; + + if (x == 0) { + bits = 0x00400000; + } else { + bits = (uint32_t) x << 23; + } + + return as_type(bits); +} + // NOTE: this is not dequantizing - we are simply fitting the template template void dequantize_f32(device const float4x4 * src, short il, thread type4x4 & reg) { @@ -242,6 +258,27 @@ void quantize_q5_1(device const float * src, device block_q5_1 & dst) { } } +void quantize_q8_0(device const float * src, device block_q8_0 & dst) { +#pragma METAL fp math_mode(safe) + float amax = 0.0f; // absolute max + + for (int j = 0; j < QK8_0; j++) { + const float v = src[j]; + amax = MAX(amax, fabs(v)); + } + + const float d = amax / ((1 << 7) - 1); + const float id = d ? 1.0f/d : 0.0f; + + dst.d = d; + + for (int j = 0; j < QK8_0; ++j) { + const float x0 = src[j]*id; + + dst.qs[j] = round(x0); + } +} + void quantize_iq4_nl(device const float * src, device block_iq4_nl & dst) { #pragma METAL fp math_mode(safe) float amax = 0.0f; // absolute max @@ -462,25 +499,34 @@ void dequantize_q8_0_t4(device const block_q8_0 *xb, short il, thread type4 & re } } -void quantize_q8_0(device const float * src, device block_q8_0 & dst) { -#pragma METAL fp math_mode(safe) - float amax = 0.0f; // absolute max +template +void dequantize_mxfp4(device const block_mxfp4 * xb, short il, thread type4x4 & reg) { + device const uint8_t * q2 = (device const uint8_t *)xb->qs; - for (int j = 0; j < QK8_0; j++) { - const float v = src[j]; - amax = MAX(amax, fabs(v)); + const float d = e8m0_to_fp32(xb->e); + const uint8_t shr = il >= 1 ? 4 : 0; + + for (int i = 0; i < 4; ++i) { + reg[i][0] = d * kvalues_mxfp4_f[(q2[4*i + 0] >> shr) & 0x0F]; + reg[i][1] = d * kvalues_mxfp4_f[(q2[4*i + 1] >> shr) & 0x0F]; + reg[i][2] = d * kvalues_mxfp4_f[(q2[4*i + 2] >> shr) & 0x0F]; + reg[i][3] = d * kvalues_mxfp4_f[(q2[4*i + 3] >> shr) & 0x0F]; } +} - const float d = amax / ((1 << 7) - 1); - const float id = d ? 1.0f/d : 0.0f; +template +void dequantize_mxfp4_t4(device const block_mxfp4 * xb, short il, thread type4 & reg) { + device const uint8_t * q2 = (device const uint8_t *)xb->qs; - dst.d = d; + const float d = e8m0_to_fp32(xb->e); + const short il4 = il%4; - for (int j = 0; j < QK8_0; ++j) { - const float x0 = src[j]*id; + const uint8_t shr = il >= 4 ? 4 : 0; - dst.qs[j] = round(x0); - } + reg[0] = d * kvalues_mxfp4_f[(q2[4*il4 + 0] >> shr) & 0x0F]; + reg[1] = d * kvalues_mxfp4_f[(q2[4*il4 + 1] >> shr) & 0x0F]; + reg[2] = d * kvalues_mxfp4_f[(q2[4*il4 + 2] >> shr) & 0x0F]; + reg[3] = d * kvalues_mxfp4_f[(q2[4*il4 + 3] >> shr) & 0x0F]; } template @@ -960,6 +1006,32 @@ kernel void kernel_div( } } +kernel void kernel_add_id( + constant ggml_metal_kargs_add_id & args, + device const char * src0, + device const char * src1, + device const char * src2, + device char * dst, + uint3 tgpig[[threadgroup_position_in_grid]], + ushort3 tpitg[[thread_position_in_threadgroup]], + ushort3 ntg[[threads_per_threadgroup]]) { + const int i1 = tgpig.x; + const int i2 = tgpig.y; + + const int i11 = *((device const int32_t *) (src2 + i1*sizeof(int32_t) + i2*args.nb21)); + + const size_t nb1 = args.ne0 * sizeof(float); + const size_t nb2 = args.ne1 * nb1; + + device float * dst_row = (device float *)((device char *)dst + i1*nb1 + i2*nb2); + device const float * src0_row = (device const float *)((device char *)src0 + i1*args.nb01 + i2*args.nb02); + device const float * src1_row = (device const float *)((device char *)src1 + i11*args.nb11); + + for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { + dst_row[i0] = src0_row[i0] + src1_row[i0]; + } +} + template kernel void kernel_repeat( constant ggml_metal_kargs_repeat & args, @@ -1431,6 +1503,32 @@ kernel void kernel_swiglu( } } +kernel void kernel_swiglu_oai( + device const char * src0, + device const char * src1, + device char * dst, + constant ggml_metal_kargs_glu & args, + uint tgpig[[threadgroup_position_in_grid]], + uint tpitg[[thread_position_in_threadgroup]], + uint ntg[[threads_per_threadgroup]]) { + device const float * src0_row = (device const float *) ((device const char *) src0 + tgpig*args.nb01) + args.i00; + device const float * src1_row = (device const float *) ((device const char *) src1 + tgpig*args.nb11) + args.i10; + device float * dst_row = (device float *) ((device char *) dst + tgpig*args.nb1); + + for (int i0 = tpitg; i0 < args.ne0; i0 += ntg) { + float x0 = src0_row[i0]; + float x1 = src1_row[i0]; + + x0 = min(x0, args.limit); + x1 = max(min(x1, args.limit), -args.limit); + + float out_glu = x0 / (1.0f + exp(-x0 * args.alpha)); + out_glu = out_glu * (1.0f + x1); + + dst_row[i0] = out_glu; + } +} + kernel void kernel_geglu_erf( device const char * src0, device const char * src1, @@ -1534,6 +1632,7 @@ template kernel void kernel_soft_max( device const char * src0, device const char * src1, + device const char * src2, device char * dst, constant ggml_metal_kargs_soft_max & args, threadgroup float * buf [[threadgroup(0)]], @@ -1552,6 +1651,7 @@ kernel void kernel_soft_max( device const float * psrc0 = (device const float *) (src0 + i01*args.nb01 + i02*args.nb02 + i03*args.nb03); device const T * pmask = src1 != src0 ? (device const T * ) (src1 + i11*args.nb11 + i12*args.nb12 + i13*args.nb13) : nullptr; + device const float * psrc2 = src2 != src0 ? (device const float *) (src2) : nullptr; device float * pdst = (device float *) (dst + i01*args.nb1 + i02*args.nb2 + i03*args.nb3); float slope = 1.0f; @@ -1567,7 +1667,7 @@ kernel void kernel_soft_max( } // parallel max - float lmax = -INFINITY; + float lmax = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = tpitg.x; i00 < args.ne00; i00 += tptg.x) { lmax = MAX(lmax, psrc0[i00]*args.scale + (pmask ? slope*pmask[i00] : 0.0f)); @@ -1623,6 +1723,10 @@ kernel void kernel_soft_max( sum = simd_sum(sum); } + if (psrc2) { + sum += exp(psrc2[i02] - max_val); + } + const float inv_sum = 1.0f/sum; for (int i00 = tpitg.x; i00 < args.ne00; i00 += tptg.x) { @@ -1634,6 +1738,7 @@ template kernel void kernel_soft_max_4( device const char * src0, device const char * src1, + device const char * src2, device char * dst, constant ggml_metal_kargs_soft_max & args, threadgroup float * buf [[threadgroup(0)]], @@ -1652,6 +1757,7 @@ kernel void kernel_soft_max_4( device const float4 * psrc4 = (device const float4 *) (src0 + i01*args.nb01 + i02*args.nb02 + i03*args.nb03); device const T * pmask = src1 != src0 ? (device const T * ) (src1 + i11*args.nb11 + i12*args.nb12 + i13*args.nb13) : nullptr; + device const float * psrc2 = src2 != src0 ? (device const float * ) (src2) : nullptr; device float4 * pdst4 = (device float4 *) (dst + i01*args.nb1 + i02*args.nb2 + i03*args.nb3); float slope = 1.0f; @@ -1666,7 +1772,7 @@ kernel void kernel_soft_max_4( } // parallel max - float4 lmax4 = -INFINITY; + float4 lmax4 = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = tpitg.x; i00 < args.ne00/4; i00 += tptg.x) { lmax4 = fmax(lmax4, psrc4[i00]*args.scale + (float4)((pmask ? slope*pmask[i00] : 0.0f))); @@ -1725,6 +1831,10 @@ kernel void kernel_soft_max_4( sum = simd_sum(sum); } + if (psrc2) { + sum += exp(psrc2[i02] - max_val); + } + const float inv_sum = 1.0f/sum; for (int i00 = tpitg.x; i00 < args.ne00/4; i00 += tptg.x) { @@ -1823,10 +1933,16 @@ kernel void kernel_ssm_scan_f32( device const void * src5, device const void * src6, device float * dst, + threadgroup float * shared [[threadgroup(0)]], constant ggml_metal_kargs_ssm_scan & args, - uint3 tgpig[[threadgroup_position_in_grid]], - uint3 tpitg[[thread_position_in_threadgroup]], - uint3 ntg[[threads_per_threadgroup]]) { + uint3 tgpig[[threadgroup_position_in_grid]], + uint3 tpitg[[thread_position_in_threadgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgptg[[simdgroups_per_threadgroup]], + uint3 tgpg[[threadgroups_per_grid]]) { + + const int64_t i0 = tpitg.x; const int64_t i1 = 0; const int64_t ir = tgpig.x; // current head const int64_t i3 = tgpig.y; // current seq @@ -1841,41 +1957,88 @@ kernel void kernel_ssm_scan_f32( const int64_t ng = args.n_group; const int64_t n_t = args.n_seq_tokens; - const int64_t s_off = nr * nh * n_t * args.n_seqs * sizeof(float); + const int64_t s_off = args.s_off; device const int32_t * ids = (device const int32_t *) src6; - device const float * s0 = (device const float *) ((device const char *) src0 + ir*args.nb02 + ids[i3]*args.nb03); - device float * s = (device float *) ((device char *) dst + ir*args.nb02 + i3*args.nb03 + s_off); + device const float * s0_buff = (device const float *) ((device const char *) src0 + ir*args.nb02 + ids[i3]*args.nb03); + device float * s_buff = (device float *) ((device char *) dst + ir*args.nb02 + i3*args.nb03 + s_off); + const int64_t i = i0 + i1*nc; + float s0 = s0_buff[i]; + float s = s_buff[i]; + + device const float * A = (device const float *) ((device const char *) src3 + ir*args.nb31); + device const float * x_block = (device const float *) ((device const char *) src1 + i1*nb10 + ir*args.nb11 + i3*args.nb13); + device const float * dt_block = (device const float *) ((device const char *) src2 + ir*nb20 + i3*args.nb22); + device const float * B_block = (device const float *) ((device const char *) src4 + (ir & (ng - 1))*args.nb41 + i3*args.nb43); + device const float * C_block = (device const float *) ((device const char *) src5 + (ir & (ng - 1))*args.nb51 + i3*args.nb53); + device float * y_block = (device float *) ((device char *) dst + (i1 + ir*(nr) + i3*(n_t*nh*nr))*nb00); for (int64_t i2 = 0; i2 < n_t; ++i2) { - device const float * x = (device const float *) ((device const char *) src1 + i1*nb10 + ir*args.nb11 + i2*args.nb12 + i3*args.nb13); // {dim, nh, nt, ns} - device const float * dt = (device const float *) ((device const char *) src2 + ir*nb20 + i2*args.nb21 + i3*args.nb22); // {nh, nt, ns} - device const float * A = (device const float *) ((device const char *) src3 + ir*args.nb31); // {d_state, nh} - device const float * B = (device const float *) ((device const char *) src4 + (ir & (ng - 1))*args.nb41 + i2*args.nb42 + i3*args.nb43); // {d_state, ng, nt, ns} - device const float * C = (device const float *) ((device const char *) src5 + (ir & (ng - 1))*args.nb51 + i2*args.nb52 + i3*args.nb53); // {d_state, ng, nt, ns} - device float * y = (device float *) ((device char *) dst + (i1 + ir*(nr) + i2*(nh*nr) + i3*(n_t*nh*nr))*nb00); // {dim, nh, nt, ns} + device const float * x = (device const float *) ((device const char *) x_block + i2*args.nb12); // {dim, nh, nt, ns} + device const float * dt = (device const float *) ((device const char *) dt_block + i2*args.nb21); // {nh, nt, ns} + device const float * B = (device const float *) ((device const char *) B_block + i2*args.nb42); // {d_state, ng, nt, ns} + device const float * C = (device const float *) ((device const char *) C_block + i2*args.nb52); // {d_state, ng, nt, ns} + device float * y = (device float *) ((device char *) y_block + i2*(nh*nr*nb00)); // {dim, nh, nt, ns} const float dt_soft_plus = dt[0] <= 20.0f ? log(1.0f + exp(dt[0])) : dt[0]; const float x_dt = x[0] * dt_soft_plus; - float sumf = 0.0f; - for (int64_t i0 = 0; i0 < nc; ++i0) { - const int64_t i = i0 + i1*nc; - const float state = (s0[i] * exp(dt_soft_plus * A[i0])) + (B[i0] * x_dt); - sumf += state * C[i0]; - s[i] = state; + const float state = (s0 * exp(dt_soft_plus * A[i0])) + (B[i0] * x_dt); + s = state; + + // Parallel sum: This relies on the fact that this kernel will be + // dispatched with each threadgroup having (d_state, 1, 1) threads which + // are subdivided into SIMD groups of size `sgptg`. The goal is to + // compute y = sum({state * C[i] for i in range(d_state)}). + // To parallelize this effectively, we first use simd_sum over each SIMD + // group to compute the sum of each SIMD group, then place the result in + // the SIMD group's indexed bucket in the shared memory. We then sum + // over the individual group sums to compute the final sum. + + // Computed for each thread + float sumf = state * C[i0]; + + // Sum the threads in the simd group => simd sum + sumf = simd_sum(sumf); + + if (sgptg > 1) { + + // Once per simd group, place the group sum into the shared buffer + if (tiisg == 0) { + shared[sgitg] = sumf; + } + + // Wait for all threads in the threadgroup to reach this point. This + // ensures that all elements of the shared buffer are populated with the + // sum of the individual simd groups. + threadgroup_barrier(mem_flags::mem_threadgroup); + + // For simd group 0 at indices < num simd groups, extract the shared + // simd sum + sumf = 0.0f; + if (sgitg == 0) { + if (tiisg < sgptg) { + sumf = shared[tiisg]; + } + sumf = simd_sum(sumf); + if (tiisg == 0) { + y[0] = sumf; + } + } + } else if (tiisg == 0) { + y[0] = sumf; } - y[0] = sumf; - // recurse s0 = s; } + + // Assign the final state to the output buffer + s_buff[i] = s; } // ref: ggml.c:ggml_compute_forward_ssm_scan_f32, Mamba-2 part -// TODO: optimize (e.g. by parallelizing over d_state) kernel void kernel_ssm_scan_f32_group( device const void * src0, device const void * src1, @@ -1885,10 +2048,16 @@ kernel void kernel_ssm_scan_f32_group( device const void * src5, device const void * src6, device float * dst, + threadgroup float * shared [[threadgroup(0)]], constant ggml_metal_kargs_ssm_scan & args, - uint3 tgpig[[threadgroup_position_in_grid]], - uint3 tpitg[[thread_position_in_threadgroup]], - uint3 ntg[[threads_per_threadgroup]]) { + uint3 tgpig[[threadgroup_position_in_grid]], + uint3 tpitg[[thread_position_in_threadgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgptg[[simdgroups_per_threadgroup]], + uint3 tgpg[[threadgroups_per_grid]]) { + + const int64_t i0 = tpitg.x; const int64_t i1 = tgpig.x; const int64_t ir = tgpig.y; // current head const int64_t i3 = tgpig.z; // current seq @@ -1903,38 +2072,81 @@ kernel void kernel_ssm_scan_f32_group( const int64_t ng = args.n_group; const int64_t n_t = args.n_seq_tokens; - const int64_t s_off = nr * nh * n_t * args.n_seqs * sizeof(float); + const int64_t s_off = args.s_off; device const int32_t * ids = (device const int32_t *) src6; - device const float * s0 = (device const float *) ((device const char *) src0 + ir*args.nb02 + ids[i3]*args.nb03); - device float * s = (device float *) ((device char *) dst + ir*args.nb02 + i3*args.nb03 + s_off); + device const float * s0_buff = (device const float *) ((device const char *) src0 + ir*args.nb02 + ids[i3]*args.nb03); + device float * s_buff = (device float *) ((device char *) dst + ir*args.nb02 + i3*args.nb03 + s_off); + const int64_t i = i0 + i1*nc; + float s0 = s0_buff[i]; + float s = s_buff[i]; + + device const float * A = (device const float *) ((device const char *) src3 + ir*args.nb31); // {1, nh} + device const float * x_block = (device const float *) ((device const char *) src1 + i1*nb10 + ir*args.nb11 + i3*args.nb13); + device const float * dt_block = (device const float *) ((device const char *) src2 + ir*nb20 + i3*args.nb22); + device const float * B_block = (device const float *) ((device const char *) src4 + (ir & (ng - 1))*args.nb41 + i3*args.nb43); + device const float * C_block = (device const float *) ((device const char *) src5 + (ir & (ng - 1))*args.nb51 + i3*args.nb53); + device float * y_block = (device float *) ((device char *) dst + (i1 + ir*(nr) + i3*(n_t*nh*nr))*nb00); for (int64_t i2 = 0; i2 < n_t; ++i2) { - device const float * x = (device const float *) ((device const char *) src1 + i1*nb10 + ir*args.nb11 + i2*args.nb12 + i3*args.nb13); // {dim, nh, nt, ns} - device const float * dt = (device const float *) ((device const char *) src2 + ir*nb20 + i2*args.nb21 + i3*args.nb22); // {nh, nt, ns} - device const float * A = (device const float *) ((device const char *) src3 + ir*args.nb31); // {1, nh} - device const float * B = (device const float *) ((device const char *) src4 + (ir & (ng - 1))*args.nb41 + i2*args.nb42 + i3*args.nb43); // {d_state, ng, nt, ns} - device const float * C = (device const float *) ((device const char *) src5 + (ir & (ng - 1))*args.nb51 + i2*args.nb52 + i3*args.nb53); // {d_state, ng, nt, ns} - device float * y = (device float *) ((device char *) dst + (i1 + ir*(nr) + i2*(nh*nr) + i3*(n_t*nh*nr))*nb00); // {dim, nh, nt, ns} + device const float * x = (device const float *) ((device const char *) x_block + i2*args.nb12); // {dim, nh, nt, ns} + device const float * dt = (device const float *) ((device const char *) dt_block + i2*args.nb21); // {nh, nt, ns} + device const float * B = (device const float *) ((device const char *) B_block + i2*args.nb42); // {d_state, ng, nt, ns} + device const float * C = (device const float *) ((device const char *) C_block + i2*args.nb52); // {d_state, ng, nt, ns} + device float * y = (device float *) ((device char *) y_block + i2*(nh*nr*nb00)); // {dim, nh, nt, ns} const float dt_soft_plus = dt[0] <= 20.0f ? log(1.0f + exp(dt[0])) : dt[0]; const float x_dt = x[0] * dt_soft_plus; const float dA = exp(dt_soft_plus * A[0]); - float sumf = 0.0f; - for (int64_t i0 = 0; i0 < nc; ++i0) { - const int64_t i = i0 + i1*nc; - const float state = (s0[i] * dA) + (B[i0] * x_dt); - sumf += state * C[i0]; - s[i] = state; + const float state = (s0 * dA) + (B[i0] * x_dt); + s = state; + + // Parallel sum: This relies on the fact that this kernel will be + // dispatched with each threadgroup having (d_state, 1, 1) threads which + // are subdivided into SIMD groups of size `sgptg`. The goal is to + // compute y = sum({state * C[i] for i in range(d_state)}). + // To parallelize this effectively, we first use simd_sum over each SIMD + // group to compute the sum of each SIMD group, then place the result in + // the SIMD group's indexed bucket in the shared memory. We then sum + // over the individual group sums to compute the final sum. + + // Computed for each thread + float sumf = state * C[i0]; + + // Sum the threads in the simd group => simd sum + sumf = simd_sum(sumf); + + // Once per simd group, place the group sum into the shared buffer + if (tiisg == 0) { + shared[sgitg] = sumf; } - y[0] = sumf; + // Wait for all threads in the threadgroup to reach this point. This + // ensures that all elements of the shared buffer are populated with the + // sum of the individual simd groups. + threadgroup_barrier(mem_flags::mem_threadgroup); + + // For simd group 0 at indices < num simd groups, extract the shared + // simd sum + sumf = 0.0f; + if (sgitg == 0) { + if (tiisg < sgptg) { + sumf = shared[tiisg]; + } + sumf = simd_sum(sumf); + if (tiisg == 0) { + y[0] = sumf; + } + } // recurse s0 = s; } + + // Assign the final state to the output buffer + s_buff[i] = s; } kernel void kernel_rwkv_wkv6_f32( @@ -3004,6 +3216,11 @@ template [[host_name("kernel_mul_mv_ext_q8_0_f32_r1_3")]] kernel mul_mv_ext_q4 template [[host_name("kernel_mul_mv_ext_q8_0_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, block_q8_0, 32, dequantize_q8_0_t4>; template [[host_name("kernel_mul_mv_ext_q8_0_f32_r1_5")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<5, block_q8_0, 32, dequantize_q8_0_t4>; +template [[host_name("kernel_mul_mv_ext_mxfp4_f32_r1_2")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<2, block_mxfp4, 32, dequantize_mxfp4_t4>; +template [[host_name("kernel_mul_mv_ext_mxfp4_f32_r1_3")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<3, block_mxfp4, 32, dequantize_mxfp4_t4>; +template [[host_name("kernel_mul_mv_ext_mxfp4_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, block_mxfp4, 32, dequantize_mxfp4_t4>; +template [[host_name("kernel_mul_mv_ext_mxfp4_f32_r1_5")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<5, block_mxfp4, 32, dequantize_mxfp4_t4>; + template [[host_name("kernel_mul_mv_ext_iq4_nl_f32_r1_2")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<2, block_iq4_nl, 32, dequantize_iq4_nl_t4>; template [[host_name("kernel_mul_mv_ext_iq4_nl_f32_r1_3")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<3, block_iq4_nl, 32, dequantize_iq4_nl_t4>; template [[host_name("kernel_mul_mv_ext_iq4_nl_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, block_iq4_nl, 32, dequantize_iq4_nl_t4>; @@ -3990,6 +4207,7 @@ kernel void kernel_flash_attn_ext( device const char * k, device const char * v, device const char * mask, + device const char * sinks, device char * dst, threadgroup half * shmem_f16 [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], @@ -4305,6 +4523,35 @@ kernel void kernel_flash_attn_ext( } } + if (sinks != q && sgitg == 0) { + for (ushort j = 0; j < Q; ++j) { + const float m = M[j]; + const float s = tiisg == 0 ? ((device const float *) sinks)[iq2] : -FLT_MAX/2; + + M[j] = simd_max(max(M[j], s)); + + const float ms = exp(m - M[j]); + const float vs = exp(s - M[j]); + + S[j] = S[j]*ms + simd_sum(vs); + + if (tiisg == j) { + ss[j*TS + 2*C + j] = ms; + } + } + + // O = diag(ms)*O + { + s8x8_t ms; + simdgroup_load(ms, ss + 2*C, TS, 0, false); + + #pragma unroll(DV8) + for (short i = 0; i < DV8; ++i) { + simdgroup_multiply(lo[i], ms, lo[i]); + } + } + } + // these are needed for reducing the results from the simdgroups (reuse the ss buffer) for (short j = tiisg; j < Q; j += NW) { ss[j*TS + 0] = S[j]; @@ -4516,6 +4763,7 @@ kernel void kernel_flash_attn_ext_vec( device const char * k, device const char * v, device const char * mask, + device const char * sinks, device char * dst, threadgroup half * shmem_f16 [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], @@ -4733,6 +4981,23 @@ kernel void kernel_flash_attn_ext_vec( } } + if (sinks != q && sgitg == 0) { + const float m = M; + const float s = tiisg == 0 ? ((device const float *) sinks)[iq2] : -FLT_MAX/2; + + M = simd_max(max(M, s)); + + const float ms = exp(m - M); + const float vs = exp(s - M); + + S = S*ms + simd_sum(vs); + +#pragma unroll(DV4/NL) + for (short ii = 0; ii < DV4; ii += NL) { + lo[ii/NL] *= ms; + } + } + // these are needed for reducing the results from the simdgroups (reuse the ss buffer) if (tiisg == 0) { ss[0] = (s_t) S; @@ -6838,6 +7103,95 @@ kernel void kernel_mul_mv_iq4_xs_f32( kernel_mul_mv_iq4_xs_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } +template +void kernel_mul_mv_mxfp4_f32_impl( + args_t args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem, + uint3 tgpig, + ushort tiisg, + ushort sgitg) { + + threadgroup float * shmem_f32 = (threadgroup float *) shmem; + const int nb = args.ne00/QK_MXFP4; + + const int r0 = tgpig.x; + const int r1 = tgpig.y; + const int im = tgpig.z; + + const int first_row = (r0 * nsg + sgitg) * nr0; + + const uint i12 = im%args.ne12; + const uint i13 = im/args.ne12; + + const uint64_t offset0 = first_row*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; + + device const block_mxfp4 * x = (device const block_mxfp4 *) (src0 + offset0); + device const float * y = (device const float *) (src1 + offset1); + + const short ix = tiisg/2; // 0...15 + const short it = tiisg%2; // 0 or 1 + + shmem_f32[tiisg] = kvalues_mxfp4_f[tiisg%16]; + threadgroup_barrier(mem_flags::mem_threadgroup); + + float4 yl[4]; + float sumf[nr0]={0.f}; + + device const float * yb = y + ix * QK_MXFP4 + it * 8; + + for (int ib = ix; ib < nb; ib += 16) { + device const float4 * y4 = (device const float4 *)yb; + yl[0] = y4[0]; + yl[1] = y4[4]; + yl[2] = y4[1]; + yl[3] = y4[5]; + +#pragma unroll(nr0) + for (short row = 0; row < nr0; row++) { + device const block_mxfp4 & xb = x[row*nb + ib]; + device const uint8_t * q2 = (device const uint8_t *)(xb.qs + 8*it); + + float4 acc1 = yl[0]*float4(shmem_f32[q2[0] & 0x0F], shmem_f32[q2[1] & 0x0F], shmem_f32[q2[2] & 0x0F], shmem_f32[q2[3] & 0x0F]); + float4 acc2 = yl[1]*float4(shmem_f32[q2[0] >> 4 ], shmem_f32[q2[1] >> 4 ], shmem_f32[q2[2] >> 4 ], shmem_f32[q2[3] >> 4 ]); + float4 acc3 = yl[2]*float4(shmem_f32[q2[4] & 0x0F], shmem_f32[q2[5] & 0x0F], shmem_f32[q2[6] & 0x0F], shmem_f32[q2[7] & 0x0F]); + float4 acc4 = yl[3]*float4(shmem_f32[q2[4] >> 4 ], shmem_f32[q2[5] >> 4 ], shmem_f32[q2[6] >> 4 ], shmem_f32[q2[7] >> 4 ]); + + acc1 = (acc1 + acc3) + (acc2 + acc4); + + sumf[row] += e8m0_to_fp32(xb.e) * ((acc1[0] + acc1[1]) + (acc1[2] + acc1[3])); + } + + yb += 16 * QK_MXFP4; + } + + device float * dst_f32 = (device float *) dst + (uint64_t)im*args.ne0*args.ne1 + (uint64_t)r1*args.ne0; + + for (int row = 0; row < nr0 && first_row + row < args.ne0; ++row) { + float sum_all = simd_sum(sumf[row]); + if (tiisg == 0) { + dst_f32[first_row + row] = sum_all; + } + } +} + +[[host_name("kernel_mul_mv_mxfp4_f32")]] +kernel void kernel_mul_mv_mxfp4_f32( + constant ggml_metal_kargs_mul_mv & args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]]) { + + kernel_mul_mv_mxfp4_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); +} + template kernel void kernel_get_rows_q( constant ggml_metal_kargs_get_rows & args, @@ -7373,6 +7727,7 @@ template [[host_name("kernel_get_rows_q4_1")]] kernel get_rows_q_t kernel_get template [[host_name("kernel_get_rows_q5_0")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q5_1")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q8_0")]] kernel get_rows_q_t kernel_get_rows_q; +template [[host_name("kernel_get_rows_mxfp4")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q2_K")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q3_K")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q4_K")]] kernel get_rows_q_t kernel_get_rows_q; @@ -7425,6 +7780,7 @@ template [[host_name("kernel_mul_mm_q4_1_f32")]] kernel mul_mm_t kernel_mul_m template [[host_name("kernel_mul_mm_q5_0_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q5_1_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q8_0_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_mxfp4_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q2_K_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q3_K_f32")]] kernel mul_mm_t kernel_mul_mm; template [[host_name("kernel_mul_mm_q4_K_f32")]] kernel mul_mm_t kernel_mul_mm; @@ -7456,6 +7812,7 @@ template [[host_name("kernel_mul_mm_id_q4_1_f16")]] kernel mul_mm_id kernel_m template [[host_name("kernel_mul_mm_id_q5_0_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q5_1_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q8_0_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_mxfp4_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q2_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q3_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; template [[host_name("kernel_mul_mm_id_q4_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; @@ -7601,6 +7958,8 @@ template [[host_name("kernel_mul_mv_id_q4_1_f32")]] kernel kernel_mul_mv_id_t template [[host_name("kernel_mul_mv_id_q5_0_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; template [[host_name("kernel_mul_mv_id_q5_1_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_mxfp4_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; + template [[host_name("kernel_mul_mv_id_q2_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; template [[host_name("kernel_mul_mv_id_q3_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; template [[host_name("kernel_mul_mv_id_q4_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; diff --git a/ggml/src/ggml-musa/CMakeLists.txt b/ggml/src/ggml-musa/CMakeLists.txt index 971314debc..02904526ad 100644 --- a/ggml/src/ggml-musa/CMakeLists.txt +++ b/ggml/src/ggml-musa/CMakeLists.txt @@ -34,8 +34,12 @@ if (MUSAToolkit_FOUND) list(APPEND GGML_SOURCES_MUSA ${SRCS}) file(GLOB SRCS "../ggml-cuda/template-instances/mmq*.cu") list(APPEND GGML_SOURCES_MUSA ${SRCS}) - file(GLOB SRCS "../ggml-musa/*.cu") - list(APPEND GGML_SOURCES_MUSA ${SRCS}) + + if (GGML_MUSA_MUDNN_COPY) + file(GLOB SRCS "../ggml-musa/*.cu") + list(APPEND GGML_SOURCES_MUSA ${SRCS}) + add_compile_definitions(GGML_MUSA_MUDNN_COPY) + endif() if (GGML_CUDA_FA_ALL_QUANTS) file(GLOB SRCS "../ggml-cuda/template-instances/fattn-vec*.cu") @@ -72,6 +76,10 @@ if (MUSAToolkit_FOUND) add_compile_definitions(GGML_USE_MUSA) add_compile_definitions(GGML_CUDA_PEER_MAX_BATCH_SIZE=${GGML_CUDA_PEER_MAX_BATCH_SIZE}) + if (GGML_MUSA_GRAPHS) + add_compile_definitions(GGML_MUSA_GRAPHS) + endif() + if (GGML_CUDA_FORCE_MMQ) add_compile_definitions(GGML_CUDA_FORCE_MMQ) endif() @@ -97,10 +105,16 @@ if (MUSAToolkit_FOUND) endif() if (GGML_STATIC) - # TODO: mudnn has not provided static libraries yet target_link_libraries(ggml-musa PRIVATE MUSA::musart_static MUSA::mublas_static) + # TODO: mudnn has not provided static libraries yet + # if (GGML_MUSA_MUDNN_COPY) + # target_link_libraries(ggml-musa PRIVATE mudnn_static) + # endif() else() - target_link_libraries(ggml-musa PRIVATE MUSA::musart MUSA::mublas mudnn) + target_link_libraries(ggml-musa PRIVATE MUSA::musart MUSA::mublas) + if (GGML_MUSA_MUDNN_COPY) + target_link_libraries(ggml-musa PRIVATE mudnn) + endif() endif() if (GGML_CUDA_NO_VMM) diff --git a/ggml/src/ggml-opencl/CMakeLists.txt b/ggml/src/ggml-opencl/CMakeLists.txt index ec5d8cf595..d8290faa46 100644 --- a/ggml/src/ggml-opencl/CMakeLists.txt +++ b/ggml/src/ggml-opencl/CMakeLists.txt @@ -55,6 +55,7 @@ endfunction() set(GGML_OPENCL_KERNELS add + add_id argsort clamp cpy @@ -82,6 +83,8 @@ set(GGML_OPENCL_KERNELS mul_mv_q4_0_f32_1d_16x_flat mul_mv_q6_k mul_mv_id_q4_0_f32_8x_flat + mul_mm_f32_f32_l4_lm + mul_mm_f16_f32_l4_lm mul norm relu @@ -105,6 +108,8 @@ set(GGML_OPENCL_KERNELS pad repeat mul_mat_f16_f32 + conv2d + conv2d_f16_f32 ) foreach (K ${GGML_OPENCL_KERNELS}) diff --git a/ggml/src/ggml-opencl/ggml-opencl.cpp b/ggml/src/ggml-opencl/ggml-opencl.cpp index 3388259152..fc838684ac 100644 --- a/ggml/src/ggml-opencl/ggml-opencl.cpp +++ b/ggml/src/ggml-opencl/ggml-opencl.cpp @@ -33,6 +33,7 @@ #undef MAX #define MIN(a, b) ((a) < (b) ? (a) : (b)) #define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define CEIL_DIV(M, N) (((M) + (N)-1) / (N)) #define UNUSED(x) (void)(x) @@ -333,6 +334,7 @@ struct ggml_backend_opencl_context { size_t max_alloc_size; bool fp16_support; bool has_vector_subgroup_broadcast; + bool disable_fusion; ggml_cl_compiler_version adreno_cl_compiler_version; int adreno_wave_size; @@ -343,6 +345,7 @@ struct ggml_backend_opencl_context { cl_command_queue queue; cl_program program_add; + cl_program program_add_id; cl_program program_clamp; cl_program program_cpy; cl_program program_cvt; @@ -390,13 +393,19 @@ struct ggml_backend_opencl_context { cl_program program_tanh; cl_program program_upscale; cl_program program_concat; + cl_program program_conv_2d_f16; + cl_program program_conv_2d_f32; + cl_program program_conv_2d_f16_f32; cl_program program_tsembd; cl_program program_mul_mv_id_q4_0_f32_8x_flat; + cl_program program_mul_mm_f32_f32_l4_lm; + cl_program program_mul_mm_f16_f32_l4_lm; - cl_kernel kernel_add, kernel_add_row; - cl_kernel kernel_mul, kernel_mul_row; - cl_kernel kernel_div, kernel_div_row; - cl_kernel kernel_sub, kernel_sub_row; + cl_kernel kernel_add, kernel_add_row, kernel_add_f16, kernel_add_row_f16; + cl_kernel kernel_mul, kernel_mul_row, kernel_mul_f16, kernel_mul_row_f16; + cl_kernel kernel_div, kernel_div_row, kernel_div_f16, kernel_div_row_f16; + cl_kernel kernel_sub, kernel_sub_row, kernel_sub_f16, kernel_sub_row_f16; + cl_kernel kernel_add_id; cl_kernel kernel_scale; cl_kernel kernel_silu, kernel_silu_4; cl_kernel kernel_gelu, kernel_gelu_4; @@ -405,10 +414,10 @@ struct ggml_backend_opencl_context { cl_kernel kernel_relu; cl_kernel kernel_sigmoid_f32, kernel_sigmoid_f16; cl_kernel kernel_clamp; - cl_kernel kernel_geglu, kernel_reglu, kernel_swiglu, kernel_geglu_erf, kernel_geglu_quick, + cl_kernel kernel_geglu, kernel_reglu, kernel_swiglu, kernel_swiglu_oai, kernel_geglu_erf, kernel_geglu_quick, kernel_geglu_f16, kernel_reglu_f16, kernel_swiglu_f16, kernel_geglu_erf_f16, kernel_geglu_quick_f16; cl_kernel kernel_norm; - cl_kernel kernel_rms_norm; + cl_kernel kernel_rms_norm, kernel_rms_norm_mul; cl_kernel kernel_group_norm; cl_kernel kernel_diag_mask_inf, kernel_diag_mask_inf_8; cl_kernel kernel_soft_max, kernel_soft_max_4; @@ -441,8 +450,13 @@ struct ggml_backend_opencl_context { cl_kernel kernel_upscale_bilinear; cl_kernel kernel_concat_f32_contiguous; cl_kernel kernel_concat_f32_non_contiguous; + cl_kernel kernel_conv_2d_f16; + cl_kernel kernel_conv_2d_f32; + cl_kernel kernel_conv_2d_f16_f32; cl_kernel kernel_timestep_embedding; cl_kernel kernel_mul_mv_id_q4_0_f32_8x_flat; + cl_kernel kernel_mul_mm_f32_f32_l4_lm; + cl_kernel kernel_mul_mm_f16_f32_l4_lm; std::vector profiling_info; @@ -588,6 +602,7 @@ struct ggml_backend_opencl_context { if (ref_count == 0) { #ifdef GGML_OPENCL_PROFILING write_profiling_info(); + profiling_info.clear(); #endif } } @@ -662,8 +677,26 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx, ggml_cl_ve backend_ctx->program_add = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_add = clCreateKernel(backend_ctx->program_add, "kernel_add", &err), err)); - CL_CHECK((backend_ctx->kernel_add_row = clCreateKernel(backend_ctx->program_add, "kernel_add_row", &err), err)); + CL_CHECK((backend_ctx->kernel_add = clCreateKernel(backend_ctx->program_add, "kernel_add", &err), err)); + CL_CHECK((backend_ctx->kernel_add_row = clCreateKernel(backend_ctx->program_add, "kernel_add_row", &err), err)); + CL_CHECK((backend_ctx->kernel_add_f16 = clCreateKernel(backend_ctx->program_add, "kernel_add_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_add_row_f16 = clCreateKernel(backend_ctx->program_add, "kernel_add_row_f16", &err), err)); + GGML_LOG_CONT("."); + } + + // add_id + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "add_id.cl.h" + }; +#else + const std::string kernel_src = read_file("add_id.cl"); +#endif + backend_ctx->program_add_id = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_add_id = clCreateKernel(backend_ctx->program_add_id, "kernel_add_id", &err), err)); GGML_LOG_CONT("."); } @@ -773,6 +806,7 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx, ggml_cl_ve CL_CHECK((backend_ctx->kernel_geglu = clCreateKernel(backend_ctx->program_glu, "kernel_geglu", &err), err)); CL_CHECK((backend_ctx->kernel_reglu = clCreateKernel(backend_ctx->program_glu, "kernel_reglu", &err), err)); CL_CHECK((backend_ctx->kernel_swiglu = clCreateKernel(backend_ctx->program_glu, "kernel_swiglu", &err), err)); + CL_CHECK((backend_ctx->kernel_swiglu_oai = clCreateKernel(backend_ctx->program_glu, "kernel_swiglu_oai", &err), err)); CL_CHECK((backend_ctx->kernel_geglu_erf = clCreateKernel(backend_ctx->program_glu, "kernel_geglu_erf", &err), err)); CL_CHECK((backend_ctx->kernel_geglu_quick = clCreateKernel(backend_ctx->program_glu, "kernel_geglu_quick", &err), err)); CL_CHECK((backend_ctx->kernel_geglu_f16 = clCreateKernel(backend_ctx->program_glu, "kernel_geglu_f16", &err), err)); @@ -1033,6 +1067,38 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx, ggml_cl_ve GGML_LOG_CONT("."); } + // mul_mm_f32_f32_l4_lm + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mm_f32_f32_l4_lm.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mm_f32_f32_l4_lm.cl"); +#endif + backend_ctx->program_mul_mm_f32_f32_l4_lm = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mm_f32_f32_l4_lm = clCreateKernel(backend_ctx->program_mul_mm_f32_f32_l4_lm, "kernel_mul_mm_f32_f32_l4_lm", &err), err)); + GGML_LOG_CONT("."); + } + + // mul_mm_f16_f32_l4_lm + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mm_f16_f32_l4_lm.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mm_f16_f32_l4_lm.cl"); +#endif + backend_ctx->program_mul_mm_f16_f32_l4_lm = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mm_f16_f32_l4_lm = clCreateKernel(backend_ctx->program_mul_mm_f16_f32_l4_lm, "kernel_mul_mm_f16_f32_l4_lm", &err), err)); + GGML_LOG_CONT("."); + } + // mul { #ifdef GGML_OPENCL_EMBED_KERNELS @@ -1045,8 +1111,10 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx, ggml_cl_ve backend_ctx->program_mul = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul = clCreateKernel(backend_ctx->program_mul, "kernel_mul", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_row = clCreateKernel(backend_ctx->program_mul, "kernel_mul_row", &err), err)); + CL_CHECK((backend_ctx->kernel_mul = clCreateKernel(backend_ctx->program_mul, "kernel_mul", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_row = clCreateKernel(backend_ctx->program_mul, "kernel_mul_row", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_f16 = clCreateKernel(backend_ctx->program_mul, "kernel_mul_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_row_f16 = clCreateKernel(backend_ctx->program_mul, "kernel_mul_row_f16", &err), err)); GGML_LOG_CONT("."); } @@ -1094,7 +1162,8 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx, ggml_cl_ve backend_ctx->program_rms_norm = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_rms_norm = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm", &err), err)); + CL_CHECK((backend_ctx->kernel_rms_norm = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm", &err), err)); + CL_CHECK((backend_ctx->kernel_rms_norm_mul = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm_mul", &err), err)); GGML_LOG_CONT("."); } @@ -1243,11 +1312,16 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx, ggml_cl_ve #else const std::string kernel_src = read_file("div.cl"); #endif + std::string compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable -cl-finite-math-only "; + backend_ctx->program_div = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_div = clCreateKernel(backend_ctx->program_div, "kernel_div", &err), err)); - CL_CHECK((backend_ctx->kernel_div_row = clCreateKernel(backend_ctx->program_div, "kernel_div_row", &err), err)); + CL_CHECK((backend_ctx->kernel_div = clCreateKernel(backend_ctx->program_div, "kernel_div", &err), err)); + CL_CHECK((backend_ctx->kernel_div_row = clCreateKernel(backend_ctx->program_div, "kernel_div_row", &err), err)); + CL_CHECK((backend_ctx->kernel_div_f16 = clCreateKernel(backend_ctx->program_div, "kernel_div_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_div_row_f16 = clCreateKernel(backend_ctx->program_div, "kernel_div_row_f16", &err), err)); GGML_LOG_CONT("."); } @@ -1263,8 +1337,10 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx, ggml_cl_ve backend_ctx->program_sub = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_sub = clCreateKernel(backend_ctx->program_sub, "kernel_sub", &err), err)); - CL_CHECK((backend_ctx->kernel_sub_row = clCreateKernel(backend_ctx->program_sub, "kernel_sub_row", &err), err)); + CL_CHECK((backend_ctx->kernel_sub = clCreateKernel(backend_ctx->program_sub, "kernel_sub", &err), err)); + CL_CHECK((backend_ctx->kernel_sub_row = clCreateKernel(backend_ctx->program_sub, "kernel_sub_row", &err), err)); + CL_CHECK((backend_ctx->kernel_sub_f16 = clCreateKernel(backend_ctx->program_sub, "kernel_sub_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_sub_row_f16 = clCreateKernel(backend_ctx->program_sub, "kernel_sub_row_f16", &err), err)); GGML_LOG_CONT("."); } @@ -1478,6 +1554,47 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx, ggml_cl_ve GGML_LOG_CONT("."); } + // conv2d + { + #ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "conv2d.cl.h" + }; + const std::string kernel_src_f16_f32 { + #include "conv2d_f16_f32.cl.h" + }; + #else + const std::string kernel_src = read_file("conv2d.cl"); + const std::string kernel_src_f16_f32 = read_file("conv2d_f16_f32.cl"); + #endif + if (!kernel_src.empty()) { + backend_ctx->program_conv_2d_f16 = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), (std::string(compile_opts) + " -DUSE_FP16=1").c_str()); + CL_CHECK((backend_ctx->kernel_conv_2d_f16 = clCreateKernel(backend_ctx->program_conv_2d_f16, "kernel_conv_2d", &err), err)); + GGML_LOG_CONT("."); + backend_ctx->program_conv_2d_f32 = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_conv_2d_f32 = clCreateKernel(backend_ctx->program_conv_2d_f32, "kernel_conv_2d", &err), err)); + GGML_LOG_CONT("."); + } else { + GGML_LOG_WARN("ggml_opencl: conv2d kernel source not found or empty. This op will not be available.\n"); + backend_ctx->program_conv_2d_f16 = nullptr; + backend_ctx->kernel_conv_2d_f16 = nullptr; + backend_ctx->program_conv_2d_f32 = nullptr; + backend_ctx->kernel_conv_2d_f32 = nullptr; + } + if (!kernel_src_f16_f32.empty()) { + backend_ctx->program_conv_2d_f16_f32 = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src_f16_f32.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_conv_2d_f16_f32 = clCreateKernel(backend_ctx->program_conv_2d_f16_f32, "kernel_conv_2d", &err), err)); + GGML_LOG_CONT("."); + } else { + GGML_LOG_WARN("ggml_opencl: conv2d_f16_f32 kernel source not found or empty. This op will not be available.\n"); + backend_ctx->program_conv_2d_f16_f32 = nullptr; + backend_ctx->kernel_conv_2d_f16_f32 = nullptr; + } + } + // mul_mv_id_q4_0_f32_8x_flat { #ifdef GGML_OPENCL_EMBED_KERNELS @@ -1949,8 +2066,8 @@ static ggml_backend_opencl_context * ggml_cl2_init(ggml_backend_dev_t dev) { backend_ctx->adreno_cl_compiler_version = get_adreno_cl_compiler_version(driver_version); backend_ctx->has_vector_subgroup_broadcast = - backend_ctx->adreno_cl_compiler_version.major >= 47 || - backend_ctx->adreno_cl_compiler_version.major == 17; + (backend_ctx->adreno_cl_compiler_version.type == E031 && backend_ctx->adreno_cl_compiler_version.major >= 47) || + (backend_ctx->adreno_cl_compiler_version.type == DX && backend_ctx->adreno_cl_compiler_version.major >= 17); GGML_LOG_INFO("ggml_opencl: vector subgroup broadcast support: %s\n", backend_ctx->has_vector_subgroup_broadcast ? "true" : "false"); @@ -2063,6 +2180,8 @@ static ggml_backend_opencl_context * ggml_cl2_init(ggml_backend_dev_t dev) { CL_CHECK((backend_ctx->B_d_max = clCreateBuffer(context, 0, max_B_d_bytes, NULL, &err), err)); #endif // GGML_OPENCL_USE_ADRENO_KERNELS + backend_ctx->disable_fusion = getenv("GGML_OPENCL_DISABLE_FUSION") != nullptr; + dev_ctx->backend_ctx = backend_ctx.release(); return dev_ctx->backend_ctx; } @@ -2232,7 +2351,45 @@ static void sync_with_other_backends(ggml_backend_t backend) { sync_with_other_backends(backend_ctx); } +static bool ggml_opencl_can_fuse(const struct ggml_cgraph * cgraph, int node_idx, std::initializer_list ops) { + if (!ggml_can_fuse(cgraph, node_idx, ops)) { + return false; + } + + if (ops.size() == 2 && ops.begin()[0] == GGML_OP_RMS_NORM && ops.begin()[1] == GGML_OP_MUL) { + const ggml_tensor *rms_norm = cgraph->nodes[node_idx]; + const ggml_tensor *mul = cgraph->nodes[node_idx+1]; + + GGML_ASSERT(rms_norm->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(rms_norm->type == GGML_TYPE_F32); + + // rms_norm only supports f32 + if (mul->src[0]->type != GGML_TYPE_F32 || + mul->src[1]->type != GGML_TYPE_F32 || + mul->type != GGML_TYPE_F32) { + return false; + } + + // if rms_norm is the B operand, then we don't handle broadcast + if (rms_norm == mul->src[1] && + !ggml_are_same_shape(mul->src[0], rms_norm->src[1])) { + return false; + } + + // rms_norm assumes contiguous rows + if (!ggml_is_contiguous_rows(mul->src[0]) || !ggml_is_contiguous_rows(mul->src[1])) { + return false; + } + } + + return true; +} + +static void ggml_opencl_op_rms_norm_fused(ggml_backend_t backend, ggml_tensor * rms_norm_tensor, ggml_tensor * mul_tensor); + static ggml_status ggml_backend_opencl_graph_compute(ggml_backend_t backend, ggml_cgraph * cgraph) { + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + for (int i = 0; i < cgraph->n_nodes; i++) { ggml_tensor * node = cgraph->nodes[i]; @@ -2245,6 +2402,12 @@ static ggml_status ggml_backend_opencl_graph_compute(ggml_backend_t backend, ggm continue; } + if (!backend_ctx->disable_fusion && ggml_opencl_can_fuse(cgraph, i, { GGML_OP_RMS_NORM, GGML_OP_MUL })) { + ggml_opencl_op_rms_norm_fused(backend, node, cgraph->nodes[i+1]); + i++; + continue; + } + bool ok = ggml_cl_compute_forward(backend, node); if (!ok) { GGML_LOG_ERROR("%s: error: op not supported %s (%s)\n", __func__, node->name, ggml_op_name(node->op)); @@ -2315,11 +2478,23 @@ static bool ggml_opencl_supports_op(ggml_backend_dev_t dev, const struct ggml_te default: return false; } - case GGML_OP_ADD: case GGML_OP_SCALE: + return op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]); + case GGML_OP_ADD: + if (op->type == GGML_TYPE_F16) { + const bool src0_ok = op->src[0]->type == GGML_TYPE_F16 || op->src[0]->type == GGML_TYPE_F32; + const bool src1_ok = op->src[1]->type == GGML_TYPE_F16 || op->src[1]->type == GGML_TYPE_F32; + if (src0_ok && src1_ok) { + return true; + } + } case GGML_OP_MUL: case GGML_OP_DIV: case GGML_OP_SUB: + return (op->src[0]->type == op->src[1]->type) && + (op->src[0]->type == op->type) && + (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16); + case GGML_OP_ADD_ID: return op->src[0]->type == GGML_TYPE_F32; case GGML_OP_UNARY: switch (ggml_get_unary_op(op)) { @@ -2342,6 +2517,7 @@ static bool ggml_opencl_supports_op(ggml_backend_dev_t dev, const struct ggml_te case GGML_GLU_OP_GEGLU: case GGML_GLU_OP_REGLU: case GGML_GLU_OP_SWIGLU: + case GGML_GLU_OP_SWIGLU_OAI: case GGML_GLU_OP_GEGLU_ERF: case GGML_GLU_OP_GEGLU_QUICK: return ggml_is_contiguous_1(op->src[0]) && (op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_F16); @@ -2361,6 +2537,10 @@ static bool ggml_opencl_supports_op(ggml_backend_dev_t dev, const struct ggml_te op->src[0]->ne[3] == 1 && op->ne[3] == 1; case GGML_OP_UPSCALE: return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; + case GGML_OP_CONV_2D: + return (op->src[0]->type == GGML_TYPE_F16 && op->src[1]->type == GGML_TYPE_F16 && op->type == GGML_TYPE_F16) || + (op->src[0]->type == GGML_TYPE_F32 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32) || + (op->src[0]->type == GGML_TYPE_F16 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32); case GGML_OP_CONCAT: return op->src[0]->type == GGML_TYPE_F32 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; case GGML_OP_TIMESTEP_EMBEDDING: @@ -2451,10 +2631,10 @@ ggml_backend_t ggml_backend_opencl_init(void) { ggml_backend_opencl_context *backend_ctx = ggml_cl2_init(dev); ggml_backend_t backend = new ggml_backend { - /* .guid = */ ggml_backend_opencl_guid(), - /* .interface = */ ggml_backend_opencl_i, - /* .device = */ dev, - /* .context = */ backend_ctx + /* .guid = */ ggml_backend_opencl_guid(), + /* .iface = */ ggml_backend_opencl_i, + /* .device = */ dev, + /* .context = */ backend_ctx }; return backend; @@ -3544,35 +3724,35 @@ static void ggml_cl_add(ggml_backend_t backend, const ggml_tensor * src0, const GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - const int ne00 = src0 ? src0->ne[0] : 0; - const int ne01 = src0 ? src0->ne[1] : 0; - const int ne02 = src0 ? src0->ne[2] : 0; - const int ne03 = src0 ? src0->ne[3] : 0; + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; - const cl_ulong nb00 = src0 ? src0->nb[0] : 0; - const cl_ulong nb01 = src0 ? src0->nb[1] : 0; - const cl_ulong nb02 = src0 ? src0->nb[2] : 0; - const cl_ulong nb03 = src0 ? src0->nb[3] : 0; + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - const int ne10 = src1 ? src1->ne[0] : 0; - const int ne11 = src1 ? src1->ne[1] : 0; - const int ne12 = src1 ? src1->ne[2] : 0; - const int ne13 = src1 ? src1->ne[3] : 0; UNUSED(ne13); + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int ne13 = src1->ne[3]; - const cl_ulong nb10 = src1 ? src1->nb[0] : 0; - const cl_ulong nb11 = src1 ? src1->nb[1] : 0; - const cl_ulong nb12 = src1 ? src1->nb[2] : 0; - const cl_ulong nb13 = src1 ? src1->nb[3] : 0; UNUSED(nb13); + const cl_ulong nb10 = src1->nb[0]; + const cl_ulong nb11 = src1->nb[1]; + const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; - const int ne0 = dst ? dst->ne[0] : 0; - const int ne1 = dst ? dst->ne[1] : 0; - const int ne2 = dst ? dst->ne[2] : 0; - const int ne3 = dst ? dst->ne[3] : 0; + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + const int ne2 = dst->ne[2]; + const int ne3 = dst->ne[3]; - const cl_ulong nb0 = dst ? dst->nb[0] : 0; - const cl_ulong nb1 = dst ? dst->nb[1] : 0; - const cl_ulong nb2 = dst ? dst->nb[2] : 0; - const cl_ulong nb3 = dst ? dst->nb[3] : 0; + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; @@ -3584,59 +3764,114 @@ static void ggml_cl_add(ggml_backend_t backend, const ggml_tensor * src0, const cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - bool bcast_row = false; cl_kernel kernel; - if (ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0) { + const bool bcast_row = ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0; + + if (bcast_row) { GGML_ASSERT(ggml_is_contiguous(src0)); - - // src1 is a row GGML_ASSERT(ne11 == 1); + } - bcast_row = true; - int ne = ne00 / 4; - kernel = backend_ctx->kernel_add_row; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + if (dst->type == GGML_TYPE_F32) { + GGML_ASSERT(src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32); + if (bcast_row) { + kernel = backend_ctx->kernel_add_row; + const int ne = ne00 / 4; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + } else { + kernel = backend_ctx->kernel_add; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); + } + } else if (dst->type == GGML_TYPE_F16) { + GGML_ASSERT(src0->type == GGML_TYPE_F16 || src0->type == GGML_TYPE_F32); + GGML_ASSERT(src1->type == GGML_TYPE_F16 || src1->type == GGML_TYPE_F32); + const int type_src0 = (src0->type == GGML_TYPE_F32); + const int type_src1 = (src1->type == GGML_TYPE_F32); + if (bcast_row) { + kernel = backend_ctx->kernel_add_row_f16; + const int ne = ne00 / 4; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &type_src0)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &type_src1)); + } else { + kernel = backend_ctx->kernel_add_f16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 30, sizeof(int), &type_src0)); + CL_CHECK(clSetKernelArg(kernel, 31, sizeof(int), &type_src1)); + } } else { - kernel = backend_ctx->kernel_add; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); - CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); - CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); + GGML_ASSERT(false && "unsupported data types for add"); } if (bcast_row) { @@ -3646,19 +3881,88 @@ static void ggml_cl_add(ggml_backend_t backend, const ggml_tensor * src0, const size_t * local_work_size_ptr = local_work_size; if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. + local_work_size_ptr = nullptr; } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 1, global_work_size, local_work_size_ptr, dst); } else { unsigned int nth = MIN(64, ne0); - size_t global_work_size[] = {ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; size_t local_work_size[] = {nth, 1, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } } +static void ggml_cl_add_id(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + + const ggml_tensor * src2 = dst->src[2]; + GGML_ASSERT(src2); + GGML_ASSERT(src2->extra); + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT(src2->type == GGML_TYPE_I32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); + + GGML_ASSERT(ggml_is_contiguous_rows(src0)); + + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + + const cl_ulong nb11 = src1->nb[1]; + + const cl_ulong nb21 = src2->nb[1]; + + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offset2 = extra2->offset + src2->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + cl_kernel kernel = backend_ctx->kernel_add_id; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne1)); + + int nth = MIN(ne00, (int) backend_ctx->get_kernel_workgroup_size(kernel)); + size_t global_work_size[] = { (size_t)ne01*nth, (size_t)ne02, 1 }; + size_t local_work_size[] = { (size_t)nth, 1, 1 }; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} + static void ggml_cl_mul(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -3667,35 +3971,39 @@ static void ggml_cl_mul(ggml_backend_t backend, const ggml_tensor * src0, const GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - const int ne00 = src0 ? src0->ne[0] : 0; - const int ne01 = src0 ? src0->ne[1] : 0; - const int ne02 = src0 ? src0->ne[2] : 0; - const int ne03 = src0 ? src0->ne[3] : 0; + GGML_ASSERT(src0->type == src1->type); + GGML_ASSERT(src0->type == dst->type); + GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); - const cl_ulong nb00 = src0 ? src0->nb[0] : 0; - const cl_ulong nb01 = src0 ? src0->nb[1] : 0; - const cl_ulong nb02 = src0 ? src0->nb[2] : 0; - const cl_ulong nb03 = src0 ? src0->nb[3] : 0; + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; - const int ne10 = src1 ? src1->ne[0] : 0; - const int ne11 = src1 ? src1->ne[1] : 0; - const int ne12 = src1 ? src1->ne[2] : 0; - const int ne13 = src1 ? src1->ne[3] : 0; UNUSED(ne13); + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - const cl_ulong nb10 = src1 ? src1->nb[0] : 0; - const cl_ulong nb11 = src1 ? src1->nb[1] : 0; - const cl_ulong nb12 = src1 ? src1->nb[2] : 0; - const cl_ulong nb13 = src1 ? src1->nb[3] : 0; UNUSED(nb13); + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int ne13 = src1->ne[3]; UNUSED(ne13); - const int ne0 = dst ? dst->ne[0] : 0; - const int ne1 = dst ? dst->ne[1] : 0; - const int ne2 = dst ? dst->ne[2] : 0; - const int ne3 = dst ? dst->ne[3] : 0; + const cl_ulong nb10 = src1->nb[0]; + const cl_ulong nb11 = src1->nb[1]; + const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; UNUSED(nb13); - const cl_ulong nb0 = dst ? dst->nb[0] : 0; - const cl_ulong nb1 = dst ? dst->nb[1] : 0; - const cl_ulong nb2 = dst ? dst->nb[2] : 0; - const cl_ulong nb3 = dst ? dst->nb[3] : 0; + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + const int ne2 = dst->ne[2]; + const int ne3 = dst->ne[3]; + + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; @@ -3718,7 +4026,12 @@ static void ggml_cl_mul(ggml_backend_t backend, const ggml_tensor * src0, const bcast_row = true; int ne = ne00 / 4; - kernel = backend_ctx->kernel_mul_row; + + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_mul_row; + } else { + kernel = backend_ctx->kernel_mul_row_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -3728,7 +4041,11 @@ static void ggml_cl_mul(ggml_backend_t backend, const ggml_tensor * src0, const CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); } else { - kernel = backend_ctx->kernel_mul; + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_mul; + } else { + kernel = backend_ctx->kernel_mul_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -3790,6 +4107,10 @@ static void ggml_cl_div(ggml_backend_t backend, const ggml_tensor * src0, const GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + GGML_ASSERT(src0->type == src1->type); + GGML_ASSERT(src0->type == dst->type); + GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); + const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; const int ne02 = src0->ne[2]; @@ -3838,7 +4159,12 @@ static void ggml_cl_div(ggml_backend_t backend, const ggml_tensor * src0, const bcast_row = true; int ne = ne00 / 4; - kernel = backend_ctx->kernel_div_row; + + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_div_row; + } else { + kernel = backend_ctx->kernel_div_row_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -3848,7 +4174,11 @@ static void ggml_cl_div(ggml_backend_t backend, const ggml_tensor * src0, const CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); } else { - kernel = backend_ctx->kernel_div; + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_div; + } else { + kernel = backend_ctx->kernel_div_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -3898,6 +4228,10 @@ static void ggml_cl_sub(ggml_backend_t backend, const ggml_tensor * src0, const GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + GGML_ASSERT(src0->type == src1->type); + GGML_ASSERT(src0->type == dst->type); + GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); + const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; const int ne02 = src0->ne[2]; @@ -3946,7 +4280,12 @@ static void ggml_cl_sub(ggml_backend_t backend, const ggml_tensor * src0, const bcast_row = true; int ne = ne00 / 4; - kernel = backend_ctx->kernel_sub_row; + + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_sub_row; + } else { + kernel = backend_ctx->kernel_sub_row_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -3956,7 +4295,11 @@ static void ggml_cl_sub(ggml_backend_t backend, const ggml_tensor * src0, const CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); } else { - kernel = backend_ctx->kernel_sub; + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_sub; + } else { + kernel = backend_ctx->kernel_sub_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -4404,6 +4747,117 @@ static void ggml_cl_rms_norm(ggml_backend_t backend, const ggml_tensor * src0, c backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } +static void ggml_opencl_op_rms_norm_fused(ggml_backend_t backend, ggml_tensor * rms_norm_tensor, ggml_tensor * mul_tensor) { + GGML_ASSERT(mul_tensor); + GGML_ASSERT(rms_norm_tensor); + + // src0 is the src of rms_norm, src1 is the other src of mul (one being rms_norm) + const ggml_tensor * src0 = rms_norm_tensor->src[0]; + const ggml_tensor * src1; + if (mul_tensor->src[0] == rms_norm_tensor) { + src1 = mul_tensor->src[1]; + } else if (mul_tensor->src[1] == rms_norm_tensor) { + src1 = mul_tensor->src[0]; + } else { + GGML_ASSERT(false && "Invalid args for rms_norm and mul"); + } + const ggml_tensor * dst = mul_tensor; + + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src0->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + float eps; + memcpy(&eps, rms_norm_tensor->op_params, sizeof(float)); + + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; + + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; + + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int ne13 = src1->ne[3]; + + const cl_ulong nb11 = src1->nb[1]; + const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; + + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; + + GGML_ASSERT(ne00 % 4 == 0); + + size_t sgs; + if (backend_ctx->gpu_family == ADRENO) { + sgs = 64; + } else if (backend_ctx->gpu_family == INTEL) { + sgs = 32; + } else { + GGML_ASSERT(false && "Unsupported GPU"); + } + + cl_kernel kernel = backend_ctx->kernel_rms_norm_mul; + + int nth = sgs; + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + while (nth < ne00 && nth < max_workgroup_size) { + nth *= 2; + } + nth = MIN(nth, max_workgroup_size); + nth = MIN(nth, ne00); + + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(float), &eps)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(float)*nth/sgs, NULL)); + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} + static void ggml_cl_group_norm(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -4998,6 +5452,82 @@ static void ggml_cl_mul_mat_f16_f32_tiled(ggml_backend_t backend, const ggml_ten backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); } +static void ggml_cl_conv_2d(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_TENSOR_BINARY_OP_LOCALS; + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + const cl_uint Cout = ne03; const cl_uint Cin = ne02; const cl_uint N = ne13; + const cl_uint KW = ne00; const cl_uint KH = ne01; const cl_uint W = ne10; const cl_uint H = ne11; const cl_uint OW = ne0; const cl_uint OH = ne1; + + const cl_uint s0 = dst->op_params[0]; const cl_uint s1 = dst->op_params[1]; + const cl_uint p0 = dst->op_params[2]; const cl_uint p1 = dst->op_params[3]; + const cl_uint d0 = dst->op_params[4]; const cl_uint d1 = dst->op_params[5]; + + const cl_uint cl_nb01 = nb01/ggml_type_size(src0->type); const cl_uint cl_nb02 = nb02/ggml_type_size(src0->type); const cl_uint cl_nb03 = nb03/ggml_type_size(src0->type); + const cl_uint cl_nb11 = nb11/ggml_type_size(src1->type); const cl_uint cl_nb12 = nb12/ggml_type_size(src1->type); const cl_uint cl_nb13 = nb13/ggml_type_size(src1->type); + const cl_uint cl_nb1 = nb1/ggml_type_size(dst->type); const cl_uint cl_nb2 = nb2/ggml_type_size(dst->type); const cl_uint cl_nb3 = nb3/ggml_type_size(dst->type); + + const int64_t NPQ = (int64_t)N * OW * OH; + + const uint32_t BS_K = 64; + const uint32_t BS_NPQ = 64; + const uint32_t BS_CRS = 16; + const uint32_t VEC_SIZE = 4; + + const uint32_t TS_K = 4; + const uint32_t TS_NPQ = 8; + + const uint32_t WG_K = BS_K / TS_K; + const uint32_t WG_NPQ = BS_NPQ / TS_NPQ; + + auto splitWork = [](uint32_t work_size, uint32_t block_size) { return (block_size + work_size - 1) / block_size; }; + const uint32_t NB_K = splitWork(Cout, BS_K); + const uint32_t NB_NPQ = splitWork(NPQ, BS_NPQ); + + cl_kernel kernel; + size_t shmem_size; + + if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F16) { + kernel = backend_ctx->kernel_conv_2d_f16; + shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_half) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_half4)); + } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_conv_2d_f32; + shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_float) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_float4)); + } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_conv_2d_f16_f32; + shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_half) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_float4)); + } else { + GGML_ASSERT(false && "Unsupported data type combination for conv2d"); + } + + cl_uint idx = 0; + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extra1->data_device)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extrad->data_device)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, idx++, shmem_size, NULL)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &Cout)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &Cin)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &N)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &KW)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &KH)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &W)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &H)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &OW)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &OH)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &s0)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &s1)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &p0)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &p1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &d0)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &d1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb01)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb02)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb03)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb11)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb12)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb13)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb1)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb2)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb3)); + + size_t global_work_size[] = { (size_t)NB_K * WG_K, (size_t)NB_NPQ * WG_NPQ, 1 }; + size_t local_work_size[] = { (size_t)WG_K, (size_t)WG_NPQ, 1 }; + + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); +} + static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -5011,18 +5541,6 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - if (src0t == GGML_TYPE_F16 && src1t == GGML_TYPE_F32 && - src0->ne[1] > 32 && // M > 32 - src1->ne[1] > 32 && // N > 32 - src0->ne[0] > 32 && // K > 32 - src0->ne[2] == 1 && src0->ne[3] == 1 && - src1->ne[2] == 1 && src1->ne[3] == 1 && - ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && - backend_ctx->kernel_mul_mat_f16_f32_tiled != NULL) { - ggml_cl_mul_mat_f16_f32_tiled(backend, src0, src1, dst); - return; - } - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; @@ -5369,6 +5887,101 @@ static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, co } // if (ne01 && ne1) #endif // GGML_OPENCL_USE_ADRENO_KERNELS + // GEMM using local memory + // Current BK = 16, so ne00 % 16 == 0 + if (ggml_is_contiguous(src0) && + ggml_is_contiguous(src1) && + src1t == GGML_TYPE_F32 && + ne00 % 16 == 0 && + ne11 > 1) { + switch(src0t) { + case GGML_TYPE_F32: { + kernel = backend_ctx->kernel_mul_mm_f32_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); + + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + case GGML_TYPE_F16: { + kernel = backend_ctx->kernel_mul_mm_f16_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); + + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + default: + break; + } + } + + if (src0t == GGML_TYPE_F16 && src1t == GGML_TYPE_F32 && + src0->ne[1] > 32 && // M > 32 + src1->ne[1] > 32 && // N > 32 + src0->ne[0] > 32 && // K > 32 + src0->ne[2] == 1 && src0->ne[3] == 1 && + src1->ne[2] == 1 && src1->ne[3] == 1 && + ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && + backend_ctx->kernel_mul_mat_f16_f32_tiled != NULL) { + ggml_cl_mul_mat_f16_f32_tiled(backend, src0, src1, dst); + return; + } + if (!ggml_is_transposed(src0) && !ggml_is_transposed(src1) && src1t == GGML_TYPE_F32 && @@ -6028,17 +6641,24 @@ static void ggml_cl_soft_max(ggml_backend_t backend, const ggml_tensor * src0, c GGML_ASSERT(src1->extra); } + const ggml_tensor * src2 = dst->src[2]; + if (src2) { + GGML_ASSERT(src2->extra); + } + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; ggml_tensor_extra_cl * extra1 = src1 ? (ggml_tensor_extra_cl *)src1->extra : nullptr; + ggml_tensor_extra_cl * extra2 = src2 ? (ggml_tensor_extra_cl *)src2->extra : nullptr; cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; cl_ulong offset1 = extra1 ? extra1->offset + src1->view_offs : offset0; + cl_ulong offset2 = extra2 ? extra2->offset + src2->view_offs : offset0; const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; @@ -6106,25 +6726,27 @@ static void ggml_cl_soft_max(ggml_backend_t backend, const ggml_tensor * src0, c CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), extra1 ? &extra1->data_device : &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb3)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(float), &scale)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(float), &max_bias)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(float), &m0)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(float), &m1)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &n_head_log2)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), extra2 ? &extra2->data_device : &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(float), &scale)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(float), &max_bias)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(float), &m0)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(float), &m1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &n_head_log2)); size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; size_t local_work_size[] = {(size_t)nth, 1, 1}; @@ -6531,6 +7153,9 @@ static void ggml_cl_glu(ggml_backend_t backend, const ggml_tensor * src0, const kernel = backend_ctx->kernel_swiglu_f16; } break; + case GGML_GLU_OP_SWIGLU_OAI: + kernel = backend_ctx->kernel_swiglu_oai; + break; case GGML_GLU_OP_GEGLU_ERF: if (dst->type == GGML_TYPE_F32) { kernel = backend_ctx->kernel_geglu_erf; @@ -6566,7 +7191,10 @@ static void ggml_cl_glu(ggml_backend_t backend, const ggml_tensor * src0, const const cl_ulong nb1 = dst->nb[1]; - const int swp = ((const int32_t *) dst->op_params)[1]; + const int swp = ggml_get_op_params_i32(dst, 1); + const float alpha = ggml_get_op_params_f32(dst, 2); + const float limit = ggml_get_op_params_f32(dst, 3); + const int ne00_off = src1 ? 0 : (swp ? ne0 : 0); const int ne10_off = src1 ? 0 : (swp ? 0 : ne0); @@ -6583,6 +7211,11 @@ static void ggml_cl_glu(ggml_backend_t backend, const ggml_tensor * src0, const CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne00_off)); CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10_off)); + if (ggml_get_glu_op(dst) == GGML_GLU_OP_SWIGLU_OAI) { + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(float), &limit)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(float), &alpha)); + } + const size_t nrows = ggml_nrows(src0); size_t nth = 512; size_t global_work_size[] = {nrows*nth, 1, 1}; @@ -6639,6 +7272,12 @@ bool ggml_cl_compute_forward(ggml_backend_t backend, struct ggml_tensor * tensor } func = ggml_cl_add; break; + case GGML_OP_ADD_ID: + if (!any_on_device) { + return false; + } + func = ggml_cl_add_id; + break; case GGML_OP_MUL: if (!any_on_device) { return false; @@ -6752,6 +7391,12 @@ bool ggml_cl_compute_forward(ggml_backend_t backend, struct ggml_tensor * tensor } ggml_cl_upscale(backend, tensor->src[0], tensor); return true; + case GGML_OP_CONV_2D: + if (!any_on_device) { + return false; + } + func = ggml_cl_conv_2d; + break; case GGML_OP_CONCAT: if (!any_on_device) { return false; diff --git a/ggml/src/ggml-opencl/kernels/add.cl b/ggml/src/ggml-opencl/kernels/add.cl index f73f3c0134..509bf17344 100644 --- a/ggml/src/ggml-opencl/kernels/add.cl +++ b/ggml/src/ggml-opencl/kernels/add.cl @@ -81,3 +81,110 @@ kernel void kernel_add_row( uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne dst[gid] = src0[gid] + src1[idx1]; } + +kernel void kernel_add_f16( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + int ne02, + int ne03, + ulong nb00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne10, + int ne11, + int ne12, + int ne13, + ulong nb10, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int ne2, + int ne3, + ulong nb0, + ulong nb1, + ulong nb2, + ulong nb3, + int type_src0, + int type_src1 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0); + + int i13 = i03 % ne13; + int i12 = i02 % ne12; + int i11 = i01 % ne11; + + global char * src0_ptr = src0 + i03*nb03 + i02*nb02 + i01*nb01; + global char * src1_ptr = src1 + i13*nb13 + i12*nb12 + i11*nb11; + global char * dst_ptr = dst + i03*nb3 + i02*nb2 + i01*nb1; + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + const int i10 = i0 % ne10; + + half v0, v1; + if (type_src0 == 1) { + v0 = convert_half(*((global float *)(src0_ptr + i0*nb00))); + } else { + v0 = *((global half *)(src0_ptr + i0*nb00)); + } + + if (type_src1 == 1) { + v1 = convert_half(*((global float *)(src1_ptr + i10*nb10))); + } else { + v1 = *((global half *)(src1_ptr + i10*nb10)); + } + + *((global half *)(dst_ptr + i0*nb0)) = v0 + v1; + } +} + +kernel void kernel_add_row_f16( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global half4 * dst, + ulong offsetd, + int ne, + int type_src0, + int type_src1 +) { + dst = (global half4*)((global char*)dst + offsetd); + + // This performs better than using %. + uint gid = get_global_id(0); + uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne + + half4 v0, v1; + if (type_src0 == 1) { + global float4* src0_f32 = (global float4*)((global char*)src0 + offset0); + v0 = convert_half4(src0_f32[gid]); + } else { + global half4* src0_f16 = (global half4*)((global char*)src0 + offset0); + v0 = src0_f16[gid]; + } + + if (type_src1 == 1) { + global float4* src1_f32 = (global float4*)((global char*)src1 + offset1); + v1 = convert_half4(src1_f32[idx1]); + } else { + global half4* src1_f16 = (global half4*)((global char*)src1 + offset1); + v1 = src1_f16[idx1]; + } + + dst[gid] = v0 + v1; +} diff --git a/ggml/src/ggml-opencl/kernels/add_id.cl b/ggml/src/ggml-opencl/kernels/add_id.cl new file mode 100644 index 0000000000..e9c6d55e6a --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/add_id.cl @@ -0,0 +1,42 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +//------------------------------------------------------------------------------ +// add_id +//------------------------------------------------------------------------------ +kernel void kernel_add_id( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * src2, + ulong offset2, + global char * dst, + ulong offsetd, + ulong nb01, + ulong nb02, + ulong nb11, + ulong nb21, + int ne0, + int ne1 +) { + src0 = (global char*)((global char*)src0 + offset0); + src1 = (global char*)((global char*)src1 + offset1); + src2 = (global char*)((global char*)src2 + offset2); + dst = (global char*)((global char*)dst + offsetd); + + int i1 = get_group_id(0); + int i2 = get_group_id(1); + + const int i11 = *((global const int *) (src2 + i1*sizeof(int) + i2*nb21)); + + const size_t nb1 = ne0 * sizeof(float); + const size_t nb2 = ne1 * nb1; + + global float * dst_row = (global float *)((global char *)dst + i1*nb1 + i2*nb2); + global float * src0_row = (global float *)((global char *)src0 + i1*nb01 + i2*nb02); + global float * src1_row = (global float *)((global char *)src1 + i11*nb11); + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + dst_row[i0] = src0_row[i0] + src1_row[i0]; + } +} diff --git a/ggml/src/ggml-opencl/kernels/conv2d.cl b/ggml/src/ggml-opencl/kernels/conv2d.cl new file mode 100644 index 0000000000..e339c90cff --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/conv2d.cl @@ -0,0 +1,185 @@ +#ifdef USE_FP16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#define T_FLOAT half +#define T_FLOAT4 half4 +#define VSTORE_T_FLOAT4(data, offset, p) vstore_half4_rte(data, offset, p) +#else +#define T_FLOAT float +#define T_FLOAT4 float4 +#define VSTORE_T_FLOAT4(data, offset, p) vstore4(data, offset, p) +#endif + +#if defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#else +#define REQD_SUBGROUP_SIZE_128 +#endif + +#define T_ACCUM float4 +#define VEC_SIZE 4 + +#define BS_K 64 +#define BS_NPQ 64 +#define BS_CRS 16 + +#define TS_K 4 +#define TS_NPQ 8 + +#define WG_K (BS_K / TS_K) +#define WG_NPQ (BS_NPQ / TS_NPQ) + +#define BS_NPQ_VEC (BS_NPQ / VEC_SIZE) +#define TS_NPQ_VEC (TS_NPQ / VEC_SIZE) + +static inline uint splitWork(uint work_size, uint block_size){ + return (work_size + block_size - 1) / block_size; +} + +REQD_SUBGROUP_SIZE_128 +kernel void kernel_conv_2d( + global void* p_knl, + ulong off_knl, + global void* p_src, + ulong off_src, + global void* p_dst, + ulong off_dst, + local void* shared, + uint Cout, uint Cin, uint N, + uint KW, uint KH, uint W, uint H, uint OW, uint OH, + uint s0, uint s1, uint p0, uint p1, uint d0, uint d1, + uint nb01, uint nb02, uint nb03, + uint nb11, uint nb12, uint nb13, + uint nb1, uint nb2, uint nb3 +) { + global T_FLOAT* knl_data = (global T_FLOAT*) ((global char*)p_knl + off_knl); + global T_FLOAT* src_data = (global T_FLOAT*) ((global char*)p_src + off_src); + global T_FLOAT* dst_data = (global T_FLOAT*) ((global char*)p_dst + off_dst); + + const uint K = Cout; + const uint CRS = Cin*KH*KW; + const uint NPQ = N*OH*OW; + + const uint lid_k = get_local_id(0); + const uint lid_npq = get_local_id(1); + const uint tid = lid_npq * WG_K + lid_k; + + const uint B_idx_K = get_group_id(0); + const uint B_idx_NPQ = get_group_id(1); + + const uint offset_k = B_idx_K * BS_K; + const uint offset_npq = B_idx_NPQ * BS_NPQ; + + local T_FLOAT* Ash = (local T_FLOAT*)shared; + local T_FLOAT4* Bsh = (local T_FLOAT4*) &Ash[BS_K * BS_CRS]; + + T_ACCUM regC[TS_K][TS_NPQ_VEC]; + for (int i = 0; i < TS_K; ++i) { + for (int j = 0; j < TS_NPQ_VEC; ++j) { + regC[i][j] = (T_ACCUM)(0.0f); + } + } + + const uint NB_CRS = splitWork(CRS, BS_CRS); + + for (uint B_idx_CRS = 0; B_idx_CRS < NB_CRS; ++B_idx_CRS) { + const uint offset_crs = B_idx_CRS * BS_CRS; + + for (int i = tid; i < BS_K * BS_CRS; i += (WG_K * WG_NPQ)) { + const uint k_l = i / BS_CRS; + const uint crs_l = i % BS_CRS; + const uint k_g = offset_k + k_l; + const uint crs_g = offset_crs + crs_l; + + if (k_g < K && crs_g < CRS) { + const uint Cin_idx = crs_g / (KW*KH); + const uint KH_idx = (crs_g - Cin_idx*KW*KH) / KW; + const uint KW_idx = crs_g - Cin_idx*KW*KH - KH_idx*KW; + const uint knl_idx = KW_idx + KH_idx*nb01 + Cin_idx*nb02 + k_g*nb03; + Ash[k_l * BS_CRS + crs_l] = knl_data[knl_idx]; + } else { + Ash[k_l * BS_CRS + crs_l] = (T_FLOAT)0.0f; + } + } + + for (int i = tid; i < BS_CRS * BS_NPQ_VEC; i += (WG_K * WG_NPQ)) { + const uint crs_l = i / BS_NPQ_VEC; + const uint npq_l_vec = i % BS_NPQ_VEC; + const uint crs_g = offset_crs + crs_l; + + T_FLOAT4 val = (T_FLOAT4)(0.0f); + if (crs_g < CRS) { + const uint Cin_idx = crs_g / (KW * KH); + const uint KH_idx = (crs_g - Cin_idx * KW * KH) / KW; + const uint KW_idx = crs_g - Cin_idx * KW * KH - KH_idx * KW; + for (int v = 0; v < VEC_SIZE; ++v) { + const uint npq_g = offset_npq + npq_l_vec * VEC_SIZE + v; + if (npq_g < NPQ) { + const uint N_idx = npq_g / (OH * OW); + const uint pq_idx = npq_g % (OH * OW); + const uint OH_idx = pq_idx / OW; + const uint OW_idx = pq_idx % OW; + const int H_idx = (int)(OH_idx * s1 + KH_idx * d1 - p1); + const int W_idx = (int)(OW_idx * s0 + KW_idx * d0 - p0); + + if (H_idx >= 0 && H_idx < H && W_idx >= 0 && W_idx < W) { + const uint src_idx = W_idx + H_idx * nb11 + Cin_idx * nb12 + N_idx * nb13; + ((T_FLOAT*)&val)[v] = src_data[src_idx]; + } + } + } + } + Bsh[crs_l * BS_NPQ_VEC + npq_l_vec] = val; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + #pragma unroll + for (uint crs_l = 0; crs_l < BS_CRS; ++crs_l) { + T_FLOAT regA[TS_K]; + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + regA[k_l_reg] = Ash[(lid_k * TS_K + k_l_reg) * BS_CRS + crs_l]; + } + + for (uint npq_l_vec_reg = 0; npq_l_vec_reg < TS_NPQ_VEC; ++npq_l_vec_reg) { + T_FLOAT4 regB = Bsh[crs_l * BS_NPQ_VEC + lid_npq * TS_NPQ_VEC + npq_l_vec_reg]; + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + regC[k_l_reg][npq_l_vec_reg] = mad(convert_float(regA[k_l_reg]), convert_float4(regB), regC[k_l_reg][npq_l_vec_reg]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + const uint k_g = offset_k + lid_k * TS_K + k_l_reg; + if (k_g >= K) continue; + + for (uint npq_l_vec_reg = 0; npq_l_vec_reg < TS_NPQ_VEC; ++npq_l_vec_reg) { + const uint npq_g_base = offset_npq + (lid_npq * TS_NPQ_VEC + npq_l_vec_reg) * VEC_SIZE; + + const uint N_idx = npq_g_base / (OH * OW); + const uint pq_idx = npq_g_base % (OH * OW); + const uint OH_idx = pq_idx / OW; + const uint OW_idx = pq_idx % OW; + + if (nb1 == OW && OW_idx + VEC_SIZE <= OW && npq_g_base + VEC_SIZE <= NPQ) { + const uint dst_idx = OW_idx + OH_idx*nb1 + k_g*nb2 + N_idx*nb3; + VSTORE_T_FLOAT4(regC[k_l_reg][npq_l_vec_reg], 0, &dst_data[dst_idx]); + } else { + T_ACCUM res = regC[k_l_reg][npq_l_vec_reg]; + for (int v = 0; v < VEC_SIZE; ++v) { + const uint npq_g = npq_g_base + v; + if (npq_g < NPQ) { + const uint N_idx_s = npq_g / (OH*OW); + const uint pq_idx_s = npq_g % (OH*OW); + const uint OH_idx_s = pq_idx_s / OW; + const uint OW_idx_s = pq_idx_s % OW; + const uint dst_idx_s = OW_idx_s + OH_idx_s*nb1 + k_g*nb2 + N_idx_s*nb3; + dst_data[dst_idx_s] = (T_FLOAT)(((float*)&res)[v]); + } + } + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/conv2d_f16_f32.cl b/ggml/src/ggml-opencl/kernels/conv2d_f16_f32.cl new file mode 100644 index 0000000000..cb05637f33 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/conv2d_f16_f32.cl @@ -0,0 +1,176 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#if defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#else +#define REQD_SUBGROUP_SIZE_128 +#endif + +#define T_ACCUM float4 +#define VEC_SIZE 4 + +#define BS_K 64 +#define BS_NPQ 64 +#define BS_CRS 16 + +#define TS_K 4 +#define TS_NPQ 8 + +#define WG_K (BS_K / TS_K) +#define WG_NPQ (BS_NPQ / TS_NPQ) + +#define BS_NPQ_VEC (BS_NPQ / VEC_SIZE) +#define TS_NPQ_VEC (TS_NPQ / VEC_SIZE) + +static inline uint splitWork(uint work_size, uint block_size){ + return (work_size + block_size - 1) / block_size; +} + +REQD_SUBGROUP_SIZE_128 +kernel void kernel_conv_2d( + global void* p_knl, + ulong off_knl, + global void* p_src, + ulong off_src, + global void* p_dst, + ulong off_dst, + local void* shared, + uint Cout, uint Cin, uint N, + uint KW, uint KH, uint W, uint H, uint OW, uint OH, + uint s0, uint s1, uint p0, uint p1, uint d0, uint d1, + uint nb01, uint nb02, uint nb03, + uint nb11, uint nb12, uint nb13, + uint nb1, uint nb2, uint nb3 +) { + global half* knl_data = (global half*) ((global char*)p_knl + off_knl); + global float* src_data = (global float*) ((global char*)p_src + off_src); + global float* dst_data = (global float*) ((global char*)p_dst + off_dst); + + const uint K = Cout; + const uint CRS = Cin*KH*KW; + const uint NPQ = N*OH*OW; + + const uint lid_k = get_local_id(0); + const uint lid_npq = get_local_id(1); + const uint tid = lid_npq * WG_K + lid_k; + + const uint B_idx_K = get_group_id(0); + const uint B_idx_NPQ = get_group_id(1); + + const uint offset_k = B_idx_K * BS_K; + const uint offset_npq = B_idx_NPQ * BS_NPQ; + + local half* Ash = (local half*)shared; + local float4* Bsh = (local float4*) &Ash[BS_K * BS_CRS]; + + T_ACCUM regC[TS_K][TS_NPQ_VEC]; + for (int i = 0; i < TS_K; ++i) { + for (int j = 0; j < TS_NPQ_VEC; ++j) { + regC[i][j] = (T_ACCUM)(0.0f); + } + } + + const uint NB_CRS = splitWork(CRS, BS_CRS); + + for (uint B_idx_CRS = 0; B_idx_CRS < NB_CRS; ++B_idx_CRS) { + const uint offset_crs = B_idx_CRS * BS_CRS; + + for (int i = tid; i < BS_K * BS_CRS; i += (WG_K * WG_NPQ)) { + const uint k_l = i / BS_CRS; + const uint crs_l = i % BS_CRS; + const uint k_g = offset_k + k_l; + const uint crs_g = offset_crs + crs_l; + + if (k_g < K && crs_g < CRS) { + const uint Cin_idx = crs_g / (KW*KH); + const uint KH_idx = (crs_g - Cin_idx*KW*KH) / KW; + const uint KW_idx = crs_g - Cin_idx*KW*KH - KH_idx*KW; + const uint knl_idx = KW_idx + KH_idx*nb01 + Cin_idx*nb02 + k_g*nb03; + Ash[k_l * BS_CRS + crs_l] = knl_data[knl_idx]; + } else { + Ash[k_l * BS_CRS + crs_l] = (half)0.0f; + } + } + + for (int i = tid; i < BS_CRS * BS_NPQ_VEC; i += (WG_K * WG_NPQ)) { + const uint crs_l = i / BS_NPQ_VEC; + const uint npq_l_vec = i % BS_NPQ_VEC; + const uint crs_g = offset_crs + crs_l; + + float4 val = (float4)(0.0f); + if (crs_g < CRS) { + const uint Cin_idx = crs_g / (KW * KH); + const uint KH_idx = (crs_g - Cin_idx * KW * KH) / KW; + const uint KW_idx = crs_g - Cin_idx * KW * KH - KH_idx * KW; + for (int v = 0; v < VEC_SIZE; ++v) { + const uint npq_g = offset_npq + npq_l_vec * VEC_SIZE + v; + if (npq_g < NPQ) { + const uint N_idx = npq_g / (OH * OW); + const uint pq_idx = npq_g % (OH * OW); + const uint OH_idx = pq_idx / OW; + const uint OW_idx = pq_idx % OW; + const int H_idx = (int)(OH_idx * s1 + KH_idx * d1 - p1); + const int W_idx = (int)(OW_idx * s0 + KW_idx * d0 - p0); + + if (H_idx >= 0 && H_idx < H && W_idx >= 0 && W_idx < W) { + const uint src_idx = W_idx + H_idx * nb11 + Cin_idx * nb12 + N_idx * nb13; + ((float*)&val)[v] = src_data[src_idx]; + } + } + } + } + Bsh[crs_l * BS_NPQ_VEC + npq_l_vec] = val; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + #pragma unroll + for (uint crs_l = 0; crs_l < BS_CRS; ++crs_l) { + half regA[TS_K]; + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + regA[k_l_reg] = Ash[(lid_k * TS_K + k_l_reg) * BS_CRS + crs_l]; + } + + for (uint npq_l_vec_reg = 0; npq_l_vec_reg < TS_NPQ_VEC; ++npq_l_vec_reg) { + float4 regB = Bsh[crs_l * BS_NPQ_VEC + lid_npq * TS_NPQ_VEC + npq_l_vec_reg]; + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + regC[k_l_reg][npq_l_vec_reg] = mad(convert_float(regA[k_l_reg]), regB, regC[k_l_reg][npq_l_vec_reg]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + const uint k_g = offset_k + lid_k * TS_K + k_l_reg; + if (k_g >= K) continue; + + for (uint npq_l_vec_reg = 0; npq_l_vec_reg < TS_NPQ_VEC; ++npq_l_vec_reg) { + const uint npq_g_base = offset_npq + (lid_npq * TS_NPQ_VEC + npq_l_vec_reg) * VEC_SIZE; + + const uint N_idx = npq_g_base / (OH * OW); + const uint pq_idx = npq_g_base % (OH * OW); + const uint OH_idx = pq_idx / OW; + const uint OW_idx = pq_idx % OW; + + if (nb1 == OW && OW_idx + VEC_SIZE <= OW && npq_g_base + VEC_SIZE <= NPQ) { + const uint dst_idx = OW_idx + OH_idx*nb1 + k_g*nb2 + N_idx*nb3; + vstore4(regC[k_l_reg][npq_l_vec_reg], 0, &dst_data[dst_idx]); + } else { + T_ACCUM res = regC[k_l_reg][npq_l_vec_reg]; + for (int v = 0; v < VEC_SIZE; ++v) { + const uint npq_g = npq_g_base + v; + if (npq_g < NPQ) { + const uint N_idx_s = npq_g / (OH*OW); + const uint pq_idx_s = npq_g % (OH*OW); + const uint OH_idx_s = pq_idx_s / OW; + const uint OW_idx_s = pq_idx_s % OW; + const uint dst_idx_s = OW_idx_s + OH_idx_s*nb1 + k_g*nb2 + N_idx_s*nb3; + dst_data[dst_idx_s] = ((float*)&res)[v]; + } + } + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/div.cl b/ggml/src/ggml-opencl/kernels/div.cl index d453ad99be..6d9b4ade9f 100644 --- a/ggml/src/ggml-opencl/kernels/div.cl +++ b/ggml/src/ggml-opencl/kernels/div.cl @@ -70,3 +70,69 @@ kernel void kernel_div_row( uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne dst[gid] = src0[gid] / src1[idx1]; } + +kernel void kernel_div_f16( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + ulong nb00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne10, + int ne11, + int ne12, + int ne13, + ulong nb10, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + ulong nb0, + ulong nb1, + ulong nb2, + ulong nb3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0); + + int i13 = i03 % ne13; + int i12 = i02 % ne12; + int i11 = i01 % ne11; + + global char * src0_ptr = src0 + i03*nb03 + i02*nb02 + i01*nb01; + global char * src1_ptr = src1 + i13*nb13 + i12*nb12 + i11*nb11; + global char * dst_ptr = dst + i03*nb3 + i02*nb2 + i01*nb1; + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + const int i10 = i0 % ne10; + *((global half *)(dst_ptr + i0*nb0)) = *((global half *)(src0_ptr + i0*nb00)) / *((global half *)(src1_ptr + i10*nb10)); + } +} + +kernel void kernel_div_row_f16( + global half4 * src0, + ulong offset0, + global half4 * src1, + ulong offset1, + global half4 * dst, + ulong offsetd, + int ne +) { + src0 = (global half4*)((global char*)src0 + offset0); + src1 = (global half4*)((global char*)src1 + offset1); + dst = (global half4*)((global char*)dst + offsetd); + + // This performs better than using %. + uint gid = get_global_id(0); + uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne + dst[gid] = src0[gid] / src1[idx1]; +} diff --git a/ggml/src/ggml-opencl/kernels/glu.cl b/ggml/src/ggml-opencl/kernels/glu.cl index 7cca16e6a9..059a4bbf1b 100644 --- a/ggml/src/ggml-opencl/kernels/glu.cl +++ b/ggml/src/ggml-opencl/kernels/glu.cl @@ -202,6 +202,47 @@ kernel void kernel_swiglu_f16( } } +//------------------------------------------------------------------------------ +// swiglu_oai +//------------------------------------------------------------------------------ +kernel void kernel_swiglu_oai( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + ulong nb01, + ulong nb11, + int ne0, + ulong nb1, + int ne00_off, + int ne10_off, + float limit, + float alpha +) { + src0 = (global char*)((global char*)src0 + offset0); + src1 = (global char*)((global char*)src1 + offset1); + dst = (global char*)((global char*)dst + offsetd); + + global float * src0_row = (global float *) ((global char *) src0 + get_group_id(0)*nb01) + ne00_off; + global float * src1_row = (global float *) ((global char *) src1 + get_group_id(0)*nb11) + ne10_off; + global float * dst_row = (global float *) ((global char *) dst + get_group_id(0)*nb1); + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + float x0 = src0_row[i0]; + float x1 = src1_row[i0]; + + x0 = min(x0, limit); + x1 = max(min(x1, limit), -limit); + + float out_glu = x0 / (1.0f + exp(-x0 * alpha)); + out_glu = out_glu * (1.0f + x1); + + dst_row[i0] = out_glu; + } +} + //------------------------------------------------------------------------------ // geglu_erf //------------------------------------------------------------------------------ diff --git a/ggml/src/ggml-opencl/kernels/im2col_f16.cl b/ggml/src/ggml-opencl/kernels/im2col_f16.cl index b84c898465..cf6cdaa4ce 100644 --- a/ggml/src/ggml-opencl/kernels/im2col_f16.cl +++ b/ggml/src/ggml-opencl/kernels/im2col_f16.cl @@ -31,7 +31,7 @@ kernel void kernel_im2col_f16( src1 = (global float*)((global char*)src1 + offset1); dst = (global half*)((global char*)dst + offsetd); - long ksize = OW * (KH > 1 ? KW : 1); + long ksize = OW * KH; long kx = i / ksize; long kd = kx * ksize; long ky = (i - kd) / OW; diff --git a/ggml/src/ggml-opencl/kernels/im2col_f32.cl b/ggml/src/ggml-opencl/kernels/im2col_f32.cl index 4bf65e4eaa..1ecdb2344a 100644 --- a/ggml/src/ggml-opencl/kernels/im2col_f32.cl +++ b/ggml/src/ggml-opencl/kernels/im2col_f32.cl @@ -31,7 +31,7 @@ kernel void kernel_im2col_f32( src1 = (global float*)((global char*)src1 + offset1); dst = (global float*)((global char*)dst + offsetd); - long ksize = OW * (KH > 1 ? KW : 1); + long ksize = OW * KH; long kx = i / ksize; long kd = kx * ksize; long ky = (i - kd) / OW; diff --git a/ggml/src/ggml-opencl/kernels/mul.cl b/ggml/src/ggml-opencl/kernels/mul.cl index 2a2b4eb70a..b12a592165 100644 --- a/ggml/src/ggml-opencl/kernels/mul.cl +++ b/ggml/src/ggml-opencl/kernels/mul.cl @@ -77,3 +77,76 @@ kernel void kernel_mul_row( uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne dst[gid] = src0[gid] * src1[idx1]; } + +kernel void kernel_mul_f16( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + int ne02, + int ne03, + ulong nb00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne10, + int ne11, + int ne12, + int ne13, + ulong nb10, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int ne2, + int ne3, + ulong nb0, + ulong nb1, + ulong nb2, + ulong nb3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0); + + int i13 = i03 % ne13; + int i12 = i02 % ne12; + int i11 = i01 % ne11; + + global char * src0_ptr = src0 + i03*nb03 + i02*nb02 + i01*nb01; + global char * src1_ptr = src1 + i13*nb13 + i12*nb12 + i11*nb11; + global char * dst_ptr = dst + i03*nb3 + i02*nb2 + i01*nb1; + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + const int i10 = i0 % ne10; + *((global half *)(dst_ptr + i0*nb0)) = *((global half *)(src0_ptr + i0*nb00)) * *((global half *)(src1_ptr + i10*nb10)); + } +} + +kernel void kernel_mul_row_f16( + global half4 * src0, + ulong offset0, + global half4 * src1, + ulong offset1, + global half4 * dst, + ulong offsetd, + int ne +) { + src0 = (global half4*)((global char*)src0 + offset0); + src1 = (global half4*)((global char*)src1 + offset1); + dst = (global half4*)((global char*)dst + offsetd); + + // This performs better than using %. + uint gid = get_global_id(0); + uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne + dst[gid] = src0[gid] * src1[idx1]; +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_f16_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_f16_f32_l4_lm.cl new file mode 100644 index 0000000000..9599a0e157 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_f16_f32_l4_lm.cl @@ -0,0 +1,132 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 16 +#define TM 4 +#define TN 8 + +kernel void kernel_mul_mm_f16_f32_l4_lm( + global half4 * src0, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src0 = (global half4*)((global char*)src0 + offset0); + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float*)((global char*)dst + offsetd); + + local half buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + int pos_a = (batch_idx_a * batch_stride_a + ir * BM * stride_a) / LOAD_VEC_A; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + half cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + const int idx = pos_a + (loadc_a + l) * stride_a / LOAD_VEC_A + loadr_a; + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = src0[idx].s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = src0[idx].s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = src0[idx].s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = src0[idx].s3; + } + + for (int l = 0; l < BN; l += loadstride_b) { + const int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK / LOAD_VEC_A; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(convert_float(cache_a[cr]), cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const int offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/mul_mm_f32_f32_l4_lm.cl b/ggml/src/ggml-opencl/kernels/mul_mm_f32_f32_l4_lm.cl new file mode 100644 index 0000000000..58c5178e39 --- /dev/null +++ b/ggml/src/ggml-opencl/kernels/mul_mm_f32_f32_l4_lm.cl @@ -0,0 +1,133 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 16 +#define TM 4 +#define TN 8 + +kernel void kernel_mul_mm_f32_f32_l4_lm( + global float4 * src0, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src0 = (global float4*)((global char*)src0 + offset0); + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float*)((global char*)dst + offsetd); + + local float buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + int pos_a = (batch_idx_a * batch_stride_a + ir * BM * stride_a) / LOAD_VEC_A; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + float cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + const int idx = pos_a + (loadc_a + l) * stride_a / LOAD_VEC_A + loadr_a; + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = src0[idx].s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = src0[idx].s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = src0[idx].s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = src0[idx].s3; + } + + for (int l = 0; l < BN; l += loadstride_b) { + const int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK / LOAD_VEC_A; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(cache_a[cr], cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const int offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff --git a/ggml/src/ggml-opencl/kernels/rms_norm.cl b/ggml/src/ggml-opencl/kernels/rms_norm.cl index 9d21f3398e..ecd053cb4c 100644 --- a/ggml/src/ggml-opencl/kernels/rms_norm.cl +++ b/ggml/src/ggml-opencl/kernels/rms_norm.cl @@ -94,3 +94,82 @@ kernel void kernel_rms_norm( } } } + +//------------------------------------------------------------------------------ +// rms_norm_mul +//------------------------------------------------------------------------------ +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_32 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_rms_norm_mul( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + int ne02, + int ne03, + ulong nb01, + ulong nb02, + ulong nb03, + int ne10, + int ne11, + int ne12, + int ne13, + ulong nb11, + ulong nb12, + ulong nb13, + ulong nb1, + ulong nb2, + ulong nb3, + float eps, + local float * sum +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0); + + global float4 * x = (global float4 *) (src0 + i03*nb03 + i02*nb02 + i01*nb01); + global float4 * f = (global float4 *) (src1 + (i03%ne13)*nb13 + (i02%ne12)*nb12 + (i01%ne11)*nb11); + + float sumf = 0; + + // parallel sum + for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { + sumf += dot(x[i00], x[i00]); + } + sumf = sub_group_reduce_add(sumf); + if (get_sub_group_local_id() == 0) { + sum[get_sub_group_id()] = sumf; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + for (uint i = get_local_size(0) / get_max_sub_group_size() / 2; i > 0; i /= 2) { + if (get_local_id(0) < i) { + sum[get_local_id(0)] += sum[get_local_id(0) + i]; + } + } + if (get_local_id(0) == 0) { + sum[0] /= ne00; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + float mean = sum[0]; + float scale = 1.0f/sqrt(mean + eps); + + global float4 * y = (global float4 *) (dst + i03*nb3 + i02*nb2 + i01*nb1); + for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { + y[i00] = (x[i00] * scale) * f[i00%(ne10/4)]; + } +} diff --git a/ggml/src/ggml-opencl/kernels/softmax_4_f16.cl b/ggml/src/ggml-opencl/kernels/softmax_4_f16.cl index a6d8ede670..571d16507c 100644 --- a/ggml/src/ggml-opencl/kernels/softmax_4_f16.cl +++ b/ggml/src/ggml-opencl/kernels/softmax_4_f16.cl @@ -26,6 +26,8 @@ kernel void kernel_soft_max_4_f16( ulong offset0, global char * src1, ulong offset1, + global char * src2, + ulong offset2, global char * dst, ulong offsetd, int ne00, @@ -48,6 +50,7 @@ kernel void kernel_soft_max_4_f16( ) { src0 = src0 + offset0; src1 = src1 + offset1; + src2 = src2 + offset2; dst = dst + offsetd; int i03 = get_group_id(2); @@ -60,6 +63,7 @@ kernel void kernel_soft_max_4_f16( global float4 * psrc4 = (global float4 *)(src0 + i01*nb01 + i02*nb02 + i03*nb03); global half4 * pmask = src1 != src0 ? (global half4 *)(src1 + i11*nb11 + i12*nb12 + i13*nb13) : 0; + global float * psrc2 = src2 != src0 ? (global float *)(src2) : 0; global float4 * pdst4 = (global float4 *)(dst + i01*nb1 + i02*nb2 + i03*nb3); float slope = 1.0f; @@ -75,7 +79,7 @@ kernel void kernel_soft_max_4_f16( } // parallel max - float4 lmax4 = -INFINITY; + float4 lmax4 = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { lmax4 = fmax(lmax4, psrc4[i00]*scale + slope*(pmask ? convert_float4(pmask[i00]) : 0.0f)); } @@ -92,7 +96,11 @@ kernel void kernel_soft_max_4_f16( } float lsum = lsum4.s0 + lsum4.s1 + lsum4.s2 + lsum4.s3; - const float sum = sub_group_reduce_add(lsum); + float sum = sub_group_reduce_add(lsum); + + if (psrc2) { + sum += exp(psrc2[i02] - max); + } for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { pdst4[i00] /= sum; diff --git a/ggml/src/ggml-opencl/kernels/softmax_4_f32.cl b/ggml/src/ggml-opencl/kernels/softmax_4_f32.cl index 35b5573b46..1f944b2201 100644 --- a/ggml/src/ggml-opencl/kernels/softmax_4_f32.cl +++ b/ggml/src/ggml-opencl/kernels/softmax_4_f32.cl @@ -26,6 +26,8 @@ kernel void kernel_soft_max_4( ulong offset0, global char * src1, ulong offset1, + global char * src2, + ulong offset2, global char * dst, ulong offsetd, int ne00, @@ -48,6 +50,7 @@ kernel void kernel_soft_max_4( ) { src0 = src0 + offset0; src1 = src1 + offset1; + src2 = src2 + offset2; dst = dst + offsetd; int i03 = get_group_id(2); @@ -60,6 +63,7 @@ kernel void kernel_soft_max_4( global float4 * psrc4 = (global float4 *)(src0 + i01*nb01 + i02*nb02 + i03*nb03); global float4 * pmask = src1 != src0 ? (global float4 *)(src1 + i11*nb11 + i12*nb12 + i13*nb13) : 0; + global float * psrc2 = src2 != src0 ? (global float *)(src2) : 0; global float4 * pdst4 = (global float4 *)(dst + i01*nb1 + i02*nb2 + i03*nb3); float slope = 1.0f; @@ -75,7 +79,7 @@ kernel void kernel_soft_max_4( } // parallel max - float4 lmax4 = -INFINITY; + float4 lmax4 = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { lmax4 = fmax(lmax4, psrc4[i00]*scale + (pmask ? slope*pmask[i00] : 0.0f)); } @@ -92,7 +96,11 @@ kernel void kernel_soft_max_4( } float lsum = lsum4.s0 + lsum4.s1 + lsum4.s2 + lsum4.s3; - const float sum = sub_group_reduce_add(lsum); + float sum = sub_group_reduce_add(lsum); + + if (psrc2) { + sum += exp(psrc2[i02] - max); + } for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { pdst4[i00] /= sum; diff --git a/ggml/src/ggml-opencl/kernels/softmax_f16.cl b/ggml/src/ggml-opencl/kernels/softmax_f16.cl index 9d292b5746..4baa6c28e4 100644 --- a/ggml/src/ggml-opencl/kernels/softmax_f16.cl +++ b/ggml/src/ggml-opencl/kernels/softmax_f16.cl @@ -26,6 +26,8 @@ kernel void kernel_soft_max_f16( ulong offset0, global char * src1, ulong offset1, + global char * src2, + ulong offset2, global char * dst, ulong offsetd, int ne00, @@ -48,6 +50,7 @@ kernel void kernel_soft_max_f16( ) { src0 = src0 + offset0; src1 = src1 + offset1; + src2 = src2 + offset2; dst = dst + offsetd; int i03 = get_group_id(2); @@ -60,6 +63,7 @@ kernel void kernel_soft_max_f16( global float * psrc0 = (global float *)(src0 + i01*nb01 + i02*nb02 + i03*nb03); global half * pmask = src1 != src0 ? (global half *)(src1 + i11*nb11 + i12*nb12 + i13*nb13) : 0; + global float * psrc2 = src2 != src0 ? (global float *)(src2) : 0; global float * pdst = (global float *)(dst + i01*nb1 + i02*nb2 + i03*nb3); float slope = 1.0f; @@ -75,7 +79,7 @@ kernel void kernel_soft_max_f16( } // parallel max - float lmax = -INFINITY; + float lmax = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = get_local_id(0); i00 < ne00; i00 += get_local_size(0)) { lmax = fmax(lmax, psrc0[i00]*scale + (pmask ? slope*pmask[i00] : 0.0f)); } @@ -91,7 +95,11 @@ kernel void kernel_soft_max_f16( pdst[i00] = exp_psrc0; } - const float sum = sub_group_reduce_add(lsum); + float sum = sub_group_reduce_add(lsum); + + if (psrc2) { + sum += exp(psrc2[i02] - max); + } for (int i00 = get_local_id(0); i00 < ne00; i00 += get_local_size(0)) { pdst[i00] /= sum; diff --git a/ggml/src/ggml-opencl/kernels/softmax_f32.cl b/ggml/src/ggml-opencl/kernels/softmax_f32.cl index 7c53dfbe5a..d503190b47 100644 --- a/ggml/src/ggml-opencl/kernels/softmax_f32.cl +++ b/ggml/src/ggml-opencl/kernels/softmax_f32.cl @@ -26,6 +26,8 @@ kernel void kernel_soft_max( ulong offset0, global char * src1, ulong offset1, + global char * src2, + ulong offset2, global char * dst, ulong offsetd, int ne00, @@ -48,6 +50,7 @@ kernel void kernel_soft_max( ) { src0 = src0 + offset0; src1 = src1 + offset1; + src2 = src2 + offset2; dst = dst + offsetd; int i03 = get_group_id(2); @@ -60,6 +63,7 @@ kernel void kernel_soft_max( global float * psrc0 = (global float *)(src0 + i01*nb01 + i02*nb02 + i03*nb03); global float * pmask = src1 != src0 ? (global float *)(src1 + i11*nb11 + i12*nb12 + i13*nb13) : 0; + global float * psrc2 = src2 != src0 ? (global float *)(src2) : 0; global float * pdst = (global float *)(dst + i01*nb1 + i02*nb2 + i03*nb3); float slope = 1.0f; @@ -75,7 +79,7 @@ kernel void kernel_soft_max( } // parallel max - float lmax = -INFINITY; + float lmax = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = get_local_id(0); i00 < ne00; i00 += get_local_size(0)) { lmax = fmax(lmax, psrc0[i00]*scale + (pmask ? slope*pmask[i00] : 0.0f)); } @@ -91,7 +95,11 @@ kernel void kernel_soft_max( pdst[i00] = exp_psrc0; } - const float sum = sub_group_reduce_add(lsum); + float sum = sub_group_reduce_add(lsum); + + if (psrc2) { + sum += exp(psrc2[i02] - max); + } for (int i00 = get_local_id(0); i00 < ne00; i00 += get_local_size(0)) { pdst[i00] /= sum; diff --git a/ggml/src/ggml-opencl/kernels/sub.cl b/ggml/src/ggml-opencl/kernels/sub.cl index 041e88ad3a..423ed595ca 100644 --- a/ggml/src/ggml-opencl/kernels/sub.cl +++ b/ggml/src/ggml-opencl/kernels/sub.cl @@ -70,3 +70,69 @@ kernel void kernel_sub_row( uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne dst[gid] = src0[gid] - src1[idx1]; } + +kernel void kernel_sub_f16( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + ulong nb00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne10, + int ne11, + int ne12, + int ne13, + ulong nb10, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + ulong nb0, + ulong nb1, + ulong nb2, + ulong nb3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0); + + int i13 = i03 % ne13; + int i12 = i02 % ne12; + int i11 = i01 % ne11; + + global char * src0_ptr = src0 + i03*nb03 + i02*nb02 + i01*nb01; + global char * src1_ptr = src1 + i13*nb13 + i12*nb12 + i11*nb11; + global char * dst_ptr = dst + i03*nb3 + i02*nb2 + i01*nb1; + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + const int i10 = i0 % ne10; + *((global half *)(dst_ptr + i0*nb0)) = *((global half *)(src0_ptr + i0*nb00)) - *((global half *)(src1_ptr + i10*nb10)); + } +} + +kernel void kernel_sub_row_f16( + global half4 * src0, + ulong offset0, + global half4 * src1, + ulong offset1, + global half4 * dst, + ulong offsetd, + int ne +) { + src0 = (global half4*)((global char*)src0 + offset0); + src1 = (global half4*)((global char*)src1 + offset1); + dst = (global half4*)((global char*)dst + offsetd); + + // This performs better than using %. + uint gid = get_global_id(0); + uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne + dst[gid] = src0[gid] - src1[idx1]; +} diff --git a/ggml/src/ggml-opt.cpp b/ggml/src/ggml-opt.cpp index a3c82d6757..e078ad14a3 100644 --- a/ggml/src/ggml-opt.cpp +++ b/ggml/src/ggml-opt.cpp @@ -64,9 +64,11 @@ struct ggml_opt_context { int32_t opt_i = 0; bool loss_per_datapoint = false; - ggml_opt_get_optimizer_params get_opt_pars = nullptr; - void * get_opt_pars_ud = nullptr; - struct ggml_tensor * adamw_params = nullptr; + ggml_opt_get_optimizer_params get_opt_pars = nullptr; + void * get_opt_pars_ud = nullptr; + struct ggml_tensor * opt_step_params = nullptr; // Stores output of get_opt_pars. + + enum ggml_opt_optimizer_type optimizer = GGML_OPT_OPTIMIZER_TYPE_ADAMW; }; struct ggml_opt_result { @@ -229,9 +231,13 @@ struct ggml_opt_optimizer_params ggml_opt_get_default_optimizer_params(void * us result.adamw.eps = 1e-8f; result.adamw.wd = 0.0f; + result.sgd.alpha = 1e-3f; + result.sgd.wd = 0.0f; + return result; } + struct ggml_opt_optimizer_params ggml_opt_get_constant_optimizer_params(void * userdata) { return *((struct ggml_opt_optimizer_params *) userdata); } @@ -249,6 +255,7 @@ struct ggml_opt_params ggml_opt_default_params( /*opt_period =*/ 1, /*get_opt_pars =*/ ggml_opt_get_default_optimizer_params, /*get_opt_pars_ud =*/ nullptr, + /*optimizer =*/ GGML_OPT_OPTIMIZER_TYPE_ADAMW, }; } @@ -316,9 +323,14 @@ static void ggml_opt_build(ggml_opt_context_t opt_ctx) { GGML_ASSERT(opt_ctx->ctx_compute && "no compute context set, either use static graphs or set one with ggml_opt_prepare_alloc"); GGML_ASSERT((!opt_ctx->static_graphs || opt_ctx->inputs->data) && "when using static graphs the inputs must be allocated statically"); + const enum ggml_opt_optimizer_type optimizer = opt_ctx->optimizer; + const bool accumulate = opt_ctx->build_type_alloc >= GGML_OPT_BUILD_TYPE_GRAD && !(opt_ctx->static_graphs && opt_ctx->build_type_alloc == GGML_OPT_BUILD_TYPE_OPT && opt_ctx->opt_period == 1); + const bool need_momenta = opt_ctx->build_type_alloc == GGML_OPT_BUILD_TYPE_OPT && + opt_ctx->optimizer == GGML_OPT_OPTIMIZER_TYPE_ADAMW; + ggml_set_input(opt_ctx->inputs); ggml_set_output(opt_ctx->outputs); @@ -340,8 +352,7 @@ static void ggml_opt_build(ggml_opt_context_t opt_ctx) { // - pred (if using static graphs) // - ncorrect (if using static graphs, 2 tensors). constexpr size_t n_loss = 1; - const size_t tensors_per_param = (accumulate ? 1 : 0) + - (opt_ctx->build_type_alloc == GGML_OPT_BUILD_TYPE_OPT ? 2 : 0); + const size_t tensors_per_param = (accumulate ? 1 : 0) + (need_momenta ? 2 : 0); const size_t tensors_const = opt_ctx->static_graphs ? 9 : 0; const size_t size_meta = (n_loss + tensors_per_param*n_param + tensors_const) * ggml_tensor_overhead(); struct ggml_init_params params = { @@ -458,7 +469,7 @@ static void ggml_opt_build(ggml_opt_context_t opt_ctx) { } } - if (opt_ctx->build_type_alloc >= GGML_OPT_BUILD_TYPE_OPT) { + if (need_momenta && opt_ctx->build_type_alloc >= GGML_OPT_BUILD_TYPE_OPT) { opt_ctx->grad_m.resize(n_nodes); opt_ctx->grad_v.resize(n_nodes); for (int i = 0; i < n_nodes; ++i) { @@ -492,23 +503,36 @@ static void ggml_opt_build(ggml_opt_context_t opt_ctx) { // gb_opt == graph backward optimize, forward pass, then backward pass to calculate gradients, then optimizer step. opt_ctx->gb_opt = ggml_graph_dup(opt_ctx->ctx_compute, opt_ctx->gb_grad, /*force_grads =*/ true); - opt_ctx->adamw_params = ggml_new_tensor_1d(opt_ctx->ctx_cpu, GGML_TYPE_F32, 7); - ggml_set_input(opt_ctx->adamw_params); - ggml_set_name(opt_ctx->adamw_params, "adamw_params"); - + opt_ctx->opt_step_params = ggml_new_tensor_1d(opt_ctx->ctx_cpu, GGML_TYPE_F32, need_momenta ? 7 : 2); + ggml_tensor * adamw_params = opt_ctx->opt_step_params; + ggml_set_input(adamw_params); + const char * optimizer_name = ggml_opt_optimizer_name(opt_ctx->optimizer); + ggml_format_name(adamw_params, "%s_params", optimizer_name); for (int i = opt_ctx->gf->n_nodes-1; i >= 0; --i) { struct ggml_tensor * node = opt_ctx->gb_opt->nodes[i]; struct ggml_tensor * grad = ggml_graph_get_grad(opt_ctx->gb_opt, node); if (grad && (node->flags & GGML_TENSOR_FLAG_PARAM)) { - struct ggml_tensor * m = opt_ctx->grad_m[i]; - struct ggml_tensor * v = opt_ctx->grad_v[i]; - struct ggml_tensor * opt_step = ggml_opt_step_adamw(opt_ctx->ctx_compute, node, grad, m, v, opt_ctx->adamw_params); - - ggml_set_name(m, (std::string("AdamW m for ") + std::string(node->name)).c_str()); - ggml_set_name(v, (std::string("AdamW v for ") + std::string(node->name)).c_str()); - ggml_set_name(opt_step, (std::string("AdamW step for ") + std::string(node->name)).c_str()); - + struct ggml_tensor * m = nullptr; + struct ggml_tensor * v = nullptr; + if (need_momenta) { + m = opt_ctx->grad_m[i]; + v = opt_ctx->grad_v[i]; + ggml_format_name(m, "AdamW m for %s", node->name); + ggml_format_name(v, "AdamW v for %s", node->name); + } + struct ggml_tensor * opt_step; + switch (optimizer) { + case GGML_OPT_OPTIMIZER_TYPE_ADAMW: + opt_step = ggml_opt_step_adamw(opt_ctx->ctx_compute, node, grad, m, v, adamw_params); + break; + case GGML_OPT_OPTIMIZER_TYPE_SGD: + opt_step = ggml_opt_step_sgd(opt_ctx->ctx_compute, node, grad, adamw_params); + break; + default: + GGML_ABORT("fatal error"); + } + ggml_format_name(opt_step, "%s step for %s", optimizer_name, node->name); ggml_build_forward_expand(opt_ctx->gb_opt, opt_step); } } @@ -534,6 +558,7 @@ ggml_opt_context_t ggml_opt_init(struct ggml_opt_params params) { result->opt_period = params.opt_period; result->get_opt_pars = params.get_opt_pars; result->get_opt_pars_ud = params.get_opt_pars_ud; + result->optimizer = params.optimizer; GGML_ASSERT(result->opt_period >= 1); @@ -756,29 +781,43 @@ void ggml_opt_alloc(ggml_opt_context_t opt_ctx, bool backward) { void ggml_opt_eval(ggml_opt_context_t opt_ctx, ggml_opt_result_t result) { GGML_ASSERT(opt_ctx->eval_ready); if (opt_ctx->allocated_graph == opt_ctx->gb_opt) { - struct ggml_opt_optimizer_params opt_pars = opt_ctx->get_opt_pars(opt_ctx->get_opt_pars_ud); + const ggml_opt_optimizer_params & opt_pars = opt_ctx->get_opt_pars(opt_ctx->get_opt_pars_ud); - GGML_ASSERT(opt_pars.adamw.alpha > 0.0f); - GGML_ASSERT(opt_pars.adamw.beta1 >= 0.0f); - GGML_ASSERT(opt_pars.adamw.beta1 <= 1.0f); - GGML_ASSERT(opt_pars.adamw.beta2 >= 0.0f); - GGML_ASSERT(opt_pars.adamw.beta2 <= 1.0f); - GGML_ASSERT(opt_pars.adamw.eps >= 0.0f); - GGML_ASSERT(opt_pars.adamw.wd >= 0.0f); - GGML_ASSERT(opt_pars.adamw.wd <= 1.0f); + switch (opt_ctx->optimizer) { + case GGML_OPT_OPTIMIZER_TYPE_ADAMW: { + GGML_ASSERT(opt_pars.adamw.alpha > 0.0f); + GGML_ASSERT(opt_pars.adamw.beta1 >= 0.0f); + GGML_ASSERT(opt_pars.adamw.beta1 <= 1.0f); + GGML_ASSERT(opt_pars.adamw.beta2 >= 0.0f); + GGML_ASSERT(opt_pars.adamw.beta2 <= 1.0f); + GGML_ASSERT(opt_pars.adamw.eps >= 0.0f); + GGML_ASSERT(opt_pars.adamw.wd >= 0.0f); + GGML_ASSERT(opt_pars.adamw.wd <= 1.0f); - // beta1, beta2 after applying warmup - const float beta1h = 1.0f/(1.0f - powf(opt_pars.adamw.beta1, opt_ctx->iter)); - const float beta2h = 1.0f/(1.0f - powf(opt_pars.adamw.beta2, opt_ctx->iter)); + // beta1, beta2 after applying warmup + const float beta1h = 1.0f / (1.0f - powf(opt_pars.adamw.beta1, opt_ctx->iter)); + const float beta2h = 1.0f / (1.0f - powf(opt_pars.adamw.beta2, opt_ctx->iter)); - float * adamw_par_data = ggml_get_data_f32(opt_ctx->adamw_params); - adamw_par_data[0] = opt_pars.adamw.alpha; - adamw_par_data[1] = opt_pars.adamw.beta1; - adamw_par_data[2] = opt_pars.adamw.beta2; - adamw_par_data[3] = opt_pars.adamw.eps; - adamw_par_data[4] = opt_pars.adamw.wd; - adamw_par_data[5] = beta1h; - adamw_par_data[6] = beta2h; + float * adamw_par_data = ggml_get_data_f32(opt_ctx->opt_step_params); + adamw_par_data[0] = opt_pars.adamw.alpha; + adamw_par_data[1] = opt_pars.adamw.beta1; + adamw_par_data[2] = opt_pars.adamw.beta2; + adamw_par_data[3] = opt_pars.adamw.eps; + adamw_par_data[4] = opt_pars.adamw.wd; + adamw_par_data[5] = beta1h; + adamw_par_data[6] = beta2h; + } break; + case GGML_OPT_OPTIMIZER_TYPE_SGD: { + GGML_ASSERT(opt_pars.sgd.alpha > 0.0f); + GGML_ASSERT(opt_pars.sgd.wd >= 0.0f); + GGML_ASSERT(opt_pars.sgd.wd <= 1.0f); + float * sgd = ggml_get_data_f32(opt_ctx->opt_step_params); + sgd[0] = opt_pars.sgd.alpha; + sgd[1] = opt_pars.sgd.wd; + } break; + default: + GGML_ABORT("fatal error"); + } } ggml_backend_sched_graph_compute(opt_ctx->backend_sched, opt_ctx->allocated_graph_copy); @@ -963,6 +1002,7 @@ void ggml_opt_fit( ggml_tensor * outputs, ggml_opt_dataset_t dataset, enum ggml_opt_loss_type loss_type, + enum ggml_opt_optimizer_type optimizer, ggml_opt_get_optimizer_params get_opt_pars, int64_t nepoch, int64_t nbatch_logical, @@ -993,6 +1033,7 @@ void ggml_opt_fit( params.opt_period = opt_period; params.get_opt_pars = get_opt_pars; params.get_opt_pars_ud = &epoch; + params.optimizer = optimizer; ggml_opt_context_t opt_ctx = ggml_opt_init(params); // Shuffling the data is generally useful but there is only a point if not all data is used in a single batch. @@ -1035,3 +1076,18 @@ void ggml_opt_fit( ggml_opt_result_free(result_train); ggml_opt_result_free(result_val); } + +enum ggml_opt_optimizer_type ggml_opt_context_optimizer_type(ggml_opt_context_t c) { + return c->optimizer; +} + +GGML_API const char * ggml_opt_optimizer_name(enum ggml_opt_optimizer_type o) { + switch (o) { + case GGML_OPT_OPTIMIZER_TYPE_ADAMW: + return "adamw"; + case GGML_OPT_OPTIMIZER_TYPE_SGD: + return "sgd"; + default: + return "undefined"; + }; +} diff --git a/ggml/src/ggml-quants.c b/ggml/src/ggml-quants.c index 9a7d1b22d7..94f6405ca1 100644 --- a/ggml/src/ggml-quants.c +++ b/ggml/src/ggml-quants.c @@ -21,6 +21,17 @@ #define UNUSED GGML_UNUSED +static inline int best_index_int8(int n, const int8_t * val, float x) { + if (x <= val[0]) return 0; + if (x >= val[n-1]) return n-1; + int ml = 0, mu = n-1; + while (mu-ml > 1) { + int mav = (ml+mu)/2; + if (x < val[mav]) mu = mav; else ml = mav; + } + return x - val[mu-1] < val[mu] - x ? mu-1 : mu; +} + // reference implementation for deterministic creation of model files void quantize_row_q4_0_ref(const float * GGML_RESTRICT x, block_q4_0 * GGML_RESTRICT y, int64_t k) { static const int qk = QK4_0; @@ -246,6 +257,53 @@ void quantize_row_q8_1_ref(const float * GGML_RESTRICT x, block_q8_1 * GGML_REST } } +static inline int best_index_mxfp4(float x, float e) { + int best_index = 0; + float best_err = fabsf(kvalues_mxfp4[0]*e - x); + for (int i = 1; i < 16; i++) { + float err = fabsf(kvalues_mxfp4[i]*e - x); + if (err < best_err) { + best_index = i; + best_err = err; + } + } + return best_index; +} + +void quantize_row_mxfp4_ref(const float * GGML_RESTRICT x, block_mxfp4 * GGML_RESTRICT y, int64_t k) { + static const int qk = QK_MXFP4; + + assert(k % qk == 0); + + const int nb = k / qk; + + for (int i = 0; i < nb; i++) { + float amax = 0.0f; // absolute max + + for (int j = 0; j < qk; j++) { + const float v = x[i*qk + j]; + + if (amax < fabsf(v)) { + amax = fabsf(v); + } + } + + const uint8_t e = amax > 0.0f ? (uint8_t) (floorf(log2f(amax)) - 2 + 127) : 0; + + const float d = GGML_E8M0_TO_FP32_HALF(e); + + y[i].e = e; + + for (int j = 0; j < qk/2; ++j) { + const uint8_t x0 = best_index_mxfp4(x[i*qk + 0 + j], d); + const uint8_t x1 = best_index_mxfp4(x[i*qk + qk/2 + j], d); + + y[i].qs[j] = x0; + y[i].qs[j] |= x1 << 4; + } + } +} + void dequantize_row_q4_0(const block_q4_0 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k) { static const int qk = QK4_0; @@ -356,6 +414,26 @@ void dequantize_row_q8_0(const block_q8_0 * GGML_RESTRICT x, float * GGML_RESTRI } } +void dequantize_row_mxfp4(const block_mxfp4 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k) { + static const int qk = QK_MXFP4; + + assert(k % qk == 0); + + const int nb = k / qk; + + for (int i = 0; i < nb; i++) { + const float d = GGML_E8M0_TO_FP32_HALF(x[i].e); + + for (int j = 0; j < qk/2; ++j) { + const int8_t x0 = kvalues_mxfp4[x[i].qs[j] & 0x0F]; + const int8_t x1 = kvalues_mxfp4[x[i].qs[j] >> 4]; + + y[i*qk + j + 0 ] = x0*d; + y[i*qk + j + qk/2] = x1*d; + } + } +} + // // 2-6 bit quantization in super-blocks // @@ -2014,6 +2092,12 @@ size_t quantize_q8_0(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, return nrow * row_size; } +size_t quantize_mxfp4(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrow, int64_t n_per_row, const float * quant_weights) { + GGML_UNUSED(quant_weights); + quantize_row_mxfp4_ref(src, dst, (int64_t)nrow*n_per_row); + return nrow * ggml_row_size(GGML_TYPE_MXFP4, n_per_row); +} + // ====================== Ternary (de)-quantization (BitNet b1.58 and TriLMs) void quantize_row_tq1_0_ref(const float * GGML_RESTRICT x, block_tq1_0 * GGML_RESTRICT y, int64_t k) { @@ -4551,17 +4635,6 @@ size_t quantize_iq1_m(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, // ============================ 4-bit non-linear quants -static inline int best_index_int8(int n, const int8_t * val, float x) { - if (x <= val[0]) return 0; - if (x >= val[n-1]) return n-1; - int ml = 0, mu = n-1; - while (mu-ml > 1) { - int mav = (ml+mu)/2; - if (x < val[mav]) mu = mav; else ml = mav; - } - return x - val[mu-1] < val[mu] - x ? mu-1 : mu; -} - static void quantize_row_iq4_nl_impl(const int super_block_size, const int block_size, const float * GGML_RESTRICT x, ggml_fp16_t * dh, uint8_t * q4, uint16_t * scales_h, uint8_t * scales_l, float * scales, float * weight, uint8_t * L, @@ -4961,6 +5034,15 @@ static bool validate_fp16(ggml_fp16_t f, size_t i) { return true; } +static bool validate_e_e8m0(uint8_t e, size_t i) { + if (e == 0xff) { + fprintf(stderr, "ggml_validate_row_data: found invalid e value %d at block %zu\n", e, i); + return false; + } + + return true; +} + #define VALIDATE_ROW_DATA_D_F16_IMPL(type, data, nb) \ const type * q = (const type *) (data); \ for (size_t i = 0; i < (nb); ++i) { \ @@ -4977,6 +5059,14 @@ static bool validate_fp16(ggml_fp16_t f, size_t i) { } \ } +#define VALIDATE_ROW_DATA_E_E8M0_IMPL(type, data, nb) \ + const type * q = (const type *) (data); \ + for (size_t i = 0; i < (nb); ++i) { \ + if (!validate_e_e8m0(q[i].e, i)) { \ + return false; \ + } \ + } + #define VALIDATE_ROW_DATA_DVEC_F16_IMPL(type, data, nb, nr) \ const type * q = (const type *) (data); \ for (size_t i = 0; i < (nb); ++i) { \ @@ -5130,6 +5220,10 @@ bool ggml_validate_row_data(enum ggml_type type, const void * data, size_t nbyte { VALIDATE_ROW_DATA_D_F16_IMPL(block_q8_0, data, nb); } break; + case GGML_TYPE_MXFP4: + { + VALIDATE_ROW_DATA_E_E8M0_IMPL(block_mxfp4, data, nb); + } break; case GGML_TYPE_Q2_K: { VALIDATE_ROW_DATA_DM_F16_IMPL(block_q2_K, data, nb, d, dmin); diff --git a/ggml/src/ggml-quants.h b/ggml/src/ggml-quants.h index d09173e111..3b688f31c2 100644 --- a/ggml/src/ggml-quants.h +++ b/ggml/src/ggml-quants.h @@ -21,6 +21,8 @@ GGML_API void quantize_row_q5_1_ref(const float * GGML_RESTRICT x, block_q5_1 * GGML_API void quantize_row_q8_0_ref(const float * GGML_RESTRICT x, block_q8_0 * GGML_RESTRICT y, int64_t k); GGML_API void quantize_row_q8_1_ref(const float * GGML_RESTRICT x, block_q8_1 * GGML_RESTRICT y, int64_t k); +GGML_API void quantize_row_mxfp4_ref(const float * GGML_RESTRICT x, block_mxfp4 * GGML_RESTRICT y, int64_t k); + GGML_API void quantize_row_q2_K_ref(const float * GGML_RESTRICT x, block_q2_K * GGML_RESTRICT y, int64_t k); GGML_API void quantize_row_q3_K_ref(const float * GGML_RESTRICT x, block_q3_K * GGML_RESTRICT y, int64_t k); GGML_API void quantize_row_q4_K_ref(const float * GGML_RESTRICT x, block_q4_K * GGML_RESTRICT y, int64_t k); @@ -45,6 +47,8 @@ GGML_API void dequantize_row_q5_1(const block_q5_1 * GGML_RESTRICT x, float * GG GGML_API void dequantize_row_q8_0(const block_q8_0 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); //GGML_API void dequantize_row_q8_1(const block_q8_1 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); +GGML_API void dequantize_row_mxfp4(const block_mxfp4 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); + GGML_API void dequantize_row_q2_K(const block_q2_K * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); GGML_API void dequantize_row_q3_K(const block_q3_K * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); GGML_API void dequantize_row_q4_K(const block_q4_K * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); @@ -90,6 +94,8 @@ GGML_API size_t quantize_q5_0(const float * GGML_RESTRICT src, void * GGML_RESTR GGML_API size_t quantize_q5_1(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); GGML_API size_t quantize_q8_0(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); +GGML_API size_t quantize_mxfp4(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); + GGML_API void iq2xs_init_impl(enum ggml_type type); GGML_API void iq2xs_free_impl(enum ggml_type type); GGML_API void iq3xs_init_impl(int grid_size); diff --git a/ggml/src/ggml-rpc/ggml-rpc.cpp b/ggml/src/ggml-rpc/ggml-rpc.cpp index f468f796d5..e84ff93efc 100644 --- a/ggml/src/ggml-rpc/ggml-rpc.cpp +++ b/ggml/src/ggml-rpc/ggml-rpc.cpp @@ -29,9 +29,12 @@ #include #include #include +#include namespace fs = std::filesystem; +static constexpr size_t MAX_CHUNK_SIZE = 1024ull * 1024ull * 1024ull; // 1 GiB + #ifdef _WIN32 typedef SOCKET sockfd_t; using ssize_t = __int64; @@ -323,11 +326,14 @@ static std::shared_ptr create_server_socket(const char * host, int por static bool send_data(sockfd_t sockfd, const void * data, size_t size) { size_t bytes_sent = 0; while (bytes_sent < size) { - ssize_t n = send(sockfd, (const char *)data + bytes_sent, size - bytes_sent, 0); + size_t size_to_send = std::min(size - bytes_sent, MAX_CHUNK_SIZE); + ssize_t n = send(sockfd, (const char *)data + bytes_sent, size_to_send, 0); if (n < 0) { + GGML_LOG_ERROR("send failed (bytes_sent=%zu, size_to_send=%zu)\n", + bytes_sent, size_to_send); return false; } - bytes_sent += n; + bytes_sent += (size_t)n; } return true; } @@ -335,11 +341,18 @@ static bool send_data(sockfd_t sockfd, const void * data, size_t size) { static bool recv_data(sockfd_t sockfd, void * data, size_t size) { size_t bytes_recv = 0; while (bytes_recv < size) { - ssize_t n = recv(sockfd, (char *)data + bytes_recv, size - bytes_recv, 0); - if (n <= 0) { + size_t size_to_recv = std::min(size - bytes_recv, MAX_CHUNK_SIZE); + ssize_t n = recv(sockfd, (char *)data + bytes_recv, size_to_recv, 0); + if (n < 0) { + GGML_LOG_ERROR("recv failed (bytes_recv=%zu, size_to_recv=%zu)\n", + bytes_recv, size_to_recv); return false; } - bytes_recv += n; + if (n == 0) { + GGML_LOG_ERROR("recv returned 0 (peer closed?)\n"); + return false; + } + bytes_recv += (size_t)n; } return true; } @@ -823,10 +836,10 @@ ggml_backend_t ggml_backend_rpc_init(const char * endpoint) { }; ggml_backend_t backend = new ggml_backend { - /* .guid = */ ggml_backend_rpc_guid(), - /* .interface = */ ggml_backend_rpc_interface, - /* .device = */ ggml_backend_rpc_add_device(endpoint), - /* .context = */ ctx + /* .guid = */ ggml_backend_rpc_guid(), + /* .iface = */ ggml_backend_rpc_interface, + /* .device = */ ggml_backend_rpc_add_device(endpoint), + /* .context = */ ctx }; return backend; } @@ -1055,7 +1068,7 @@ bool rpc_server::set_tensor(const std::vector & input) { GGML_ASSERT(ctx_ptr != nullptr); ggml_context * ctx = ctx_ptr.get(); ggml_tensor * tensor = deserialize_tensor(ctx, in_tensor); - if (tensor == nullptr) { + if (tensor == nullptr || tensor->buffer == nullptr) { GGML_LOG_ERROR("[%s] error deserializing tensor\n", __func__); return false; } @@ -1124,7 +1137,7 @@ bool rpc_server::set_tensor_hash(const rpc_msg_set_tensor_hash_req & request, rp GGML_ASSERT(ctx_ptr != nullptr); ggml_context * ctx = ctx_ptr.get(); ggml_tensor * tensor = deserialize_tensor(ctx, &request.tensor); - if (tensor == nullptr) { + if (tensor == nullptr || tensor->buffer == nullptr) { GGML_LOG_ERROR("[%s] error deserializing tensor\n", __func__); return false; } @@ -1192,7 +1205,7 @@ bool rpc_server::get_tensor(const rpc_msg_get_tensor_req & request, std::vector< GGML_ASSERT(ctx_ptr != nullptr); ggml_context * ctx = ctx_ptr.get(); ggml_tensor * tensor = deserialize_tensor(ctx, &request.tensor); - if (tensor == nullptr) { + if (tensor == nullptr || tensor->buffer == nullptr) { GGML_LOG_ERROR("[%s] error deserializing tensor\n", __func__); return false; } @@ -1229,7 +1242,7 @@ bool rpc_server::copy_tensor(const rpc_msg_copy_tensor_req & request, rpc_msg_co ggml_tensor * src = deserialize_tensor(ctx, &request.src); ggml_tensor * dst = deserialize_tensor(ctx, &request.dst); - if (src == nullptr || dst == nullptr) { + if (src == nullptr || dst == nullptr || src->buffer == nullptr || dst->buffer == nullptr) { GGML_LOG_ERROR("[%s] error deserializing tensors\n", __func__); return false; } diff --git a/ggml/src/ggml-sycl/backend.hpp b/ggml/src/ggml-sycl/backend.hpp index f839a42bc9..410a67b019 100644 --- a/ggml/src/ggml-sycl/backend.hpp +++ b/ggml/src/ggml-sycl/backend.hpp @@ -28,6 +28,7 @@ #include "mmvq.hpp" #include "norm.hpp" #include "outprod.hpp" +#include "quantize.hpp" #include "quants.hpp" #include "rope.hpp" #include "set_rows.hpp" diff --git a/ggml/src/ggml-sycl/cpy.cpp b/ggml/src/ggml-sycl/cpy.cpp index 1ffd7f1226..3d321b58ac 100644 --- a/ggml/src/ggml-sycl/cpy.cpp +++ b/ggml/src/ggml-sycl/cpy.cpp @@ -1,31 +1,12 @@ #include "cpy.hpp" #include -#include #include "dequantize.hpp" #include "ggml-sycl/common.hpp" #include "ggml-sycl/presets.hpp" #include "ggml.h" -static __dpct_inline__ int best_index_int8(int n, const int8_t * val, float x) { - if (x <= val[0]) { - return 0; - } - if (x >= val[n - 1]) { - return n - 1; - } - int ml = 0, mu = n - 1; - while (mu - ml > 1) { - int mav = (ml + mu) / 2; - if (x < val[mav]) { - mu = mav; - } else { - ml = mav; - } - } - return x - val[mu - 1] < val[mu] - x ? mu - 1 : mu; -} static void cpy_1_f32_f32(const char * cxi, char * cdsti) { const float * xi = (const float *) cxi; @@ -97,28 +78,6 @@ static void cpy_f32_f16(const char * cx, char * cdst, const int ne, const int ne cpy_1(cx + x_offset, cdst + dst_offset); } -static void cpy_blck_f32_q8_0(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q8_0 * dsti = (block_q8_0 *) cdsti; - - float amax = 0.0f; // absolute max - - for (int j = 0; j < QK8_0; j++) { - const float v = xi[j]; - amax = sycl::fmax(amax, sycl::fabs((float) v)); - } - - const float d = amax / ((1 << 7) - 1); - const float id = d ? 1.0f / d : 0.0f; - - dsti->d = d; - - for (int j = 0; j < QK8_0; ++j) { - const float x0 = xi[j] * id; - - dsti->qs[j] = sycl::round((float) x0); - } -} /* quantized type same copy */ template @@ -140,178 +99,7 @@ static void cpy_blck_q8_0_f32(const char * cxi, char * cdsti) { } } -static void cpy_blck_f32_q4_0(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q4_0 * dsti = (block_q4_0 *) cdsti; - float amax = 0.0f; - float vmax = 0.0f; - - for (int j = 0; j < QK4_0; ++j) { - const float v = xi[j]; - if (amax < sycl::fabs((float) v)) { - amax = sycl::fabs((float) v); - vmax = v; - } - } - - const float d = vmax / -8; - const float id = d ? 1.0f / d : 0.0f; - - dsti->d = d; - - for (int j = 0; j < QK4_0 / 2; ++j) { - const float x0 = xi[0 + j] * id; - const float x1 = xi[QK4_0 / 2 + j] * id; - - const uint8_t xi0 = dpct::min(15, (int8_t) (x0 + 8.5f)); - const uint8_t xi1 = dpct::min(15, (int8_t) (x1 + 8.5f)); - - dsti->qs[j] = xi0; - dsti->qs[j] |= xi1 << 4; - } -} - -static void cpy_blck_f32_q4_1(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q4_1 * dsti = (block_q4_1 *) cdsti; - - float vmin = FLT_MAX; - float vmax = -FLT_MAX; - - for (int j = 0; j < QK4_1; ++j) { - const float v = xi[j]; - - if (v < vmin) { - vmin = v; - } - if (v > vmax) { - vmax = v; - } - } - - const float d = (vmax - vmin) / ((1 << 4) - 1); - const float id = d ? 1.0f / d : 0.0f; - - dsti->dm.x() = d; - dsti->dm.y() = vmin; - - for (int j = 0; j < QK4_1 / 2; ++j) { - const float x0 = (xi[0 + j] - vmin) * id; - const float x1 = (xi[QK4_1 / 2 + j] - vmin) * id; - - const uint8_t xi0 = dpct::min(15, (int8_t) (x0 + 0.5f)); - const uint8_t xi1 = dpct::min(15, (int8_t) (x1 + 0.5f)); - - dsti->qs[j] = xi0; - dsti->qs[j] |= xi1 << 4; - } -} - -static void cpy_blck_f32_q5_0(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q5_0 * dsti = (block_q5_0 *) cdsti; - - float amax = 0.0f; - float vmax = 0.0f; - - for (int j = 0; j < QK5_0; ++j) { - const float v = xi[j]; - if (amax < sycl::fabs((float) v)) { - amax = sycl::fabs((float) v); - vmax = v; - } - } - - const float d = vmax / -16; - const float id = d ? 1.0f / d : 0.0f; - - dsti->d = d; - - uint32_t qh = 0; - for (int j = 0; j < QK5_0 / 2; ++j) { - const float x0 = xi[0 + j] * id; - const float x1 = xi[QK5_0 / 2 + j] * id; - - const uint8_t xi0 = dpct::min(31, (int8_t) (x0 + 16.5f)); - const uint8_t xi1 = dpct::min(31, (int8_t) (x1 + 16.5f)); - - dsti->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); - qh |= ((xi0 & 0x10u) >> 4) << (j + 0); - qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_0 / 2); - } - memcpy(dsti->qh, &qh, sizeof(qh)); -} - -static void cpy_blck_f32_q5_1(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q5_1 * dsti = (block_q5_1 *) cdsti; - - float min = xi[0]; - float max = xi[0]; - - for (int j = 1; j < QK5_1; ++j) { - const float v = xi[j]; - min = v < min ? v : min; - max = v > max ? v : max; - } - - const float d = (max - min) / 31; - const float id = d ? 1.0f / d : 0.0f; - - dsti->dm.x() = d; - dsti->dm.y() = min; - - uint32_t qh = 0; - for (int j = 0; j < QK5_1 / 2; ++j) { - const float x0 = (xi[0 + j] - min) * id; - const float x1 = (xi[QK5_1 / 2 + j] - min) * id; - - const uint8_t xi0 = (uint8_t) (x0 + 0.5f); - const uint8_t xi1 = (uint8_t) (x1 + 0.5f); - - dsti->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); - qh |= ((xi0 & 0x10u) >> 4) << (j + 0); - qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_1 / 2); - } - memcpy(dsti->qh, &qh, sizeof(qh)); -} - -static void cpy_blck_f32_iq4_nl(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_iq4_nl * dsti = (block_iq4_nl *) cdsti; - - float amax = 0.0f; - float vmax = 0.0f; - - for (int j = 0; j < QK4_NL; ++j) { - const float v = xi[j]; - if (amax < sycl::fabs((float) v)) { - amax = sycl::fabs((float) v); - vmax = v; - } - } - - float d = vmax / kvalues_iq4nl[0]; - const float id = d ? 1.0f / d : 0.0f; - - float sumqx = 0, sumq2 = 0; - for (int j = 0; j < QK4_NL / 2; ++j) { - const float x0 = xi[0 + j] * id; - const float x1 = xi[QK4_NL / 2 + j] * id; - const uint8_t xi0 = best_index_int8(16, kvalues_iq4nl, x0); - const uint8_t xi1 = best_index_int8(16, kvalues_iq4nl, x1); - dsti->qs[j] = xi0 | (xi1 << 4); - const float v0 = kvalues_iq4nl[xi0]; - const float v1 = kvalues_iq4nl[xi1]; - const float w0 = xi[0 + j] * xi[0 + j]; - const float w1 = xi[QK4_NL / 2 + j] * xi[QK4_NL / 2 + j]; - sumqx += w0 * v0 * xi[j] + w1 * v1 * xi[QK4_NL / 2 + j]; - sumq2 += w0 * v0 * v0 + w1 * v1 * v1; - } - - dsti->d = sumq2 > 0 ? sumqx / sumq2 : d; -} template static void cpy_blck_q_f32(const char * cxi, char * cdsti) { float * cdstf = (float *) (cdsti); diff --git a/ggml/src/ggml-sycl/cpy.hpp b/ggml/src/ggml-sycl/cpy.hpp index 0a0f561d23..3c331f1ef2 100644 --- a/ggml/src/ggml-sycl/cpy.hpp +++ b/ggml/src/ggml-sycl/cpy.hpp @@ -2,10 +2,222 @@ #define GGML_SYCL_CPY_HPP #include "common.hpp" +#include typedef void (*cpy_kernel_t)(const char * cx, char * cdst); +__dpct_inline__ int best_index_int8(int n, const int8_t * val, float x) { + if (x <= val[0]) { + return 0; + } + if (x >= val[n - 1]) { + return n - 1; + } + int ml = 0, mu = n - 1; + while (mu - ml > 1) { + int mav = (ml + mu) / 2; + if (x < val[mav]) { + mu = mav; + } else { + ml = mav; + } + } + return x - val[mu - 1] < val[mu] - x ? mu - 1 : mu; +} + +inline void cpy_blck_f32_q8_0(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_q8_0 * dsti = (block_q8_0 *) cdsti; + + float amax = 0.0f; // absolute max + + for (int j = 0; j < QK8_0; j++) { + const float v = xi[j]; + amax = sycl::fmax(amax, sycl::fabs((float) v)); + } + + const float d = amax / ((1 << 7) - 1); + const float id = d ? 1.0f / d : 0.0f; + + dsti->d = d; + + for (int j = 0; j < QK8_0; ++j) { + const float x0 = xi[j] * id; + + dsti->qs[j] = sycl::round((float) x0); + } +} + +inline void cpy_blck_f32_q4_0(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_q4_0 * dsti = (block_q4_0 *) cdsti; + + float amax = 0.0f; + float vmax = 0.0f; + + for (int j = 0; j < QK4_0; ++j) { + const float v = xi[j]; + if (amax < sycl::fabs((float) v)) { + amax = sycl::fabs((float) v); + vmax = v; + } + } + + const float d = vmax / -8; + const float id = d ? 1.0f / d : 0.0f; + + dsti->d = d; + + for (int j = 0; j < QK4_0 / 2; ++j) { + const float x0 = xi[0 + j] * id; + const float x1 = xi[QK4_0 / 2 + j] * id; + + const uint8_t xi0 = dpct::min(15, (int8_t) (x0 + 8.5f)); + const uint8_t xi1 = dpct::min(15, (int8_t) (x1 + 8.5f)); + + dsti->qs[j] = xi0; + dsti->qs[j] |= xi1 << 4; + } +} + +inline void cpy_blck_f32_q4_1(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_q4_1 * dsti = (block_q4_1 *) cdsti; + + float vmin = FLT_MAX; + float vmax = -FLT_MAX; + + for (int j = 0; j < QK4_1; ++j) { + const float v = xi[j]; + + vmin = sycl::min(v, vmin); + vmax = sycl::max(v, vmax); + } + + const float d = (vmax - vmin) / ((1 << 4) - 1); + const float id = d ? 1.0f / d : 0.0f; + + dsti->dm.x() = d; + dsti->dm.y() = vmin; + + for (int j = 0; j < QK4_1 / 2; ++j) { + const float x0 = (xi[0 + j] - vmin) * id; + const float x1 = (xi[QK4_1 / 2 + j] - vmin) * id; + + const uint8_t xi0 = dpct::min(15, (int8_t) (x0 + 0.5f)); + const uint8_t xi1 = dpct::min(15, (int8_t) (x1 + 0.5f)); + + dsti->qs[j] = xi0; + dsti->qs[j] |= xi1 << 4; + } +} + +inline void cpy_blck_f32_q5_0(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_q5_0 * dsti = (block_q5_0 *) cdsti; + + float amax = 0.0f; + float vmax = 0.0f; + + for (int j = 0; j < QK5_0; ++j) { + const float v = xi[j]; + if (amax < sycl::fabs((float) v)) { + amax = sycl::fabs((float) v); + vmax = v; + } + } + + const float d = vmax / -16; + const float id = d ? 1.0f / d : 0.0f; + + dsti->d = d; + + uint32_t qh = 0; + for (int j = 0; j < QK5_0 / 2; ++j) { + const float x0 = xi[0 + j] * id; + const float x1 = xi[QK5_0 / 2 + j] * id; + + const uint8_t xi0 = dpct::min(31, (int8_t) (x0 + 16.5f)); + const uint8_t xi1 = dpct::min(31, (int8_t) (x1 + 16.5f)); + + dsti->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); + qh |= ((xi0 & 0x10u) >> 4) << (j + 0); + qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_0 / 2); + } + memcpy(dsti->qh, &qh, sizeof(qh)); +} + +inline void cpy_blck_f32_q5_1(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_q5_1 * dsti = (block_q5_1 *) cdsti; + + float min = xi[0]; + float max = xi[0]; + + for (int j = 1; j < QK5_1; ++j) { + const float v = xi[j]; + min = v < min ? v : min; + max = v > max ? v : max; + } + + const float d = (max - min) / 31; + const float id = d ? 1.0f / d : 0.0f; + + dsti->dm.x() = d; + dsti->dm.y() = min; + + uint32_t qh = 0; + for (int j = 0; j < QK5_1 / 2; ++j) { + const float x0 = (xi[0 + j] - min) * id; + const float x1 = (xi[QK5_1 / 2 + j] - min) * id; + + const uint8_t xi0 = (uint8_t) (x0 + 0.5f); + const uint8_t xi1 = (uint8_t) (x1 + 0.5f); + + dsti->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); + qh |= ((xi0 & 0x10u) >> 4) << (j + 0); + qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_1 / 2); + } + memcpy(dsti->qh, &qh, sizeof(qh)); +} + +inline void cpy_blck_f32_iq4_nl(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_iq4_nl * dsti = (block_iq4_nl *) cdsti; + + float amax = 0.0f; + float vmax = 0.0f; + + for (int j = 0; j < QK4_NL; ++j) { + const float v = xi[j]; + if (amax < sycl::fabs((float) v)) { + amax = sycl::fabs((float) v); + vmax = v; + } + } + + float d = vmax / kvalues_iq4nl[0]; + const float id = d ? 1.0f / d : 0.0f; + + float sumqx = 0, sumq2 = 0; + for (int j = 0; j < QK4_NL / 2; ++j) { + const float x0 = xi[0 + j] * id; + const float x1 = xi[QK4_NL / 2 + j] * id; + const uint8_t xi0 = best_index_int8(16, kvalues_iq4nl, x0); + const uint8_t xi1 = best_index_int8(16, kvalues_iq4nl, x1); + dsti->qs[j] = xi0 | (xi1 << 4); + const float v0 = kvalues_iq4nl[xi0]; + const float v1 = kvalues_iq4nl[xi1]; + const float w0 = xi[0 + j] * xi[0 + j]; + const float w1 = xi[QK4_NL / 2 + j] * xi[QK4_NL / 2 + j]; + sumqx += w0 * v0 * xi[j] + w1 * v1 * xi[QK4_NL / 2 + j]; + sumq2 += w0 * v0 * v0 + w1 * v1 * v1; + } + + dsti->d = sumq2 > 0 ? sumqx / sumq2 : d; +} + void ggml_sycl_cpy(ggml_backend_sycl_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1); void ggml_sycl_dup(ggml_backend_sycl_context & ctx, ggml_tensor * dst); -#endif // GGML_SYCL_CPY_HPP +#endif // GGML_SYCL_CPY_HPP diff --git a/ggml/src/ggml-sycl/ggml-sycl.cpp b/ggml/src/ggml-sycl/ggml-sycl.cpp index 872eb4b052..a0a650e92e 100644 --- a/ggml/src/ggml-sycl/ggml-sycl.cpp +++ b/ggml/src/ggml-sycl/ggml-sycl.cpp @@ -44,6 +44,7 @@ #include "ggml-sycl/set_rows.hpp" #include "ggml-sycl/sycl_hw.hpp" #include "ggml-sycl/getrows.hpp" +#include "ggml-sycl/quantize.hpp" #include "ggml.h" static bool g_sycl_loaded = false; @@ -1373,120 +1374,6 @@ typedef void (*ggml_sycl_op_mul_mat_t)( -template -static void quantize_q8_1(const float * __restrict__ x, void * __restrict__ vy, const int kx, const int kx_padded, - const sycl::nd_item<3> &item_ct1) { - const int ix = (item_ct1.get_local_range(2) * item_ct1.get_group(2) + - item_ct1.get_local_id(2)) * QUANT_BLOCK_TILE; - - if (ix >= kx_padded) { - return; - } - - const int iy = item_ct1.get_local_range(1) * item_ct1.get_group(1) + - item_ct1.get_local_id(1); - - const int i_padded = iy*kx_padded + ix; - - block_q8_1 * y = (block_q8_1 *) vy; - - const int ib = i_padded / QK8_1; // block index - const int iqs = i_padded % QK8_1; // quant index - typedef sycl::vec TC; - typedef sycl::vec TQ; - TC zeros; - TQ qzeros; -#pragma unroll - for (int i = 0; i < QUANT_BLOCK_TILE; i++) - { - zeros[i] = 0.f; - qzeros[i] = 0; - } - const TC xi = ix < kx ? *(const TC *)&x[iy * kx + ix] : zeros; - float sum = xi[0]; - float amax = sycl::fabs(xi[0]); -#pragma unroll - for (int i = 1; i < QUANT_BLOCK_TILE; i++) - { - sum += xi[i]; - amax = sycl::fmax(sycl::fabs(xi[i]), amax); - } - sum = warp_reduce_sum(sum, item_ct1); - amax = warp_reduce_max(amax, item_ct1); - - const float d = amax / 127; - TQ q = qzeros; - if (amax != 0.0f) - { -#pragma unroll - for (int i = 0; i < QUANT_BLOCK_TILE; i++) { - q[i] = sycl::round(xi[i] / d); - } - } - - *(TQ *)&y[ib].qs[iqs] = q; - - if (iqs > 0) { - return; - } - - reinterpret_cast(y[ib].ds.x()) = d; - reinterpret_cast(y[ib].ds.y()) = sum; -} - -template -static __dpct_inline__ void quantize_and_reorder_q8_1(const float * __restrict__ x, void * reordered_q8_tensor, - const int kx, const int kx_padded, const sycl::nd_item<1> & it) { - /* - Quantizes and reorders the resultant q8 tensor in a per row fashion - Each sub-group calculates one quant block. i.e. QK8_1 quant values and the d and sum values - */ - - auto subgroup_id = it.get_group(0); - auto wi_id = it.get_local_id(0); - - const int num_blocks_per_row = kx / QK8_1; - auto row = subgroup_id / num_blocks_per_row; - auto col = subgroup_id % num_blocks_per_row; - - auto row_offset = row * (kx_padded / QK8_1) * sizeof(block_q8_1); - auto col_offset = QK8_1 * col + wi_id * ElementsPerWI; - - auto quant_ptr = (int8_t *) ((char *) reordered_q8_tensor + row_offset + col_offset); - auto ds_ptr = (sycl::half2 *) ((char *) reordered_q8_tensor + row_offset + kx + col * sizeof(sycl::half2)); - - sycl::vec wi_f32_vals; - sycl::vec quantized_values; - - auto float_ptr_offset = subgroup_id * QK8_1 + ElementsPerWI * wi_id; - wi_f32_vals = *reinterpret_cast *>(x + float_ptr_offset); - - float sum = 0.0f; - float amax = 0.0f; - -#pragma unroll(ElementsPerWI) - for (int i = 0; i < ElementsPerWI; i++) { - sum += wi_f32_vals[i]; - amax = sycl::fmax(amax, sycl::fabs(wi_f32_vals[i])); - quantized_values[i] = 0; - } - sum = sycl::reduce_over_group(it.get_group(), sum, sycl::plus()); - amax = sycl::reduce_over_group(it.get_group(), amax, sycl::maximum()); - float d = amax == 0 ? 1 : amax / 127; - -#pragma unroll(ElementsPerWI) - for (int i = 0; i < ElementsPerWI; i++) { - quantized_values[i] = sycl::round(wi_f32_vals[i] / d); - } - - d = amax == 0 ? 0 : d; - - *reinterpret_cast *>(quant_ptr) = quantized_values; - if (wi_id == 0) { - *ds_ptr = sycl::half2(sycl::half(d), sycl::half(sum)); - } -} - static void mul_mat_p021_f16_f32( const void * __restrict__ vx, const float * __restrict__ y, float * __restrict__ dst, const int ncols_x, const int nrows_x, const int nchannels_x, const int nchannels_y, @@ -1770,32 +1657,6 @@ static void pool2d_nchw_kernel( o_ptr[cur_oh * ow + cur_ow] = res; } -static void quantize_row_q8_1_sycl(const float * x, void * vy, const int kx, const int ky, const int kx_padded, - bool reorder_q8_tensor, queue_ptr stream) { - if (reorder_q8_tensor) { - auto local_range = std::size_t(WARP_SIZE); - auto num_quant_blocks = ky * (kx / QK8_1); - auto global_range = num_quant_blocks * local_range; - stream->parallel_for(sycl::nd_range<1>({ global_range }, { local_range }), - [=](sycl::nd_item<1> it) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - quantize_and_reorder_q8_1(x, vy, kx, kx_padded, it); - }); - } else { - const int block_num_x = (kx_padded + SYCL_QUANTIZE_BLOCK_SIZE - 1) / SYCL_QUANTIZE_BLOCK_SIZE; - const sycl::range<3> num_blocks(1, ky, block_num_x); - int constexpr QUANT_BLOCK_TILE = QK8_1 / WARP_SIZE; - static_assert(QK8_1 % WARP_SIZE == 0); - const sycl::range<3> block_size(1, 1, SYCL_QUANTIZE_BLOCK_SIZE / QUANT_BLOCK_TILE); - { - dpct::has_capability_or_fail(stream->get_device(), { sycl::aspect::fp16 }); - - stream->parallel_for(sycl::nd_range<3>(num_blocks * block_size, block_size), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - quantize_q8_1(x, vy, kx, kx_padded, item_ct1); - }); - } - } -} static void ggml_mul_mat_p021_f16_f32_sycl(const void *vx, const float *y, float *dst, const int ncols_x, @@ -2372,10 +2233,10 @@ static void ggml_sycl_set_peer_access(const int n_tokens, int main_device) { peer_access_enabled = enable_peer_access; } +template